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hcs12 microcontrollers freescale.com mc9s12xs256 reference manual covers mc9s12xs family mc9s12xs256 mc9s12xs128 mc9s12xs64 mc9s12xs256rmv1 rev. 1.10 05/2010
to provide the most up-to-date information, the document revision on the world wide web is the most current. a printed copy may be an earlier revision. to verify you have the latest information available, refer to: http://freescale.com/ this document contains information for the complete s12xs family and thus includes a set of separate flash (ftmr) module sections to cover the whole family. a full list of family members and options is included in the appendices. this document contains information for all constituent modules, with the exception of the cpu. for cpu information please refer to cpu12xv1 in the cpu12/cpu12x reference manual. revision history date revision level description may, 2009 1.08 removed all kgd references corrected detailed register map (ferstat) corrected statement on vdda/vddx protection diodes september, 2009 1.09 updated chapter 8 s12xe clocks and reset generator (s12xecrgv1) updated chapter 14 serial communication interface (s12sciv5) updated chapter 16 timer module (tim16b8cv2) updated chapter 18 256 kbyte flash module (s12xftmr256k1v1) updated chapter 19 128 kbyte flash module (s12xftmr128k1v1) updated chapter 20 64 kbyte flash module (s12xftmr64k1v1) may, 2010 1.10 updated chapter 2 port integration module (s12xspimv1) updated chapter 16 timer module (tim16b8cv2) bdm alternate clock source de?ed in device overview
s12xs family reference manual, rev. 1.10 freescale semiconductor 3 chapter 1 device overview s12xs family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 chapter 2 port integration module (s12xspimv1) . . . . . . . . . . . . . . . . . . . . . . . . . . .59 chapter 3 memory mapping control (s12xmmcv4) . . . . . . . . . . . . . . . . . . . . . . . .127 chapter 4 interrupt (s12xintv2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .151 chapter 5 background debug module (s12xbdmv2) . . . . . . . . . . . . . . . . . . . . . . .167 chapter 6 s12x debug (s12xdbgv3) module . . . . . . . . . . . . . . . . . . . . . . . . . . . . .193 chapter 7 security (s12xs9secv2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .229 chapter 8 s12xe clocks and reset generator (s12xecrgv1) . . . . . . . . . . . . . . .235 chapter 9 pierce oscillator (s12xosclcpv2) . . . . . . . . . . . . . . . . . . . . . . . . . . . .265 chapter 10 analog-to-digital converter (adc12b16cv1) . . . . . . . . . . . . . . . . . . . . .269 chapter 11 freescale? scalable controller area network (s12mscanv3) . . . . . .295 chapter 12 periodic interrupt timer (s12pit24b4cv1) . . . . . . . . . . . . . . . . . . . . . . .349 chapter 13 pulse-width modulator (s12pwm8b8cv1) . . . . . . . . . . . . . . . . . . . . . . .365 chapter 14 serial communication interface (s12sciv5) . . . . . . . . . . . . . . . . . . . . . .397 chapter 15 serial peripheral interface (s12spiv5) . . . . . . . . . . . . . . . . . . . . . . . . . . .435 chapter 16 timer module (tim16b8cv2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .461 chapter 17 voltage regulator (s12vregl3v3v1) . . . . . . . . . . . . . . . . . . . . . . . . . . .489 chapter 18 256 kbyte flash module (s12xftmr256k1v1). . . . . . . . . . . . . . . . . . . .507 chapter 19 128 kbyte flash module (s12xftmr128k1v1). . . . . . . . . . . . . . . . . . . .557 chapter 20 64 kbyte flash module (s12xftmr64k1v1). . . . . . . . . . . . . . . . . . . . . .607 appendix a electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .657 appendix b package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .698 appendix c pcb layout guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .708 appendix d derivative differences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .712 appendix e detailed register address map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .713 appendix f ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .735
s12xs family reference manual, rev. 1.10 4 freescale semiconductor
s12xs family reference manual, rev. 1.10 freescale semiconductor 5 chapter 1 device overview s12xs family 1.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 1.1.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 1.1.2 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 1.1.3 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 1.1.4 device memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 1.1.5 address mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 1.1.6 detailed register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 1.1.7 part id assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 1.2 signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 1.2.1 device pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 1.2.2 pin assignment overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 1.2.3 detailed signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 1.2.4 power supply pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 1.3 system clock description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 1.4 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 1.4.1 chip con?uration summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 1.4.2 power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 1.4.3 freeze mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 1.5 security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 1.6 resets and interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 1.6.1 resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 1.6.2 vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 1.6.3 effects of reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 1.7 atd0 con?uration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 1.7.1 external trigger input connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 1.7.2 atd0 channel[17] connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 1.8 vreg con?uration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 1.8.1 temperature sensor con?uration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 1.9 bdm clock con?uration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 1.10 oscillator con?uration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 chapter 2 port integration module (s12xspimv1) 2.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 2.1.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 2.1.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 2.2 external signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 2.3 memory map and register de?ition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
s12xs family reference manual, rev. 1.10 6 freescale semiconductor 2.3.1 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 2.3.2 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73 2.3.3 port a data register (porta) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 2.3.4 port b data register (portb) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 2.3.5 port a data direction register (ddra) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 2.3.6 port b data direction register (ddrb) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 2.3.7 pim reserved registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 7 2.3.8 port e data register (porte) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 2.3.9 port e data direction register (ddre) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 2.3.10 ports abek, bkgd pin pull-up control register (pucr) . . . . . . . . . . . . . . . . . . . . . . 79 2.3.11 ports abek reduced drive register (rdriv) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 2.3.12 eclk control register (eclkctl) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 2.3.13 pim reserved register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 2.3.14 irq control register (irqcr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 2.3.15 pim reserved register pimtest . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 2.3.16 port k data register (portk) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 2.3.17 port k data direction register (ddrk) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 2.3.18 port t data register (ptt) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 5 2.3.19 port t input register (ptit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 6 2.3.20 port t data direction register (ddrt) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 2.3.21 port t reduced drive register (rdrt) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 2.3.22 port t pull device enable register (pert) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 2.3.23 port t polarity select register (ppst) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 2.3.24 pim reserved register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 2.3.25 port t routing register (pttrr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 2.3.26 port s data register (pts) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1 2.3.27 port s input register (ptis) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2 2.3.28 port s data direction register (ddrs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 2.3.29 port s reduced drive register (rdrs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 2.3.30 port s pull device enable register (pers) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 2.3.31 port s polarity select register (ppss) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 2.3.32 port s wired-or mode register (woms) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 2.3.33 pim reserved register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 2.3.34 port m data register (ptm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 2.3.35 port m input register (ptim) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 2.3.36 port m data direction register (ddrm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 2.3.37 port m reduced drive register (rdrm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 2.3.38 port m pull device enable register (perm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 2.3.39 port m polarity select register (ppsm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 2.3.40 port m wired-or mode register (womm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 2.3.41 module routing register (modrr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 2.3.42 port p data register (ptp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 2.3.43 port p input register (ptip) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 2.3.44 port p data direction register (ddrp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 2.3.45 port p reduced drive register (rdrp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
s12xs family reference manual, rev. 1.10 freescale semiconductor 7 2.3.46 port p pull device enable register (perp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 2.3.47 port p polarity select register (ppsp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 2.3.48 port p interrupt enable register (piep) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 2.3.49 port p interrupt flag register (pifp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 2.3.50 port h data register (pth) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 2.3.51 port h input register (ptih) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 2.3.52 port h data direction register (ddrh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 2.3.53 port h reduced drive register (rdrh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 2.3.54 port h pull device enable register (perh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 2.3.55 port h polarity select register (ppsh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 2.3.56 port h interrupt enable register (pieh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 2.3.57 port h interrupt flag register (pifh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 2.3.58 port j data register (ptj) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 12 2.3.59 port j input register (ptij) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3 2.3.60 port j data direction register (ddrj) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 2.3.61 port j reduced drive register (rdrj) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 2.3.62 port j pull device enable register (perj) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 2.3.63 port j polarity select register (ppsj) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 2.3.64 port j interrupt enable register (piej) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 2.3.65 port j interrupt flag register (pifj) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 2.3.66 port ad0 data register 0 (pt0ad0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 2.3.67 port ad0 data register 1 (pt1ad0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 2.3.68 port ad0 data direction register 0 (ddr0ad0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 2.3.69 port ad0 data direction register 1 (ddr1ad0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 2.3.70 port ad0 reduced drive register 0 (rdr0ad0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 2.3.71 port ad0 reduced drive register 1 (rdr1ad0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 2.3.72 port ad0 pull up enable register 0 (per0ad0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 2.3.73 port ad0 pull up enable register 1 (per1ad0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 2.3.74 pim reserved registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 0 2.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 2.4.1 general . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 2.4.2 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 2.4.3 pins and ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 2.4.4 pin interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 2.5 initialization information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 2.5.1 port data and data direction register writes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 chapter 3 memory mapping control (s12xmmcv4) 3.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 3.1.1 terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 3.1.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 3.1.3 s12x memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 3.1.4 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 29 3.1.5 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
s12xs family reference manual, rev. 1.10 8 freescale semiconductor 3.2 external signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 3.3 memory map and registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 3.3.1 module memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 3.3.2 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 3.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 3.4.1 mcu operating mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 3.4.2 memory map scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 3.4.3 chip bus control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 3.5 initialization/application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 3.5.1 call and rtc instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 chapter 4 interrupt (s12xintv2) 4.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 4.1.1 glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 4.1.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 4.1.3 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 53 4.1.4 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 4.2 external signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 4.3 memory map and register de?ition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 55 4.3.1 module memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 4.3.2 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 4.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 4.4.1 s12x exception requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 4.4.2 interrupt prioritization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 4.4.3 xgate requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 63 4.4.4 priority decoders . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 4.4.5 reset exception requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 4.4.6 exception priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 4.5 initialization/application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 4.5.1 initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 4.5.2 interrupt nesting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 4.5.3 wake up from stop or wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 chapter 5 background debug module (s12xbdmv2) 5.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 5.1.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 5.1.2 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 68 5.1.3 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 5.2 external signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 5.3 memory map and register de?ition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 70 5.3.1 module memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 5.3.2 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
s12xs family reference manual, rev. 1.10 freescale semiconductor 9 5.3.3 family id assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 5.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 5.4.1 security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 5.4.2 enabling and activating bdm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 5.4.3 bdm hardware commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 5.4.4 standard bdm firmware commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 5.4.5 bdm command structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 5.4.6 bdm serial interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 81 5.4.7 serial interface hardware handshake protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 5.4.8 hardware handshake abort procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 5.4.9 sync ?request timed reference pulse . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 5.4.10 instruction tracing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 5.4.11 serial communication time out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 chapter 6 s12x debug (s12xdbgv3) module 6.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 6.1.1 glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 6.1.2 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 6.1.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 6.1.4 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 95 6.1.5 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 6.2 external signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 6.3 memory map and registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 6.3.1 module memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 6.3.2 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 6.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 6.4.1 s12xdbg operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 6.4.2 comparator modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 14 6.4.3 trigger modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 6.4.4 state sequence control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 9 6.4.5 trace buffer operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 0 6.4.6 tagging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226 6.4.7 breakpoints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226 chapter 7 security (s12xs9secv2) 7.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 7.1.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 7.1.2 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 30 7.1.3 securing the microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230 7.1.4 operation of the secured microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231 7.1.5 unsecuring the microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233 7.1.6 reprogramming the security bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233
s12xs family reference manual, rev. 1.10 10 freescale semiconductor 7.1.7 complete memory erase (special modes) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234 chapter 8 s12xe clocks and reset generator (s12xecrgv1) 8.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235 8.1.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235 8.1.2 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 36 8.1.3 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236 8.2 signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 8.2.1 v ddpll , v sspll . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 8.2.2 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 8.3 memory map and registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238 8.3.1 module memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238 8.3.2 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239 8.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252 8.4.1 functional blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252 8.4.2 operation modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257 8.4.3 low power options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 8 8.5 resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260 8.5.1 description of reset operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261 8.6 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263 8.6.1 description of interrupt operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264 chapter 9 pierce oscillator (s12xosclcpv2) 9.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265 9.1.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265 9.1.2 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 65 9.1.3 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266 9.2 external signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266 9.2.1 v ddpll and v sspll ?operating and ground voltage pins . . . . . . . . . . . . . . . . . . . . 266 9.2.2 extal and xtal ?input and output pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266 9.3 memory map and register de?ition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 68 9.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268 9.4.1 gain control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268 9.4.2 clock monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268 9.4.3 wait mode operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 8 9.4.4 stop mode operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 8 chapter 10 analog-to-digital converter (adc12b16cv1) 10.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269 10.1.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269 10.1.2 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271
s12xs family reference manual, rev. 1.10 freescale semiconductor 11 10.1.3 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272 10.2 signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273 10.2.1 detailed signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273 10.3 memory map and register de?ition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273 10.3.1 module memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273 10.3.2 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276 10.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292 10.4.1 analog sub-block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292 10.4.2 digital sub-block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292 10.5 resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293 10.6 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294 chapter 11 freescale? scalable controller area network (s12mscanv3) 11.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295 11.1.1 glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296 11.1.2 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296 11.1.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297 11.1.4 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297 11.2 external signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298 11.2.1 rxcan ?can receiver input pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298 11.2.2 txcan ?can transmitter output pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298 11.2.3 can system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298 11.3 memory map and register de?ition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299 11.3.1 module memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299 11.3.2 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301 11.3.3 programmers model of message storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320 11.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331 11.4.1 general . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331 11.4.2 message storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331 11.4.3 identi?r acceptance filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 4 11.4.4 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 340 11.4.5 low-power options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 42 11.4.6 reset initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 346 11.4.7 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 346 11.5 initialization/application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 348 11.5.1 mscan initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 48 11.5.2 bus-off recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 348 chapter 12 periodic interrupt timer (s12pit24b4cv1) 12.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349 12.1.1 glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349 12.1.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349
s12xs family reference manual, rev. 1.10 12 freescale semiconductor 12.1.3 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349 12.1.4 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350 12.2 external signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350 12.3 register de?ition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 351 12.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 360 12.4.1 timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 360 12.4.2 interrupt interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 361 12.4.3 hardware trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 362 12.5 initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 362 12.5.1 startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 362 12.5.2 shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 362 12.5.3 flag clearing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 362 12.6 application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363 chapter 13 pulse-width modulator (s12pwm8b8cv1) 13.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 365 13.1.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 365 13.1.2 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 366 13.1.3 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 366 13.2 external signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 366 13.2.1 pwm7 ?pwm channel 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 367 13.2.2 pwm6 ?pwm channel 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 367 13.2.3 pwm5 ?pwm channel 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 367 13.2.4 pwm4 ?pwm channel 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 367 13.2.5 pwm3 ?pwm channel 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 367 13.2.6 pwm3 ?pwm channel 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 367 13.2.7 pwm3 ?pwm channel 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 367 13.2.8 pwm3 ?pwm channel 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 367 13.3 memory map and register de?ition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 367 13.3.1 module memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 367 13.3.2 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 368 13.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 383 13.4.1 pwm clock select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 383 13.4.2 pwm channel timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 386 13.5 resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 394 13.6 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 395 chapter 14 serial communication interface (s12sciv5) 14.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 397 14.1.1 glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 397 14.1.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 398 14.1.3 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 398
s12xs family reference manual, rev. 1.10 freescale semiconductor 13 14.1.4 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 399 14.2 external signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400 14.2.1 txd ?transmit pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 0 14.2.2 rxd ?receive pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 0 14.3 memory map and register de?ition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400 14.3.1 module memory map and register de?ition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400 14.3.2 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 401 14.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 413 14.4.1 infrared interface submodule . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 414 14.4.2 lin support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 414 14.4.3 data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 415 14.4.4 baud rate generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 16 14.4.5 transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 417 14.4.6 receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 422 14.4.7 single-wire operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 30 14.4.8 loop operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 431 14.5 initialization/application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 431 14.5.1 reset initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 431 14.5.2 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 431 14.5.3 interrupt operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 432 14.5.4 recovery from wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 434 14.5.5 recovery from stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 434 chapter 15 serial peripheral interface (s12spiv5) 15.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 435 15.1.1 glossary of terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 435 15.1.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 435 15.1.3 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 435 15.1.4 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 436 15.2 external signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 437 15.2.1 mosi ?master out/slave in pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 437 15.2.2 miso ?master in/slave out pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 437 15.2.3 ss ?slave select pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 438 15.2.4 sck ?serial clock pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 438 15.3 memory map and register de?ition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 438 15.3.1 module memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 438 15.3.2 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 439 15.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 447 15.4.1 master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 448 15.4.2 slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 449 15.4.3 transmission formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 50 15.4.4 spi baud rate generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 455 15.4.5 special features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 456 15.4.6 error conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 457
s12xs family reference manual, rev. 1.10 14 freescale semiconductor 15.4.7 low power mode options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 458 chapter 16 timer module (tim16b8cv2) 16.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 461 16.1.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 461 16.1.2 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 462 16.1.3 block diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 463 16.2 external signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 465 16.2.1 ioc7 ?input capture and output compare channel 7 pin . . . . . . . . . . . . . . . . . . . . 465 16.2.2 ioc6 ?input capture and output compare channel 6 pin . . . . . . . . . . . . . . . . . . . . 465 16.2.3 ioc5 ?input capture and output compare channel 5 pin . . . . . . . . . . . . . . . . . . . . 465 16.2.4 ioc4 ?input capture and output compare channel 4 pin . . . . . . . . . . . . . . . . . . . . 465 16.2.5 ioc3 ?input capture and output compare channel 3 pin . . . . . . . . . . . . . . . . . . . . 465 16.2.6 ioc2 ?input capture and output compare channel 2 pin . . . . . . . . . . . . . . . . . . . . 465 16.2.7 ioc1 ?input capture and output compare channel 1 pin . . . . . . . . . . . . . . . . . . . . 466 16.2.8 ioc0 ?input capture and output compare channel 0 pin . . . . . . . . . . . . . . . . . . . . 466 16.3 memory map and register de?ition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 466 16.3.1 module memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 466 16.3.2 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 466 16.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 483 16.4.1 prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 484 16.4.2 input capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 485 16.4.3 output compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 485 16.4.4 pulse accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 486 16.4.5 event counter mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 86 16.4.6 gated time accumulation mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 487 16.5 resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 487 16.6 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 487 16.6.1 channel [7:0] interrupt (c[7:0]f) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 488 16.6.2 pulse accumulator input interrupt (paovi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 488 16.6.3 pulse accumulator over?w interrupt (paovf) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 488 16.6.4 timer over?w interrupt (tof) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 488 chapter 17 voltage regulator (s12vregl3v3v1) 17.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 489 17.1.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 489 17.1.2 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 489 17.1.3 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 490 17.2 external signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 492 17.2.1 vddr ?regulator power input pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 492 17.2.2 vdda, vssa ?regulator reference supply pins . . . . . . . . . . . . . . . . . . . . . . . . . . . 492 17.2.3 vdd, vss ?regulator output1 (core logic) pins . . . . . . . . . . . . . . . . . . . . . . . . . . 492
s12xs family reference manual, rev. 1.10 freescale semiconductor 15 17.2.4 vddf ?regulator output2 (nvm logic) pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 493 17.2.5 vddpll, vsspll ?regulator output3 (pll) pins . . . . . . . . . . . . . . . . . . . . . . . . . 493 17.2.6 vddx ?power input pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 493 17.2.7 v regen optional regulator enable pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 493 17.2.8 v reg_api optional autonomous periodical interrupt output pin . . . . . . . . . . . . . . 493 17.3 memory map and register de?ition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 493 17.3.1 module memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 494 17.3.2 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 495 17.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 502 17.4.1 general . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 502 17.4.2 regulator core (reg) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 2 17.4.3 low-voltage detect (lvd) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 502 17.4.4 power-on reset (por) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 502 17.4.5 low-voltage reset (lvr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 502 17.4.6 htd - high temperature detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 503 17.4.7 regulator control (ctrl) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 503 17.4.8 autonomous periodical interrupt (api) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 503 17.4.9 resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 504 17.4.10description of reset operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 504 17.4.11interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 504 chapter 18 256 kbyte flash module (s12xftmr256k1v1) 18.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 507 18.1.1 glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 508 18.1.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 509 18.1.3 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 509 18.2 external signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 510 18.3 memory map and registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 510 18.3.1 module memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 511 18.3.2 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 514 18.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 535 18.4.1 flash command operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 535 18.4.2 flash command description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 540 18.4.3 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 553 18.4.4 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 554 18.4.5 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 554 18.5 security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 554 18.5.1 unsecuring the mcu using backdoor key access . . . . . . . . . . . . . . . . . . . . . . . . . . . . 554 18.5.2 unsecuring the mcu in special single chip mode using bdm . . . . . . . . . . . . . . . . . 555 18.5.3 mode and security effects on flash command availability . . . . . . . . . . . . . . . . . . . . . 556 18.6 initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 556
s12xs family reference manual, rev. 1.10 16 freescale semiconductor chapter 19 128 kbyte flash module (s12xftmr128k1v1) 19.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 557 19.1.1 glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 558 19.1.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 559 19.1.3 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 559 19.2 external signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 560 19.3 memory map and registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 560 19.3.1 module memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 561 19.3.2 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 564 19.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 585 19.4.1 flash command operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 585 19.4.2 flash command description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 590 19.4.3 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 603 19.4.4 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 604 19.4.5 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 604 19.5 security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 604 19.5.1 unsecuring the mcu using backdoor key access . . . . . . . . . . . . . . . . . . . . . . . . . . . . 604 19.5.2 unsecuring the mcu in special single chip mode using bdm . . . . . . . . . . . . . . . . . 605 19.5.3 mode and security effects on flash command availability . . . . . . . . . . . . . . . . . . . . . 606 19.6 initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 606 chapter 20 64 kbyte flash module (s12xftmr64k1v1) 20.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 607 20.1.1 glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 608 20.1.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 609 20.1.3 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 610 20.2 external signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 610 20.3 memory map and registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 611 20.3.1 module memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 611 20.3.2 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 615 20.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 635 20.4.1 flash command operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 635 20.4.2 flash command description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 640 20.4.3 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 653 20.4.4 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 654 20.4.5 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 654 20.5 security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 654 20.5.1 unsecuring the mcu using backdoor key access . . . . . . . . . . . . . . . . . . . . . . . . . . . . 655 20.5.2 unsecuring the mcu in special single chip mode using bdm . . . . . . . . . . . . . . . . . 655 20.5.3 mode and security effects on flash command availability . . . . . . . . . . . . . . . . . . . . . 656 20.6 initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 656
s12xs family reference manual, rev. 1.10 freescale semiconductor 17 appendix a electrical characteristics a.1 general . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 657 a.1.1 parameter classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 57 a.1.2 power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 657 a.1.3 pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 658 a.1.4 current injection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 659 a.1.5 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 659 a.1.6 esd protection and latch-up immunity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 660 a.1.7 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 661 a.1.8 power dissipation and thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 662 a.1.9 i/o characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 666 a.1.10 supply currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 669 a.2 atd characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 673 a.2.1 atd operating characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 673 a.2.2 factors influencing accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 673 a.2.3 atd accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 675 a.3 nvm, flash. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 679 a.3.1 timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 679 a.3.2 nvm reliability parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 683 a.4 voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 685 a.5 output loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 686 a.5.1 resistive loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 686 a.5.2 capacitive loads. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 686 a.5.3 chip power-up and voltage drops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 686 a.6 reset, oscillator and pll . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 688 a.6.1 startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 688 a.6.2 oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 690 a.6.3 phase locked loop. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 691 a.7 mscan. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 693 a.8 spi timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 694 a.8.1 master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 694 a.8.2 slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 696 appendix b package information b.1 112-pin lqfp mechanical dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 9 b.2 80-pin qfp mechanical dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 702 b.3 64-pin lqfp mechanical dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 05 appendix c pcb layout guidelines c.1 general . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 708 c.1.1 112-pin lqfp recommended pcb layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 709
s12xs family reference manual, rev. 1.10 18 freescale semiconductor c.1.2 80-pin qfp recommended pcb layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 710 c.1.3 64-pin lqfp recommended pcb layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 711 appendix d derivative differences d.1 memory sizes and package options s12xs family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 712 appendix e detailed register address map e.1 detailed register map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 713 appendix f ordering information f.1 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 735
s12xs family reference manual, rev. 1.10 freescale semiconductor 19 chapter 1 device overview s12xs family 1.1 introduction the new s12xs family of 16-bit micro controllers is a compatible, reduced version of the s12xe family. these families provide an easy approach to develop common platforms from low-end to high-end applications, minimizing the redesign of software and hardware. targeted at generic automotive applications and can nodes, some typical examples of these applications are: body controllers, occupant detection, door modules, rke receivers, smart actuators, lighting modules and smart junction boxes amongst many others. the s12xs family retains many of the features of the s12xe family including error correction code (ecc) on flash memory, a separate data-flash module for code or data storage, a frequency modulated locked loop (ipll) that improves the emc performance and a fast atd converter. s12xs family delivers 32-bit performance with all the advantages and ef?iencies of a 16-bit mcu while retaining the low cost, power consumption, emc and code-size ef?iency advantages currently enjoyed by users of freescales existing 16-bit s12 and s12x mcu families. like members of other s12x families, the s12xs family runs 16-bit wide accesses without wait states for all peripherals and memories. the s12xs family is available in 112-pin lqfp, 80-pin qfp, 64-pin lqfp package options and maintains a high level of pin compatibility with the s12xe family. in addition to the i/o ports available in each module, up to 18 further i/o ports are available with interrupt capability allowing wake-up from stop or wait modes. the peripheral set includes mscan, spi, two scis, an 8-channel 24-bit periodic interrupt timer, 8- channel 16-bit timer, 8-channel pwm and up to 16- channel 12-bit atd converter. software controlled peripheral-to-port routing enables access to a ?xible mix of the peripheral modules in the lower pin count package options. 1.1.1 features features of the s12xs family are listed here. please see table d-1 for memory options and table d-2 for the peripheral features that are available on the different family members. 16-bit cpu12x upward compatible with s12 instruction set with the exception of ve fuzzy instructions (mem, wav, wavr, rev, revw) which have been removed enhanced indexed addressing access to large data segments independent of ppage
device overview s12xs family s12xs family reference manual, rev. 1.10 20 freescale semiconductor int (interrupt module) seven levels of nested interrupts flexible assignment of interrupt sources to each interrupt level. external non-maskable high priority interrupt (xirq) the following inputs can act as wake-up interrupts irq and non-maskable xirq can receive pins sci receive pins depending on the package option up to 20 pins on ports j, h and p con?urable as rising or falling edge sensitive mmc (module mapping control) dbg (debug module) monitoring of cpu bus with tag-type or force-type breakpoint requests 64 x 64-bit circular trace buffer captures change-of-?w or memory access information bdm (background debug mode) osc_lcp (oscillator) low power loop control pierce oscillator utilizing a 4mhz to 16mhz crystal good noise immunity full-swing pierce option utilizing a 2mhz to 40mhz crystal transconductance sized for optimum start-up margin for typical crystals ipll (internally ?tered, frequency modulated phase-locked-loop clock generation) no external components required con?urable option to spread spectrum for reduced emc radiation (frequency modulation) crg (clock and reset generation) cop watchdog real time interrupt clock monitor fast wake up from stop in self clock mode memory options 64k, 128k and 256k byte flash flash general features 64 data bits plus 8 syndrome ecc (error correction code) bits allow single bit failure correction and double fault detection erase sector size 1024 bytes automated program and erase algorithm protection scheme to prevent accidental program or erase security option to prevent unauthorized access sense-amp margin level setting for reads 4k and 8k byte data flash space
device overview s12xs family s12xs family reference manual, rev. 1.10 freescale semiconductor 21 16 data bits plus 6 syndrome ecc (error correction code) bits allow single bit failure correction and double fault detection erase sector size 256 bytes automated program and erase algorithm 4k, 8k and 12k byte ram 16-channel, 12-bit analog-to-digital converter 8/10/12 bit resolution ? s, 10-bit single conversion time left or right justi?d result data external and internal conversion trigger capability internal oscillator for conversion in stop modes wake from low power modes on analog comparison > or <= match continuous conversion mode multiplexer for 16 analog input channels multiple channel scans pins can also be used as digital i/o mscan (1 m bit per second, can 2.0 a, b software compatible module) 1 mbit per second, can 2.0 a, b software compatible module standard and extended data frames 0 - 8 bytes data length programmable bit rate up to 1 mbps five receive buffers with fifo storage scheme three transmit buffers with internal prioritization flexible identi?r acceptance ?ter programmable as: 2 x 32-bit 4 x 16-bit 8 x 8-bit wake-up with integrated low pass ?ter option loop back for self test listen-only mode to monitor can bus bus-off recovery by software intervention or automatically 16-bit time stamp of transmitted/received messages tim (standard timer module) 8 x 16-bit channels for input capture or output compare 16-bit free-running counter with 8-bit precision prescaler 1 x 16-bit pulse accumulator pit (periodic interrupt timer) up to four timers with independent time-out periods time-out periods selectable between 1 and 2 24 bus clock cycles
device overview s12xs family s12xs family reference manual, rev. 1.10 22 freescale semiconductor time-out interrupt and peripheral triggers start of timers can be aligned up to 8 channel x 8-bit or 4 channel x 16-bit pulse width modulator programmable period and duty cycle per channel center- or left-aligned outputs programmable clock select logic with a wide range of frequencies serial peripheral interface module (spi) con?urable for 8 or 16-bit data size full-duplex or single-wire bidirectional double-buffered transmit and receive master or slave mode msb-?st or lsb-?st shifting serial clock phase and polarity options two serial communication interfaces (sci) full-duplex or single wire operation standard mark/space non-return-to-zero (nrz) format selectable irda 1.4 return-to-zero-inverted (rzi) format with programmable pulse widths 13-bit baud rate selection programmable character length programmable polarity for transmitter and receiver receive wakeup on active edge break detect and transmit collision detect supporting lin on-chip voltage regulator two parallel, linear voltage regulators with bandgap reference low-voltage detect (lvd) with low-voltage interrupt (lvi) power-on reset (por) circuit low-voltage reset (lvr) low-power wake-up timer (api) internal oscillator driving a down counter trimmable to +/-10% accuracy time-out periods range from 0.2ms to ~13s with a 0.2ms resolution input/output up to 91 general-purpose input/output (i/o) pins depending on the package option and 2 input- only pins hysteresis and con?urable pull up/pull down device on all input pins con?urable drive strength on all output pins package options 112-pin low-pro?e quad ?t-pack (lqfp) 80-pin quad ?t-pack (qfp)
device overview s12xs family s12xs family reference manual, rev. 1.10 freescale semiconductor 23 64-pin low-pro?e quad ?t-pack (lqfp) operating conditions wide single supply voltage range 3.135 v to 5.5 v at full performance separate supply for internal voltage regulator and i/o allow optimized emc ?tering 40mhz maximum cpu bus frequency ambient temperature range ?0 c to 125 c temperature options: ?0 c to 85 c ?0 c to 105 c ?0 c to 125 c 1.1.2 modes of operation operating modes: normal single-chip mode special single-chip mode with active background debug mode note this chip family does not support external bus modes. low-power modes: system stop modes pseudo stop mode full stop mode with fast wake-up option system wait mode
device overview s12xs family s12xs family reference manual, rev. 1.10 24 freescale semiconductor 1.1.3 block diagram figure 1-1 shows a block diagram of the s12xs family devices figure 1-1. s12xs family block diagram 4k ?12k bytes ram reset extal xtal 4k ?8k bytes data flash bkgd vddr periodic interrupt clock monitor single-wire background test voltage regulator debug module vdd atd multilevel interrupt module ptad sci0 ss sck ps3 ps0 ps1 ps2 mosi miso spi0 pts an[15:0] pad[15:0] vddpll 8/10/12-bit 16-channel analog-digital converter 16-bit 8 channel timer tim asynchronous serial if 8-bit 8 channel pulse width modulator pwm pit pb[7:0] ptb pa[7:0] pta pk[7,5:0] ptk xirq irq eclk pe4 pe3 pe2 pe1 pe0 pe7 pe6 pe5 pte vddf 64k ?256k bytes flash cpu12x amplitude controlled low power pierce or full drive pierce oscillator cop watchdog pll with frequency modulation option debug module 4 address breakpoints 2 data breakpoints 512 byte trace buffer reset generation and test entry rxd txd sci1 asynchronous serial if rxd txd ps7 ps4 ps5 ps6 ph3 ph0 ph1 ph2 pth (wake-up int) ph7 ph4 ph5 ph6 can0 pm3 pm0 pm1 pm2 ptm mscan 2.0b rxcan txcan pm7 pm4 pm5 pm6 synchronous serial if async. periodic int. 4ch 24-bit timer ptj (wake-up int) pj7 pj6 pt3 pt0 pt1 pt2 ptt pt7 pt4 pt5 pt6 pp3 pp0 pp1 pp2 ptp (wake-up int) pp7 pp4 pp5 pp6 pwm3 pwm0 pwm1 pwm2 pwm7 pwm4 pwm5 pwm6 ioc3 ioc0 ioc1 ioc2 ioc7 ioc4 ioc5 ioc6 vdda vssa vrh vrl pj1 pj0 xclks/eclkx2
device overview s12xs family s12xs family reference manual, rev. 1.10 freescale semiconductor 25 1.1.4 device memory map table 1-1 shows the device register memory map. table 1-1. device register memory map address module size (bytes) 0x0000?x0009 pim (port integration module ) 10 0x000a?x000b mmc (memory map control) 2 0x000c?x000d pim (port integration module) 2 0x000e?x000f reserved 2 0x0010?x0017 mmc (memory map control) 8 0x0018?x0019 reserved 2 0x001a?x001b device id register 2 0x001c?x001f pim (port integration module) 4 0x0020?x002f dbg (debug module) 16 0x0030?x0031 reserved 2 0x0032?x0033 pim (port integration module) 2 0x0034?x003f ecrg (clock and reset generator) 12 0x0040?x006f tim (timer module) 48 0x0070?x00c7 reserved 88 0x00c8?x00cf sci0 (serial communications interface) 8 0x00d0?x00d7 sci1 (serial communications interface) 8 0x00d8?x00df spi0 (serial peripheral interface) 8 0x00e0?x00ff reserved 32 0x0100?x0113 ftmr control registers 20 0x0114?x011f reserved 12 0x0120?x012f int (interrupt module) 16 0x0130?x013f reserved 16 0x0140?x017f can0 64 0x0180?x023f reserved 192 0x0240?x027f pim (port integration module) 64 0x0280?x02bf reserved 64 0x02c0?x02ef atd0 (analog-to-digital converter 12 bit 16-channel) 48 0x02f0?x02f7 voltage regulator 8 0x02f8?x02ff reserved 8 0x0300?x0327 pwm (pulse-width modulator 8 channels) 40 0x0328?x033f reserved 24 0x0340?x0367 pit (periodic interrupt timer) 40
device overview s12xs family s12xs family reference manual, rev. 1.10 26 freescale semiconductor note reserved register space shown in table 1-1 is not allocated to any module. this register space is reserved for future use. writing to these locations has no effect. read access to these locations returns zero. 1.1.5 address mapping figure 1-2 shows s12xs cpu and bdm local address translation to the global memory map. it indicates also the location of the internal resources in the memory map. 0x0368?x07ff reserved 1176 table 1-1. device register memory map (continued) address module size (bytes)
device overview s12xs family s12xs family reference manual, rev. 1.10 freescale semiconductor 27 figure 1-2. s12xs family global memory map 0x7f_ffff 0x00_0000 0x13_ffff 0x0f_ffff dflash ram 0x00_07ff rpage ppage 0x3f_ffff cpu and bdm local memory map global memory map flash flashsize unimplemented flash 0xffff vectors 0xc000 0x8000 unpaged 0x4000 0x1000 0x0000 16k flash window 0x2000 0x0800 8k ram 4k ram window 2k registers 16k flash unpaged 16k flash 2k registers unimplemented ram unimplemented space ram_low flash_low ramsize df_high dflash resources reserved epage 1k dflash window 0x0c00
device overview s12xs family s12xs family reference manual, rev. 1.10 28 freescale semiconductor accessing the reserved area in the range of 0x0c00 to 0x0fff will return unde?ed data values. a cpu access to any unimplemented space causes an illegal address reset. the range between 0x10_0000 and 0x13_ffff is mapped to dflash (data flash). the dflash block sizes are listed in table 1-2 . table 1-2. derivative dependent memory parameters of device internal resources 1.1.6 detailed register map the detailed register map is listed in the appendix of the reference manual. 1.1.7 part id assignments the part id is located in two 8-bit registers partidh and partidl (addresses 0x001a and 0x001b). the read-only value is a unique part id for each revision of the chip. table 1-3 shows the assigned part id number and mask set number. the version id is a word located in a ?sh information row at 0x40_00e8. the version id number indicates a speci? version of internal nvm variables used to patch nvm errata. the default is no patch (0xffff). device flash_low size/ ppage 1 1 number of 16k pages addressable via ppage register ram_low size/ rpage 2 2 number of 4k pages addressing the ram. df_high size/ epage 3 3 number of 1k pages addressing the dflash s12xs256 0x7c_0000 256k / 16 0x0f_d000 12k / 3 0x10_1fff 8k / 8 s12xs128 0x7e_0000 128k / 8 0x0f_e000 8k / 2 0x10_1fff 8k / 8 s12xs64 0x7f_0000 64k / 4 0x0f_f000 4k / 1 0x10_0fff 4k / 4 table 1-3. assigned part id numbers device mask set number part id 1 1 the coding is as follows: bit 15-12: major family identi?r bit 11-6: minor family identi?r bit 5-4: major mask set revision number including fab transfers bit 3-0: minor ?non full ?mask set revision version id mc9s12xs256 0m05m $c0c0 0xffff mc9s12xs128 0m04m $c1c0 0xffff 1m04m $c1c1 0xffff mc9s12xs64 0m04m $c1c0 0xffff 1m04m $c1c1 0xffff
device overview s12xs family s12xs family reference manual, rev. 1.10 freescale semiconductor 29 1.2 signal description this section describes signals that connect off-chip. it includes a pinout diagram, a table of signal properties, and detailed discussion of signals. it is built from the signal description sections of the individual ip blocks on the device. 1.2.1 device pinout the xs family of devices offers pin-compatible packaged devices to assist with system development and accommodate expansion of the application. the s12xs family devices are offered in the following package options: 112-pin lqfp 80-pin qfp 64-pin lqfp
device overview s12xs family s12xs family reference manual, rev. 1.10 30 freescale semiconductor figure 1-3. s12xs family pin assignments 112-pin lqfp package vrh vdda pad15/an15 pad07/an07 pad14/an14 pad06/an06 pad13/an13 pad05/an05 pad12/an12 pad04/an04 pad11/an11 pad03/an03 pad10/an10 pad02/an02 pad09/an09 pad01/an01 pad08/an08 pad00/an00 vss2 vdd pa7 pa6 pa5 pa4 pa3 pa2 pa1 pa0 pp4/kwp4/pwm4 pp5/kpw5/pwm5 pp6/kwp6/pwm6 pp7/kwp7/pwm7 pk7 vddx1 vssx1 pm0/rxcan0/rxd1 pm1/txcan0/txd1 pm2/miso0 pm3/ ss0 pm4/mosi0 pm5/sck0 pj6/kwj6 pj7/kwj7 test ps7/ ss0 ps6/sck0 ps5/mosi0 ps4/miso0 ps3/txd1 ps2/rxd1 ps1/txd0 ps0/rxd0 pm6 pm7 vssa vrl pwm3/kwp3/pp3 txd1/ioc2/pwm2/kwp2/pp2 ioc1/pwm1/kwp1/pp1 rxd1/ioc0/pwm0/kwp0/pp0 pk3 pk2 pk1 pk0 ioc0/pt0 ioc1/pt1 ioc2/pt2 ioc3/pt3 vddf vss1 pwm4/ioc4/pt4 vreg_api/pwm5/ioc5/pt5 pwm6/ioc6/pt6 pwm7/ioc7/pt7 pk5 pk4 kwj1/pj1 kwj0/pj0 modc/bkgd pb0 pb1 pb2 pb3 pb4 pb5 pb6 pb7 kwh7/ph7 kwh6/ph6 kwh5/ph5 kwh4/ph4 xclks/eclkx2/pe7 pe6 pe5 eclk/pe4 vssx2 vddx2 reset vddr vss3 vsspll extal xtal vddpll kwh3/ph3 kwh2/ph2 kwh1/ph1 kwh0/ph0 pe3 pe2 irq/pe1 xirq/pe0 pins shown in bold are not available on the 80 qfp package s12xs family 112lqfp 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57
device overview s12xs family s12xs family reference manual, rev. 1.10 freescale semiconductor 31 figure 1-4. s12xs family pin assignments 80-pin qfp package 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 vrh vdda pad07/an07 pad06/an06 pad05/an05 pad04/an04 pad03/an03 pad02/an02 pad01/an01 pad00/an00 vss2 vdd pa7 pa6 pa5 pa4 pa 3 pa 2 pa 1 pa 0 pb5 pb6 pb7 xclks/eclkx2/pe7 pe6 pe5 eclk/pe5 vssx2 vddx2 reset vddr vss3 vsspll extal xtal vddpll pe3 pe2 irq/pe1 xirq/pe0 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 s12xs family 80qfp pwm3/kwp3/pp3 txd1/ioc2/pwm2/kwp2/pp2 ioc1/pwm1/kwp1/pp1 rxd1/ioc0/pwm0/kwp0/pp0 ioc0/pt0 ioc1/pt1 ioc2/pt2 ioc3/pt3 vddf vss1 pwm4/ioc4/pt4 vreg_api/pwm5/ioc5/pt5 pwm6/ioc6/pt6 pwm7/ioc7/pt7 modc/bkgd pb0 pb1 pb2 pb3 pb4 pp4/kwp4/pwm4 pp5/kpw5/pwm5 pp7/kpw7/pwm7 vddx1 vssx1 pm0/rxcan0/rxd1 pm1/txcan0/txd1 pm2/miso0 pm3/ ss0 pm4/mosi0 pm5/sck0 pj6/kwj6 pj7/kwj7 test ps3/txd1 ps2/rxd1 ps1/txd0 ps0/rxd0 vssa vrl pins shown in bold are not available on the 64 qfp package
device overview s12xs family s12xs family reference manual, rev. 1.10 32 freescale semiconductor figure 1-5. s12xs family pin assignments 64-pin lqfp package 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 s12xs family 64lqfp vrh vdda pad07/an07 pad06/an06 pad05/an05 pad04/an04 pad03/an03 pad02/an02 pad01/an01 pad00/an00 vss2 vdd pa 3 pa 2 pa 1 pa 0 pb5 pb6 pb7 xclks/eclkx2/pe7 eclk/pe4 vssx2 vddx2 reset vddr vss3 vsspll extal xtal vddpll irq/pe1 xirq/pe0 pwm3/kwp3/pp3 txd1/ioc2/pwm2/kwp2/pp2 ioc1/pwm1/kwp1/pp1 rxd1/ioc0/pwm0/kwp0/pp0 ioc0/pt0 ioc1/pt1 ioc2/pt2 ioc3/pt3 vddf vss1 pwm4/ioc4/pt4 vreg_api/pwm5/ioc5/pt5 pwm6/ioc6/pt6 pwm7/ioc7/pt7 modc/bkgd pb0 pp5/kpw5/pwm5 pp7/kwp7/pwm7 vddx1 vssx1 pm0/rxcan0/rxd1 pm1/txcan0/txd1 pm2/miso0 pm3/ ss0 pm4/mosi0 pm5/sck0 test ps3/txd1 ps2/rxd1 ps1/txd0 ps0/rxd0 vssa/vrl
device overview s12xs family s12xs family reference manual, rev. 1.10 freescale semiconductor 33 1.2.2 pin assignment overview table 1-4 provides a summary of which ports are available for each package option. routing of pin functions is summarized in table 1-5 . table 1-4. port availability by package option port 112 lqfp 80 qfp 64 lqfp port ad/adc channels 16/16 8/8 8/8 port a pins 8 8 4 port b pins 8 8 4 port e pins inc. irq/xirq input only 8 8 4 port h 800 port j 420 port k 700 port m 866 port p 876 port s 844 port t 888 sum of ports 91 59 44 i/o power pairs vddx/vssx 2/2 2/2 2/2 table 1-5. peripheral - port routing options 1 1 ? denotes reset condition, ? denotes a possible rerouting under software control sci1 spi0 pwm tim pm[1:0] o pm[5:2] o pp[2,0] o pp[2:0] o pp[7:4] x ps[3:2] x ps[7:4] x pt[2:0] x pt[7:4] o
s12xs family reference manual, rev. 1.10 34 freescale semiconductor device overview s12xs family table 1-6 provides a pin out summary listing the availability and functionality of individual pins for each package option. table 1-6. pin-out summary 1 package terminal function power supply internal pull resistor description lqfp 112 qfp 80 lqfp 64 pin 2nd func. 3rd func. 4th func. 5th func. ctrl reset state 1 1 1 pp3 kwp3 pwm3 v ddx perp/ppsp disabled port p i/o, interrupt, pwm channel 2 2 2 pp2 kwp2 pwm2 ioc2 txd1 v ddx perp/ppsp disabled port p i/o, interrupt, pwm/tim channel, txd of sci1 3 3 3 pp1 kwp1 pwm1 ioc1 v ddx perp/ppsp disabled port p i/o, interrupt, pwm/tim channel 4 4 4 pp0 kwp0 pwm0 ioc0 rxd1 v ddx perp/ppsp disabled port p i/o, interrupt, pwm/tim channel, rxd of sci1 5 - - pk3 v ddx pucr up port k i/o 6 - - pk2 v ddx pucr up port k i/o 7 - - pk1 v ddx pucr up port k i/o 8 - - pk0 v ddx pucr up port k i/o 9 5 5 pt0 ioc0 v ddx pert/ppst disabled port t i/o, tim channel 10 6 6 pt1 ioc1 v ddx pert/ppst disabled port t i/o, tim channel 11 7 7 pt2 ioc2 v ddx pert/ppst disabled port t i/o, tim channel 12 8 8 pt3 ioc3 v ddx pert/ppst disabled port t i/o, tim channel 13 9 9 vddf 14 10 10 vss1 15 11 11 pt4 ioc4 pwm4 v ddx pert/ppst disabled port t i/o, pwm/tim channel
device overview s12xs family s12xs family reference manual, rev. 1.10 freescale semiconductor 35 16 12 12 pt5 ioc5 pwm5 vreg_ api ? ddx pert/ppst disabled port t i/o, pwm/tim channel, api output 17 13 13 pt6 ioc6 pwm6 v ddx pert/ppst disabled port t i/o, channel of pwm/tim 18 14 14 pt7 ioc7 pwm7 v ddx pert/ppst disabled port t i/o, channel of pwm/tim 19 - - pk5 v ddx pucr up port k i/o 20 - - pk4 v ddx pucr up port k i/o 21 - - pj1 kwj1 v ddx perj/ppsj up port j i/o, interrupt 22 - - pj0 kwj0 v ddx perj/ppsj up port j i/o, interrupt 23 15 15 bkgd modc v ddx always on up background debug 24 16 16 pb0 v ddx pucr disabled port b i/o 25 17 - pb1 v ddx pucr disabled port b i/o 26 18 - pb2 v ddx pucr disabled port b i/o 27 19 - pb3 v ddx pucr disabled port b i/o 28 20 - pb4 v ddx pucr disabled port b i/o 29 21 17 pb5 v ddx pucr disabled port b i/o 30 22 18 pb6 v ddx pucr disabled port b i/o 31 23 19 pb7 v ddx pucr disabled port b i/o 32 - - ph7 kwh7 v ddx perh/ppsh disabled port h i/o, interrupt 33 - - ph6 kwh6 v ddx perh/ppsh disabled port h i/o, interrupt 34 - - ph5 kwh5 v ddx perh/ppsh disabled port h i/o, interrupt 35 - - ph4 kwh4 v ddx perh/ppsh disabled port h i/o, interrupt table 1-6. pin-out summary 1 (continued) package terminal function power supply internal pull resistor description lqfp 112 qfp 80 lqfp 64 pin 2nd func. 3rd func. 4th func. 5th func. ctrl reset state
s12xs family reference manual, rev. 1.10 36 freescale semiconductor device overview s12xs family 36 24 20 pe7 xclks eclkx2 v ddx pucr up port e i/o, system clock output, clock select input 37 25 - pe6 v ddx while reset pin is low: down 2 port e i/o 38 26 - pe5 v ddx while reset pin is low: down 2 port e i/o 39 27 21 pe4 eclk v ddx pucr up port e i/o, bus clock output 40 28 22 vssx2 41 29 23 vddx2 42 30 24 reset v ddx pullup external reset 43 31 25 vddr 44 32 26 vss3 45 33 27 vsspll 46 34 28 extal v ddpll na na oscillator pin 47 35 29 xtal v ddpll na na oscillator pin 48 36 30 vddpll 49 - - ph3 kwh3 v ddx perh/ppsh disabled port h i/o, interrupt 50 - - ph2 kwh2 v ddx perh/ppsh disabled port h i/o, interrupt 51 - - ph1 kwh1 v ddx perh/ppsh disabled port h i/o, interrupt 52 - - ph0 kwh0 v ddx perh/ppsh disabled port h i/o, interrupt 53 37 - pe3 v ddx pucr up port e i/o 54 38 - pe2 v ddx pucr up port e i/o table 1-6. pin-out summary 1 (continued) package terminal function power supply internal pull resistor description lqfp 112 qfp 80 lqfp 64 pin 2nd func. 3rd func. 4th func. 5th func. ctrl reset state
device overview s12xs family s12xs family reference manual, rev. 1.10 freescale semiconductor 37 55 39 31 pe1 irq v ddx pucr up port e input, maskable interrupt 56 40 32 pe0 xirq v ddx pucr up port e input, non- maskable interrupt 57 41 33 pa0 v ddx pucr disabled port a i/o 58 42 34 pa1 v ddx pucr disabled port a i/o 59 43 35 pa2 v ddx pucr disabled port a i/o 60 44 36 pa3 v ddx pucr disabled port a i/o 61 45 - pa4 v ddx pucr disabled port a i/o 62 46 - pa5 v ddx pucr disabled port a i/o 63 47 - pa6 v ddx pucr disabled port a i/o 64 48 - pa7 v ddx pucr disabled port a i/o 65 49 37 vdd 66 50 38 vss2 67 51 39 pad00 an00 v dda per1ad disabled port ad i/o, analog input of atd 68 - - pad08 an08 v dda per0ad disabled port ad i/o, analog input of atd 69 52 40 pad01 an01 v dda per1ad disabled port ad i/o, analog input of atd 70 - - pad09 an09 v dda per0ad disabled port ad i/o, analog input of atd 71 53 41 pad02 an02 v dda per1ad disabled port ad i/o, analog input of atd table 1-6. pin-out summary 1 (continued) package terminal function power supply internal pull resistor description lqfp 112 qfp 80 lqfp 64 pin 2nd func. 3rd func. 4th func. 5th func. ctrl reset state
s12xs family reference manual, rev. 1.10 38 freescale semiconductor device overview s12xs family 72 - - pad10 an10 v dda per0ad disabled port ad i/o, analog input of atd 73 54 42 pad03 an03 v dda per1ad disabled port ad i/o, analog input of atd 74 - - pad11 an11 v dda per0ad disabled port ad i/o, analog input of atd 75 55 43 pad04 an04 v dda per1ad disabled port ad i/o, analog input of atd 76 - - pad12 an12 v dda per0ad disabled port ad i/o, analog input of atd 77 56 44 pad05 an05 v dda per1ad disabled port ad i/o, analog input of atd 78 - - pad13 an13 v dda per0ad disabled port ad i/o, analog input of atd 79 57 45 pad06 an06 v dda per1ad disabled port ad i/o, analog input of atd 80 - - pad14 an14 v dda per0ad disabled port ad i/o, analog input of atd 81 58 46 pad07 an07 v dda per1ad disabled port ad i/o, analog input of atd 82 - - pad15 an15 v dda per0ad disabled port ad i/o, analog input of atd 83 59 47 vdda 84 60 48 vrh 85 61 49 vrl 3 86 62 49 vssa table 1-6. pin-out summary 1 (continued) package terminal function power supply internal pull resistor description lqfp 112 qfp 80 lqfp 64 pin 2nd func. 3rd func. 4th func. 5th func. ctrl reset state
device overview s12xs family s12xs family reference manual, rev. 1.10 freescale semiconductor 39 87 - - pm7 v ddx perm/ppsm disabled port m i/o 88 - - pm6 v ddx perm/ppsm disabled port m i/o 89 63 50 ps0 rxd0 v ddx pers/ppss up port s i/o, rxd of sci0 90 64 51 ps1 txd0 v ddx pers/ppss up port s i/o, txd of sci0 91 65 52 ps2 rxd1 v ddx pers/ppss up port s i/o, rxd of sci1 92 66 53 ps3 txd1 v ddx pers/ppss up port s i/o, txd of sci1 93 - - ps4 miso0 v ddx pers/ppss up port s i/o, miso of spi0 94 - - ps5 mosi0 v ddx pers/ppss up port s i/o, mosi of spi0 95 - - ps6 sck0 v ddx pers/ppss up port s i/o, sck of spi0 96 - - ps7 ss0 v ddx pers/ppss up port s i/o, ss of spi0 97 67 54 test n.a. reset pin down test input 98 68 - pj7 kwj7 v ddx perj/ppsj up port j i/o, interrupt 99 69 - pj6 kwj6 v ddx perj/ppsj up port j i/o, interrupt 100 70 55 pm5 sck0 v ddx perm/ppsm disabled port m i/o, sck of spi0 101 71 56 pm4 mosi0 v ddx perm/ppsm disabled port m i/o, mosi of spi0 102 72 57 pm3 ss0 v ddx perm/ppsm disabled port m i/o, ss of spi0 103 73 58 pm2 miso0 v ddx perm/ppsm disabled port m i/o, miso of spi0 104 74 59 pm1 txcan0 txd1 v ddx perm/ppsm disabled port m i/o, tx of can0, txd of sci1 105 75 60 pm0 rxcan0 rxd1 v ddx perm/ppsm disabled port m i/o, rx of can0, rxd of sci1 table 1-6. pin-out summary 1 (continued) package terminal function power supply internal pull resistor description lqfp 112 qfp 80 lqfp 64 pin 2nd func. 3rd func. 4th func. 5th func. ctrl reset state
s12xs family reference manual, rev. 1.10 40 freescale semiconductor device overview s12xs family 106 76 61 vssx1 107 77 62 vddx1 108 - - pk7 v ddx pucr up port k i/o 109 78 63 pp7 kwp7 pwm7 v ddx perp/ppsp disabled port p i/o, interrupt, pwm channel 110 - - pp6 kwp6 pwm6 v ddx perp/ppsp disabled port p i/o, interrupt, pwm channel 111 79 64 pp5 kwp5 pwm5 v ddx perp/ppsp disabled port p i/o, interrupt, pwm channel 112 80 - pp4 kwp4 pwm4 v ddx perp/ppsp disabled port p i/o, interrupt, pwm channel 1 table shows a superset of pin functions. not all functions are available on all derivatives 2 for compatibility to xe family 3 vrl and vssa share single pin on 64 package option table 1-6. pin-out summary 1 (continued) package terminal function power supply internal pull resistor description lqfp 112 qfp 80 lqfp 64 pin 2nd func. 3rd func. 4th func. 5th func. ctrl reset state
device overview s12xs family s12xs family reference manual, rev. 1.10 freescale semiconductor 41 1.2.3 detailed signal descriptions note the pin list of the largest package version of each s12xs family derivative gives the complete of interface signals that also exist on smaller package options, although some of them are not bonded out. for devices assembled in smaller packages all non-bonded out pins should be con?ured as outputs after reset in order to avoid current drawn from ?ating inputs. refer to table 1-6 for affected pins. 1.2.3.1 extal, xtal ?oscillator pins extal and xtal are the crystal driver and external clock pins. on reset all the device clocks are derived from the extal input frequency. xtal is the oscillator output. 1.2.3.2 reset ?external reset pin the reset pin is an active low bidirectional control signal. it acts as an input to initialize the mcu to a known start-up state. as an output it is driven low to indicate when any internal mcu reset source triggers. the reset pin has an internal pull-up device. 1.2.3.3 test ?test pin this input only pin is reserved for factory test. this pin has a pull-down device. note the test pin must be tied to v ss in all applications. 1.2.3.4 bkgd / modc ?background debug and mode pin the bkgd/modc pin is used as a pseudo-open-drain pin for the background debug communication. it is used as a mcu operating mode select pin during reset. the state of this pin is latched to the modc bit at the rising edge of reset. the bkgd pin has an internal pull-up device. 1.2.3.5 pad[15:0] / an[15:0] ?port ad input pins of atd0 pad[15:0] are general-purpose input or output pins and analog inputs an[15:0] of the analog-to-digital converter atd0. 1.2.3.6 pa[7:0] ?port a i/o pins pa[7:0] are general-purpose input or output pins. 1.2.3.7 pb[7:0] ?port b i/o pins pb[7:0] are general-purpose input or output pins.
device overview s12xs family s12xs family reference manual, rev. 1.10 42 freescale semiconductor 1.2.3.8 pe7 / eclkx2 / xclks ?port e i/o pin 7 pe7 is a general-purpose input or output pin. eclkx2 is a clock output of twice the internal bus frequency. the xclks is an input signal which controls whether a crystal in combination with the internal loop controlled pierce oscillator is used or whether full swing pierce oscillator/external clock circuitry is used (refer to section 1.10 oscillator con?uration ). an internal pull-up is enabled during reset. 1.2.3.9 pe[6:5] ?port e i/o pin 6-5 pe[6:5] are a general-purpose input or output pins. 1.2.3.10 pe4 / eclk ?port e i/o pin 4 pe4 is a general-purpose input or output pin. it can be con?ured to output the internal bus clock eclk. eclk can be used as a timing reference. the eclk output has a programmable prescaler. 1.2.3.11 pe[3:2] ?port e i/o pin 3 pe[3:2] are a general-purpose input or output pins. 1.2.3.12 pe1 / irq ?port e input pin 1 pe1 is a general-purpose input pin and the maskable interrupt request input that provides a means of applying asynchronous interrupt requests. this will wake up the mcu from stop or wait mode. 1.2.3.13 pe0 / xirq ?port e input pin 0 pe0 is a general-purpose input pin and the non-maskable interrupt request input that provides a means of applying asynchronous interrupt requests. this will wake up the mcu from stop or wait mode. the xirq interrupt is level sensitive and active low. as xirq is level sensitive, while this pin is low the mcu will not enter stop mode. 1.2.3.14 ph[7:0] / kwh[7:0] ?port h i/o pins ph[7:0] are a general-purpose input or output pins. they can be con?ured as keypad wakeup inputs. 1.2.3.15 pj[7:6] / kwj[7:6] ?port j i/o pins 7-6 pj[7:6] are a general-purpose input or output pins. they can be con?ured as keypad wakeup inputs. 1.2.3.16 pj[1:0] / kwj[1:0] ?port j i/o pins 1-0 pj[1:0] are a general-purpose input or output pins. they can be con?ured as keypad wakeup inputs. 1.2.3.17 pk[7,5:0] ?port k i/o pins 7 and 5-0 pk[7,5:0] are a general-purpose input or output pins.
device overview s12xs family s12xs family reference manual, rev. 1.10 freescale semiconductor 43 1.2.3.18 pm[7:6] ?port m i/o pins 7-6 pm[7:6] are a general-purpose input or output pins. 1.2.3.19 pm5 / sck0 ?port m i/o pin 5 pm5 is a general-purpose input or output pin. it can be con?ured as the serial clock pin sck of the serial peripheral interface 0 (spi0). 1.2.3.20 pm4 / mosi0 ?port m i/o pin 4 pm4 is a general-purpose input or output pin. it can be con?ured as the master output (during master mode) or slave input pin (during slave mode) mosi for the serial peripheral interface 0 (spi0). 1.2.3.21 pm3 / ss0 ?port m i/o pin 3 pm3 is a general-purpose input or output pin. it can be con?ured as the slave select pin ss of the serial peripheral interface 0 (spi0). 1.2.3.22 pm2 / miso0 ?port m i/o pin 2 pm2 is a general-purpose input or output pin. it can be con?ured as the master input (during master mode) or slave output pin (during slave mode) miso for the serial peripheral interface 0 (spi0). 1.2.3.23 pm1 / txcan0 / txd1 ?port m i/o pin 1 pm1 is a general-purpose input or output pin. it can be con?ured as the transmit pin txcan of the scalable controller area network controller 0 (can0). it can be con?ured as the transmit pin txd of serial communication interface 1 (sci1). 1.2.3.24 pm0 / rxcan0 / rxd1 ?port m i/o pin 0 pm0 is a general-purpose input or output pin. it can be con?ured as the receive pin rxcan of the scalable controller area network controller 0 (can0). it can be con?ured as the receive pin rxd of serial communication interface 1 (sci1). 1.2.3.25 pp7 / kwp7 / pwm7 ?port p i/o pin 7 pp7 is a general-purpose input or output pin. it can be con?ured as keypad wakeup input. it can be con?ured as pulse width modulator (pwm) channel 7 output or emergency shutdown input. 1.2.3.26 pp[6:3] / kwp[6:3] / pwm[6:3] ?port p i/o pins 6-3 pp[6:3] are a general-purpose input or output pins. they can be con?ured as keypad wakeup inputs. they can be con?ured as pulse width modulator (pwm) channel 6-3 output.
device overview s12xs family s12xs family reference manual, rev. 1.10 44 freescale semiconductor 1.2.3.27 pp2 / kwp2 / pwm2 / txd1 / ioc2 ?port p i/o pin 2 pp2 is a general-purpose input or output pin. it can be con?ured as a keypad wakeup input. it can be con?ured as pulse width modulator (pwm) channel 2 output, tim channel 2 or as the transmit pin txd of serial communication interface 1 (sci1). 1.2.3.28 pp1 / kwp1 / pwm1 / ioc1 ?port p i/o pin 1 pp1 is a general-purpose input or output pin. it can be con?ured as a keypad wakeup input. it can be con?ured as pulse width modulator (pwm) channel 1 output, tim channel 1. 1.2.3.29 pp0 / kwp0 / pwm0 / rxd1 / ioc0 ?port p i/o pin 0 pp0 is a general-purpose input or output pin. it can be con?ured as a keypad wakeup input. it can be con?ured as pulse width modulator (pwm) channel 0 output, tim channel 0 or as the receive pin rxd of serial communication interface 1 (sci1). 1.2.3.30 ps7 / ss0 ?port s i/o pin 7 ps7 is a general-purpose input or output pin. it can be con?ured as the slave select pin ss of the serial peripheral interface 0 (spi0). 1.2.3.31 ps6 / sck0 ?port s i/o pin 6 ps6 is a general-purpose input or output pin. it can be con?ured as the serial clock pin sck of the serial peripheral interface 0 (spi0). 1.2.3.32 ps5 / mosi0 ?port s i/o pin 5 ps5 is a general-purpose input or output pin. it can be con?ured as master output (during master mode) or slave input pin (during slave mode) mosi of the serial peripheral interface 0 (spi0). 1.2.3.33 ps4 / miso0 ?port s i/o pin 4 ps4 is a general-purpose input or output pin. it can be con?ured as master input (during master mode) or slave output pin (during slave mode) mosi of the serial peripheral interface 0 (spi0). 1.2.3.34 ps3 / txd1 ?port s i/o pin 3 ps3 is a general-purpose input or output pin. it can be con?ured as the transmit pin txd of serial communication interface 1 (sci1). 1.2.3.35 ps2 / rxd1 ?port s i/o pin 2 ps2 is a general-purpose input or output pin. it can be con?ured as the receive pin rxd of serial communication interface 1 (sci1).
device overview s12xs family s12xs family reference manual, rev. 1.10 freescale semiconductor 45 1.2.3.36 ps1 / txd0 ?port s i/o pin 1 ps1 is a general-purpose input or output pin. it can be con?ured as the transmit pin txd of serial communication interface 0 (sci0). 1.2.3.37 ps0 / rxd0 ?port s i/o pin 0 ps0 is a general-purpose input or output pin. it can be con?ured as the receive pin rxd of serial communication interface 0 (sci0). 1.2.3.38 pt[7:6] / ioc[7:6] / pwm[7:6] ?port t i/o pins 7-6 pt[7:6] are general-purpose input or output pins. they can be con?ured as timer (tim) channel 7-6 or pulse width modulator (pwm) outputs 7-6 1.2.3.39 pt5 / ioc5 / vreg_api ?port t i/o pin 5 pt[5] is a general-purpose input or output pin. it can be con?ured as timer (tim) channel 5, pulse width modulator (pwm) output 5 or as the vreg_api signal output. 1.2.3.40 pt4 / ioc4 / pwm4 ?port t i/o pin 4 pt4 is a general-purpose input or output pin. it can be con?ured as timer (tim) channel 4 or pulse width modulator (pwm) output 4. 1.2.3.41 pt[3:0] / ioc[3:0] ?port t i/o pin [3:0] pt[3:0] are a general-purpose input or output pins. they can be con?ured as timer (tim) channels 3-0. 1.2.4 power supply pins s12xs family power and ground pins are described below. because fast signal transitions place high, short-duration current demands on the power supply, use bypass capacitors with high-frequency characteristics and place them as close to the mcu as possible. note all v ss pins must be connected together in the application. 1.2.4.1 vddx[2:1], vssx[2:1] ?power and ground pins for i/o drivers external power and ground for i/o drivers. bypass requirements depend on how heavily the mcu pins are loaded. all v ddx pins are connected together internally. all v ssx pins are connected together internally. 1.2.4.2 vddr ?power pin for internal voltage regulator power supply input to the internal voltage regulator.
device overview s12xs family s12xs family reference manual, rev. 1.10 46 freescale semiconductor 1.2.4.3 vdd, vss2, vss3 ?core power pins the voltage supply of nominally 1.8 v is derived from the internal voltage regulator. the return current path is through the vss2 and vss3 pins. no static external loading of these pins is permitted. 1.2.4.4 vddf, vss1 ?nvm power pins the voltage supply of nominally 2.8 v is derived from the internal voltage regulator. the return current path is through the vss1 pin. no static external loading of these pins is permitted. 1.2.4.5 vdda, vssa ?power supply pins for atd and voltage regulator these are the power supply and ground input pins for the analog-to-digital converters and the voltage regulator. 1.2.4.6 vrh, vrl ?atd reference voltage input pins v rh and v rl are the reference voltage input pins for the analog-to-digital converter. 1.2.4.7 vddpll, vsspll ?power supply pins for pll these pins provide operating voltage and ground for the oscillator and the phased-locked loop. the voltage supply of nominally 1.8 v is derived from the internal voltage regulator. this allows the supply voltage to the oscillator and pll to be bypassed independently. this voltage is generated by the internal voltage regulator. no static external loading of these pins is permitted. table 1-7. power and ground connection summary mnemonic nominal voltage description vddr 5.0 v external power supply to internal voltage regulator vddx[2:1] 5.0 v external power and ground, supply to pin drivers vssx[2:1] 0 v vdda 5.0 v operating voltage and ground for the analog-to-digital converters and the reference for the internal voltage regulator, allows the supply voltage to the a/d to be bypassed independently. vssa 0 v vrl 0 v reference voltages for the analog-to-digital converter. vrh 5.0 v vdd 1.8 v internal power and ground generated by internal regulator for the internal core. vss1, vss2, vss3 0 v vddf 2.8 v internal power and ground generated by internal regulator for the internal nvm.
device overview s12xs family s12xs family reference manual, rev. 1.10 47 freescale semiconductor vddpll 1.8 v provides operating voltage and ground for the phased-locked loop. this allows the supply voltage to the pll to be bypassed independently. internal power and ground generated by internal regulator. vsspll 0 v table 1-7. power and ground connection summary mnemonic nominal voltage description
device overview s12xs family s12xs family reference manual, rev. 1.10 48 freescale semiconductor 1.3 system clock description the clock and reset generator module (crg) provides the internal clock signals for the core and all peripheral modules. figure 1-6 shows the clock connections from the crg to all modules. consult the s12xecrg section for details on clock generation. note the xs family uses the xe family clock and reset generator module. therefore all crg references are related to s12xecrg. figure 1-6. clock connections the system clock can be supplied in several ways enabling a range of system operating frequencies to be supported: the on-chip phase locked loop (pll) the pll self clocking the oscillator sci0 . . sci 1 spi0 atd0 can0 crg bus clock extal xtal core clock oscillator clock ram s12x flash pit tim pim pwm
device overview s12xs family s12xs family reference manual, rev. 1.10 freescale semiconductor 49 the clock generated by the pll or oscillator provides the main system clock frequencies core clock and bus clock. as shown in figure 1-6 , these system clocks are used throughout the mcu to drive the core, the memories, and the peripherals. the program flash memory is supplied by the bus clock and the oscillator clock. the oscillator clock is used as a time base to derive the program and erase times for the nvms. the can modules may be con?ured to have their clock sources derived either from the bus clock or directly from the oscillator clock. this allows the user to select its clock based on the required jitter performance. in order to ensure the presence of the clock the mcu includes an on-chip clock monitor connected to the output of the oscillator. the clock monitor can be con?ured to invoke the pll self-clocking mode or to generate a system reset if it is allowed to time out as a result of no oscillator clock being present. in addition to the clock monitor, the mcu also provides a clock quality checker which performs a more accurate check of the clock. the clock quality checker counts a predetermined number of clock edges within a de?ed time window to insure that the clock is running. the checker can be invoked following speci? events such as on wake-up or clock monitor failure. 1.4 modes of operation the mcu can operate in different modes. these are described in 1.4.1 chip con?uration summary . the mcu can operate in different power modes to facilitate power saving when full system performance is not required. these are described in 1.4.2 power modes . some modules feature a software programmable option to freeze the module status whilst the background debug module is active to facilitate debugging. this is described in 1.4.3 freeze mode . 1.4.1 chip con?uration summary the different modes and the security state of the mcu affect the debug features (enabled or disabled). the operating mode out of reset is determined by the state of the modc signal during reset (see table 1- 8 ). the modc bit in the mode register shows the current operating mode and provides limited mode switching during operation. the state of the modc signal is latched into this bit on the rising edge of reset. 1.4.1.1 normal single-chip mode this mode is intended for normal device operation. the opcode from the on-chip memory is being executed after reset (requires the reset vector to be programmed correctly). the processor program is executed from internal memory. table 1-8. chip modes chip modes modc normal single chip 1 special single chip 0
device overview s12xs family s12xs family reference manual, rev. 1.10 50 freescale semiconductor 1.4.1.2 special single-chip mode this mode is used for debugging single-chip operation, boot-strapping, or security related operations. the background debug module bdm is active in this mode. the cpu executes a monitor program located in an on-chip rom. bdm ?mware waits for additional serial commands through the bkgd pin. 1.4.2 power modes the mcu features two main low-power modes. consult the respective section for module speci? behavior in system stop, system pseudo stop, and system wait mode. an important source of information about the clock system is the clock and reset generator section (crg). 1.4.2.1 system stop modes the system stop modes are entered if the cpu executes the stop instruction unless an nvm command is active. depending on the state of the pstp bit in the clksel register the mcu goes into pseudo stop mode or full stop mode. please refer to crg section. asserting reset, xirq, irq or any other interrupt that is not masked exits system stop modes. system stop modes can be exited by cpu activity, depending on the con?uration of the interrupt request. if the cpu executes the stop instruction whilst an nvm command is being processed, then the system clocks continue running until nvm activity is completed. if a non-masked interrupt occurs within this time then the system does not effectively enter stop mode although the stop instruction has been executed. 1.4.2.2 full stop mode the oscillator is stopped in this mode. by default all clocks are switched off and all counters and dividers remain frozen. the autonomous periodic interrupt (api) and atd module may be enabled to self wake the device. a fast wake up mode is available to allow the device to wake from full stop mode immediately on the pll internal clock without starting the oscillator clock. 1.4.2.3 pseudo stop mode in this mode the system clocks are stopped but the oscillator is still running and the real time interrupt (rti) and watchdog (cop), api and atd modules may be enabled. other peripherals are turned off. this mode consumes more current than system stop mode but, as the oscillator continues to run, the full speed wake up time from this mode is signi?antly shorter. 1.4.2.4 wait mode this mode is entered when the cpu executes the wai instruction. in this mode the cpu will not execute instructions. the internal cpu clock is switched off. all peripherals can be active in system wait mode. for further power consumption the peripherals can individually turn off their local clocks. asserting reset, xirq, irq or any other interrupt that is not masked ends system wait mode.
device overview s12xs family s12xs family reference manual, rev. 1.10 freescale semiconductor 51 1.4.2.5 run mode although this is not a low-power mode, unused peripheral modules should not be enabled in order to save power. 1.4.3 freeze mode the timer module, pulse width modulator, analog-to-digital converters, and the periodic interrupt timer provide a software programmable option to freeze the module status when the background debug module is active. this is useful when debugging application software. for detailed description of the behavior of the atd, tim, pwm, and pit when the background debug module is active consult the corresponding section. 1.5 security the mcu security mechanism prevents unauthorized access to the flash memory. for a detailed description of the security features refer to the s12xs9sec section. 1.6 resets and interrupts consult the cpu12/cpu12x reference manual and the s12xint section for information on exception processing. note when referring to the s12xint section please be aware that the xs family neither features an xgate nor an mpu module. 1.6.1 resets resets are explained in detail in the clock reset generator (s12xecrg) section. table 1-9. reset sources and vector locations 1.6.2 vectors table 1-10 lists all interrupt sources and vectors in the default order of priority. the interrupt module (s12xint) provides an interrupt vector base register (ivbr) to relocate the vectors. associated with each vector address reset source ccr mask local enable $fffe power-on reset (por) none none $fffe low voltage reset (lvr) none none $fffe external pin reset none none $fffe illegal address reset none none $fffc clock monitor reset none pllctl (cme, scme) $fffa cop watchdog reset none cop rate select
device overview s12xs family s12xs family reference manual, rev. 1.10 52 freescale semiconductor i-bit maskable service request is a con?uration register. it selects if the service request is enabled and the service request priority level. table 1-10. interrupt vector locations (sheet 1 of 2) vector address 1 interrupt source ccr mask local enable stop wake up wait wake up vector base + $f8 unimplemented instruction trap none none vector base+ $f6 swi none none vector base+ $f4 xirq x bit none yes yes vector base+ $f2 irq i bit irqcr (irqen) yes yes vector base+ $f0 real time interrupt i bit crgint (rtie) refer to crg interrupt section vector base+ $ee tim timer channel 0 i bit tie (c0i) no yes vector base + $ec tim timer channel 1 i bit tie (c1i) no yes vector base+ $ea tim timer channel 2 i bit tie (c2i) no yes vector base+ $e8 tim timer channel 3 i bit tie (c3i) no yes vector base+ $e6 tim timer channel 4 i bit tie (c4i) no yes vector base+ $e4 tim timer channel 5 i bit tie (c5i) no yes vector base + $e2 tim timer channel 6 i bit tie (c6i) no yes vector base+ $e0 tim timer channel 7 i bit tie (c7i) no yes vector base+ $de tim timer over?w i bit tsrc2 (tof) no yes vector base+ $dc tim pulse accumulator a over?w i bit pactl (paovi) no yes vector base + $da tim pulse accumulator input edge i bit pactl (pai) no yes vector base + $d8 spi0 i bit spi0cr1 (spie, sptie) no yes vector base+ $d6 sci0 i bit sci0cr2 (tie, tcie, rie, ilie) ye s ye s vector base + $d4 sci1 i bit sci1cr2 (tie, tcie, rie, ilie) ye s ye s vector base + $d2 atd0 i bit atd0ctl2 (ascie) yes yes vector base + $d0 reserved vector base + $ce port j i bit piej (piej7-piej0) yes yes vector base + $cc port h i bit pieh (pieh7-pieh0) yes yes vector base + $ca reserved vector base + $c8 reserved vector base + $c6 crg pll lock i bit crgint(lockie) refer to crg interrupt section vector base + $c4 crg self-clock mode i bit crgint (scmie) refer to crg interrupt section vector base + $c2 to vector base + $bc reserved
device overview s12xs family s12xs family reference manual, rev. 1.10 freescale semiconductor 53 1.6.3 effects of reset when a reset occurs, mcu registers and control bits are initialized. refer to the respective block sections for register reset states. on each reset, the flash module executes a reset sequence to load flash configuration registers. vector base + $ba flash fault detect i bit fcnfg2 (sfdie, dfdie) no no vector base + $b8 flash i bit fcnfg (ccie) no yes vector base + $b6 can0 wake-up i bit can0rier (wupie) yes yes vector base + $b4 can0 errors i bit can0rier (cscie, ovrie) no yes vector base + $b2 can0 receive i bit can0rier (rxfie) no yes vector base + $b0 can0 transmit i bit can0tier (txeie[2:0]) no yes vector base + $ae to vector base + $90 reserved vector base + $8e port p interrupt i bit piep (piep7-piep0) yes yes vector base+ $8c pwm emergency shutdown i bit pwmsdn (pwmie) no yes vector base + $8a to vector base + $82 reserved vector base + $80 low-voltage interrupt (lvi) i bit vregctrl (lvie) no yes vector base + $7e autonomous periodical interrupt (api) i bit vregapictrl (apie) yes yes vector base + $7c high temperature interrupt (hti) i bit vreghtcl (htie) no yes vector base + $7a periodic interrupt timer channel 0 i bit pitinte (pinte0) no yes vector base + $78 periodic interrupt timer channel 1 i bit pitinte (pinte1) no yes vector base + $76 periodic interrupt timer channel 2 i bit pitinte (pinte2) no yes vector base + $74 periodic interrupt timer channel 3 i bit pitinte (pinte3) no yes vector base + $72 to vector base + $40 reserved vector base + $3e atd0 compare interrupt i bit atd0ctl2 (acmpie) yes yes vector base + $3c to vector base + $14 reserved vector base + $12 system call interrupt (sys) none vector base + $10 spurious interrupt none 1 16 bits vector address based table 1-10. interrupt vector locations (sheet 2 of 2) vector address 1 interrupt source ccr mask local enable stop wake up wait wake up
device overview s12xs family s12xs family reference manual, rev. 1.10 54 freescale semiconductor 1.6.3.1 flash con?uration reset sequence phase on each reset, the flash module will hold cpu activity while loading flash module registers from the flash memory. if double faults are detected in the reset phase, flash module protection and security may be active on leaving reset. this is explained in more detail in the flash module section. 1.6.3.2 reset while flash command active if a reset occurs while any flash command is in progress, that command will be immediately aborted. the state of the word being programmed or the sector/block being erased is not guaranteed. 1.6.3.3 i/o pins refer to the pim section for reset con?urations of all peripheral module ports. 1.6.3.4 memory the ram arrays are not initialized out of reset. 1.6.3.5 cop con?uration the cop time-out rate bits cr[2:0] and the wcop bit in the copctl register are loaded from the flash register fopt. see table 1-11 and table 1-12 for coding. the fopt register is loaded from the flash con?uration ?ld byte at global address $7fff0e during the reset sequence. if the mcu is secured the cop time-out rate is always set to the longest period (cr[2:0] = 111) after any reset into special single chip mode. table 1-11. initial cop rate con?uration nv[2:0] in fopt register cr[2:0] in copctl register 000 111 001 110 010 101 011 100 100 011 101 010 110 001 111 000 table 1-12. initial wcop con?uration nv[3] in fopt register wcop in copctl register 10 01
device overview s12xs family s12xs family reference manual, rev. 1.10 freescale semiconductor 55 1.7 atd0 con?uration 1.7.1 external trigger input connection the atd module includes four external trigger inputs etrig0, etrig1, etrig2, and etrig3. the external trigger allows the user to synchronize atd conversion to external trigger events. table 1-13 shows the connection of the external trigger inputs. consult the atd section for information about the analog-to-digital converter module. references to freeze mode are equivalent to active bdm mode. 1.7.2 atd0 channel[17] connection further to the 16 externally available channels, atd0 features an extra channel[17] that is connected to the internal temperature sensor at device level. to access this channel atd0 must use the channel encoding sc:cd:cc:cb:ca = 1:0:0:0:1 in atdctl5. for more temperature sensor information, please refer to 1.8.1 temperature sensor con?uration . 1.8 vreg con?uration the device must be con?ured with the internal voltage regulator enabled. operation in conjunction with an external voltage regulator is not supported. the api trimming register apitr is loaded from the flash ifr option ?ld at global address 0x40_00f0 bits[5:0] during the reset sequence. currently factory programming of this ifr range is not supported. read access to reserved vreg register space returns ?? write accesses have no effect. this device does not support access abort of reserved vreg register space. 1.8.1 temperature sensor con?uration the vreg high temperature trimming register bits vreghttr[3:0] are loaded from the internal flash during the reset sequence. to use the high temperature interrupt within the speci?d limits (t htia and t htid ) these bits must be loaded with 0x8. currently factory programming is not supported. the device temperature can be monitored on atd0 channel[17]. the internal bandgap reference voltage can also be mapped to atd0 analog input channel[17]. the voltage regulator vsel bit when set, maps the bandgap and, when clear, maps the temperature sensor to atd0 channel[17]. table 1-13. atd0 external trigger sources external trigger input connectivity etrig0 pulse width modulator channel 1 etrig1 pulse width modulator channel 3 etrig2 periodic interrupt timer hardware trigger 0 etrig3 periodic interrupt timer hardware trigger 1
device overview s12xs family s12xs family reference manual, rev. 1.10 56 freescale semiconductor 1.9 bdm clock con?uration the bdm alternate clock source is the oscillator clock. 1.10 oscillator con?uration the xclks is an input signal which controls whether a crystal in combination with the internal loop controlled (low power) pierce oscillator is used or whether full swing pierce oscillator/external clock circuitry is used. the xclks signal selects the oscillator con?uration during reset low phase while a clock quality check is ongoing. this is the case for: power on reset or low-voltage reset clock monitor reset any reset while in self-clock mode or full stop mode
device overview s12xs family s12xs family reference manual, rev. 1.10 freescale semiconductor 57 the selected oscillator con?uration is frozen with the rising edge of the reset pin in any of these above described reset cases. figure 1-7. loop controlled pierce oscillator connections ( xclks = 1) figure 1-8. full swing pierce oscillator connections ( xclks = 0) figure 1-9. external clock connections ( xclks = 0) mcu extal xtal v sspll crystal or ceramic resonator c 2 c 1 mcu extal xtal r s r b v sspll crystal or ceramic resonator c 2 c 1 r b =1m ? ; r s speci?d by crystal vendor mcu extal xtal cmos-compatible external oscillator not connected
device overview s12xs family s12xs family reference manual, rev. 1.10 58 freescale semiconductor
s12xs family reference manual, rev. 1.10 freescale semiconductor 59 chapter 2 port integration module (s12xspimv1) revision history 2.1 introduction 2.1.1 overview the s12xs family port integration module establishes the interface between the peripheral modules and the i/o pins for all ports. it controls the electrical pin properties as well as the signal prioritization and multiplexing on shared pins. this document covers: port a, b and k used as general purpose i/o port e associated with the irq, xirq interrupt inputs port t associated with 1 timer module port s associated with 2 sci module and 1 spi module port m associated with 1 mscan port p connected to the pwm - inputs can be used as an external interrupt source port h and j used as general purpose i/o - inputs can be used as an external interrupt source port ad associated with one 16-channel atd module most i/o pins can be con?ured by register bits to select data direction and drive strength, to enable and select pull-up or pull-down devices. revision number revision date sections affected description of changes v01.04 02 apr 2008 corrected reduced drive strength to 1/5 separated pe1,0 bit descriptions from other pe gpio v01.05 31 mar 2009 corrected perj bit description orthographical corrections v01.06 18 dec 2009 table 2-1./2-61 corrected pp0, pm0 pin descriptions added function independency to wired-or bit descriptions minor corrections
port integration module (s12xspimv1) s12xs family reference manual, rev. 1.10 60 freescale semiconductor note this document assumes the availability of all features (112-pin package option). some functions are not available on lower pin count package options. refer to the pin-out summary section. 2.1.2 features the port integration module includes these distinctive registers: data and data direction registers for ports a, b, e, k, t, s, m, p, h, j, and ad when used as general-purpose i/o control registers to enable/disable pull-device and select pull-ups/pull-downs on ports t, s, m, p, h, and j on per-pin basis control registers to enable/disable pull-up devices on port ad on per-pin basis single control register to enable/disable pull-ups on ports a, b, e, and k on per-port basis and on bkgd pin control registers to enable/disable reduced output drive on ports t, s, m, p, h, j, and ad on per-pin basis single control register to enable/disable reduced output drive on ports a, b, e, and k on per-port basis control registers to enable/disable open-drain (wired-or) mode on ports s, and m interrupt ?g register for pin interrupts on ports p, h, and j control register to con?ure irq pin operation routing registers to support module port relocation free-running clock outputs a standard port pin has the following minimum features: input/output selection 5v output drive with two selectable drive strengths 5v digital and analog input input with selectable pull-up or pull-down device optional features supported on dedicated pins: open drain for wired-or connections interrupt inputs with glitch filtering 2.2 external signal description this section lists and describes the signals that connect off-chip. table shows all the pins and their functions that are controlled by the port integration module. refer to the device de?ition for the availability of the individual pins in the different package options.
port integration module (s12xspimv1) s12xs family reference manual, rev. 1.10 freescale semiconductor 61 note if there is more than one function associated with a pin, the priority is indicated by the position in the table from top (highest priority) to bottom (lowest priority) table 2-1. pin functions and priorities port pin name pin function & priority 1 i/o description pin function after reset - bkgd modc 2 i modc input during reset bkgd bkgd i/o s12x_bdm communication pin a pa[7:0] gpio i/o general purpose gpio b pb[7:0] gpio i/o general purpose gpio e pe[7] xclks 2 i external clock selection input during reset gpio eclkx2 o free-running clock at core clock rate (eclk x 2) gpio i/o general purpose pe[6:5] gpio i/o general purpose pe[4] eclk o free-running clock at bus clock rate or programmable down-scaled bus clock gpio i/o general purpose pe[3:2] gpio i/o general purpose pe[1] irq i maskable level- or falling edge-sensitive interrupt gpi i general-purpose pe[0] xirq i non-maskable level-sensitive interrupt gpi i general-purpose k pk[7,5:0] gpio i/o general purpose gpio
port integration module (s12xspimv1) s12xs family reference manual, rev. 1.10 62 freescale semiconductor t pt7 ioc7 i/o timer channel 7 gpio (pwm7) i/o pulse width modulator channel 7; emergency shut-down gpio i/o general purpose pt6 ioc6 i/o timer channel 6 (pwm6) o pulse width modulator channel 6 gpio i/o general purpose pt5 ioc5 i/o timer channel 5 (pwm5) o pulse width modulator channel 5 vreg_api o vreg autonomous periodical interrupt clock gpio i/o general purpose pt4 ioc4 i/o timer channel 4 (pwm4) o pulse width modulator channel 4 gpio i/o general purpose pt[3:0] ioc[3:0] i/o timer channel 3 - 0 gpio i/o general purpose s ps7 ss0 i/o serial peripheral interface 0 slave select output in master mode, input in slave mode or master mode. gpio gpio i/o general purpose ps6 sck0 i/o serial peripheral interface 0 serial clock pin gpio i/o general purpose ps5 mosi0 i/o serial peripheral interface 0 master out/slave in pin gpio i/o general purpose ps4 miso0 i/o serial peripheral interface 0 master in/slave out pin gpio i/o general purpose ps3 txd1 o serial communication interface 1 transmit pin gpio i/o general purpose ps2 rxd1 i serial communication interface 1 receive pin gpio i/o general purpose ps1 txd0 o serial communication interface 0 transmit pin gpio i/o general purpose ps0 rxd0 i serial communication interface 0 receive pin gpio i/o general purpose table 2-1. pin functions and priorities (continued) port pin name pin function & priority 1 i/o description pin function after reset
port integration module (s12xspimv1) s12xs family reference manual, rev. 1.10 freescale semiconductor 63 m pm[7:6] gpio i/o general purpose gpio pm5 (sck0) i/o serial peripheral interface 0 serial clock pin gpio i/o general purpose pm4 (mosi0) i/o serial peripheral interface 0 master out/slave in pin gpio i/o general purpose pm3 ( ss0) i/o serial peripheral interface 0 slave select output in master mode, input in slave mode or master mode. gpio i/o general purpose pm2 (miso0) i/o serial peripheral interface 0 master in/slave out pin gpio i/o general purpose pm1 txcan0 o mscan0 transmit pin (txd1) o serial communication interface 1 transmit pin gpio i/o general purpose pm0 rxcan0 i mscan0 receive pin (rxd1) i serial communication interface 1 receive pin gpio i/o general purpose table 2-1. pin functions and priorities (continued) port pin name pin function & priority 1 i/o description pin function after reset
port integration module (s12xspimv1) s12xs family reference manual, rev. 1.10 64 freescale semiconductor 2.3 memory map and register de?ition this section provides a detailed description of all port integration module registers. p pp7 pwm7 i/o pulse width modulator channel 7; emergency shut-down gpio gpio/kwp7 i/o general purpose; with interrupt pp[6:3] pwm[6:3] o pulse width modulator channel 6 - 3 gpio/kwp[6:3] i/o general purpose; with interrupt pp2 pwm2 o pulse width modulator channel 2 (ioc2) i/o timer channel 2 (txd1) o serial communication interface 1 transmit pin gpio/kwp2 i/o general purpose; with interrupt pp1 pwm1 o pulse width modulator channel 1 (ioc1) i/o timer channel 1 gpio/kwp1 i/o general purpose; with interrupt pp0 pwm0 o pulse width modulator channel 0 (ioc0) i/o timer channel 0 (rxd1) i serial communication interface 1 receive pin gpio/kwp0 i/o general purpose; with interrupt h ph[7:0] gpio/kwh[7:0] i/o general purpose; with interrupt gpio j pj[7:6] gpio/kwj[7:6] i/o general purpose; with interrupt gpio pj[1:0] gpio/kwj[1:0] i/o general purpose; with interrupt ad pad[15:0] gpio i/o general purpose gpio an[15:0] i atd analog 1 signals in brackets denote alternative module routing pins. 2 function active when reset asserted. table 2-1. pin functions and priorities (continued) port pin name pin function & priority 1 i/o description pin function after reset
port integration module (s12xspimv1) s12xs family reference manual, rev. 1.10 freescale semiconductor 65 2.3.1 memory map table 2-2 shows the register map of the port integration module. table 2-2. block memory map port offset or address register access reset value section/page a b 0x0000 porta?ort a data register r/w 0x00 2.3.3/2-75 0x0001 portb?ort b data register r/w 0x00 2.3.4/2-75 0x0002 ddra?ort a data direction register r/w 0x00 2.3.5/2-76 0x0003 ddrb?ort b data direction register r/w 0x00 2.3.6/2-76 0x0004 : 0x0007 pim reserved r 0x00 2.3.7/2-77 e 0x0008 porte?ort e data register r/w 1 0x00 2.3.8/2-77 0x0009 ddre?ort e data direction register r/w 1 0x00 2.3.9/2-78 0x000a : 0x000b non-pim address range 2 - - - a b e k 0x000c pucr?ull-up control register r/w 1 0xd0 2.3.10/2-79 0x000d rdriv?educed drive register r/w 1 0x00 2.3.11/2-80 0x000e : 0x001b non-pim address range 2 - - - e 0x001c eclkctl?clk control register r/w 1 0b 3 100_0000 2.3.12/2-81 0x001d pim reserved r 0x00 2.3.13/2-82 0x001e irqcr?rq control register r/w 1 0x40 2.3.14/2-83 0x001f pim reserved r 0x00 2.3.15/2-83 0x0020 : 0x0031 non-pim address range 2 - - - k 0x0032 portk?ort k data register r/w 0x00 2.3.16/2-84 0x0033 ddrk?ort k data direction register r/w 0x00 2.3.17/2-84 0x0034 : 0x023f non-pim address range 2 - - -
port integration module (s12xspimv1) s12xs family reference manual, rev. 1.10 66 freescale semiconductor t 0x0240 ptt?ort t data register r/w 0x00 2.3.18/2-85 0x0241 ptit?ort t input register r 4 2.3.19/2-86 0x0242 ddrt?ort t data direction register r/w 0x00 2.3.20/2-87 0x0243 rdrt?ort t reduced drive register r/w 0x00 2.3.21/2-87 0x0244 pert?ort t pull device enable register r/w 0x00 2.3.22/2-88 0x0245 ppst?ort t polarity select register r/w 0x00 2.3.23/2-88 0x0246 pim reserved r 0x00 2.3.24/2-89 0x0247 port t routing register r/w 0x00 2.3.25/2-89 s 0x0248 pts?ort s data register r/w 0x00 2.3.26/2-91 0x0249 ptis?ort s input register r 4 2.3.27/2-92 0x024a ddrs?ort s data direction register r/w 0x00 2.3.28/2-93 0x024b rdrs?ort s reduced drive register r/w 0x00 2.3.29/2-94 0x024c pers?ort s pull device enable register r/w 0xff 2.3.30/2-94 0x024d ptps?ort s polarity select register r/w 0x00 2.3.31/2-95 0x024e woms?ort s wired-or mode register r/w 0x00 2.3.32/2-95 0x024f pim reserved r 0x00 2.3.33/2-96 m 0x0250 ptm?ort m data register r/w 0x00 2.3.34/2-96 0x0251 ptim?ort m input register r 4 2.3.35/2-98 0x0252 ddrm?ort m data direction register r/w 0x00 2.3.36/2-98 0x0253 rdrm?ort m reduced drive register r/w 0x00 2.3.37/2-99 0x0254 perm?ort m pull device enable register r/w 0x00 2.3.38/2-100 0x0255 ppsm?ort m polarity select register r/w 0x00 2.3.39/2-100 0x0256 womm?ort m wired-or mode register r/w 0x00 2.3.40/2-101 0x0257 modrr?odule routing register r/w 0x00 2.3.41/2-101 p 0x0258 ptp?ort p data register r/w 0x00 2.3.42/2-102 0x0259 ptip?ort p input register r 4 2.3.43/2-104 0x025a ddrp?ort p data direction register r/w 0x00 2.3.44/2-105 0x025b rdrp?ort p reduced drive register r/w 0x00 2.3.45/2-106 0x025c perp?ort p pull device enable register r/w 0x00 2.3.46/2-106 0x025d ptpp?ort p polarity select register r/w 0x00 2.3.47/2-107 0x025e piep?ort p interrupt enable register r/w 0x00 2.3.48/2-107 0x025f pifp?ort p interrupt flag register r/w 0x00 2.3.49/2-108 table 2-2. block memory map (continued) port offset or address register access reset value section/page
port integration module (s12xspimv1) s12xs family reference manual, rev. 1.10 freescale semiconductor 67 h 0x0260 pth?ort h data register r/w 0x00 2.3.50/2-108 0x0261 ptih?ort h input register r 4 2.3.51/2-109 0x0262 ddrh?ort h data direction register r/w 0x00 2.3.52/2-109 0x0263 rdrh?ort h reduced drive register r/w 0x00 2.3.53/2-110 0x0264 perh?ort h pull device enable register r/w 0x00 2.3.54/2-110 0x0265 ppsh?ort h polarity select register r/w 0x00 2.3.55/2-111 0x0266 pieh?ort h interrupt enable register r/w 0x00 2.3.56/2-111 0x0267 pifh?ort h interrupt flag register r/w 0x00 2.3.57/2-112 j 0x0268 ptj?ort j data register r/w 0x00 2.3.58/2-112 0x0269 ptij?ort j input register r 4 2.3.59/2-113 0x026a ddrj?ort j data direction register r/w 0x00 2.3.60/2-113 0x026b rdrj?ort j reduced drive register r/w 0x00 2.3.61/2-114 0x026c perj?ort j pull device enable register r/w 0xff 2.3.62/2-114 0x026d ppsj?ort j polarity select register r/w 0x00 2.3.63/2-115 0x026e piej?ort j interrupt enable register r/w 0x00 2.3.64/2-115 0x026f pifj?ort j interrupt flag register r/w 0x00 2.3.65/2-116 ad 0x0270 pt0ad0?ort ad0 data register 0 r/w 0x00 2.3.66/2-116 0x0271 pt1ad0?ort ad0 data register 1 r/w 0x00 2.3.67/2-117 0x0272 ddr0ad0?ort ad0 data direction register 0 r/w 0x00 2.3.68/2-117 0x0273 ddr1ad0?ort ad0 data direction register 1 r/w 0x00 2.3.69/2-118 0x0274 rdr0ad0?ort ad0 reduced drive register 0 r/w 0x00 2.3.70/2-118 0x0275 rdr1ad0?ort ad0 reduced drive register 1 r/w 0x00 2.3.71/2-119 0x0276 per0ad0?ort ad0 pull up enable register 0 r/w 0x00 2.3.72/2-119 0x0277 per1ad0?ort ad0 pull up enable register 1 r/w 0x00 2.3.73/2-120 0x0278 : 0x027f pim reserved r 0x00 2.3.74/2-120 1 write access not applicable for one or more register bits. refer to register description. 2 refer to memory map in soc guide to determine related module. 3 mode dependent. 4 read always returns logic level on pins. table 2-2. block memory map (continued) port offset or address register access reset value section/page
port integration module (s12xspimv1) s12xs family reference manual, rev. 1.10 68 freescale semiconductor register name bit 7 6 5 4 3 2 1 bit 0 0x0000 porta r pa7pa6pa5pa4pa3pa2pa1pa0 w 0x0001 portb r pb7 pb6 pb5 pb4 pb3 pb2 pb1 pb0 w 0x0002 ddra r ddra7 ddra6 ddra5 ddra4 ddra3 ddra2 ddra1 ddra0 w 0x0003 ddrb r ddrb7 ddrb6 ddrb5 ddrb4 ddrb3 ddrb2 ddrb1 ddrb0 w 0x0004 reserved r00000000 w 0x0005 reserved r00000000 w 0x0006 reserved r00000000 w 0x0007 reserved r00000000 w 0x0008 porte r pe7 pe6 pe5 pe4 pe3 pe2 pe1 pe0 w 0x0009 ddre r ddre7 ddre6 ddre5 ddre4 ddre3 ddre2 00 w 0x000a 0x000b non-pim address range r non-pim address range w 0x000c pucr r pupke bkpue 0 pupee 00 pupbe pupae w 0x000d rdriv r rdpk 00 rdpe 00 rdpb rdpa w 0x000e 0x001b non-pim address range r non-pim address range w = unimplemented or reserved
port integration module (s12xspimv1) s12xs family reference manual, rev. 1.10 freescale semiconductor 69 0x001c eclkctl r neclk nclkx2 div16 ediv4 ediv3 ediv2 ediv1 ediv0 w 0x001d reserved r00000000 w 0x001e irqcr r irqe irqen 000000 w 0x001f reserved r00000000 w 0x0020 0x0031 non-pim address range r non-pim address range w 0x0032 portk r pk7 0 pk5 pk4 pk3 pk2 pk1 pk0 w 0x0033 ddrk r ddrk7 0 ddrk5 ddrk4 ddrk3 ddrk2 ddrk1 ddrk0 w 0x0034 0x023f non-pim address range r non-pim address range w 0x0240 ptt r ptt7 ptt6 ptt5 ptt4 ptt3 ptt2 ptt1 ptt0 w 0x0241 ptit r ptit7 ptit6 ptit5 ptit4 ptit3 ptit2 ptit1 ptit0 w 0x0242 ddrt r ddrt7 ddrt6 ddrt5 ddrt4 ddrt3 ddrt2 ddrt1 ddrt0 w 0x0243 rdrt r rdrt7 rdrt6 rdrt5 rdrt4 rdrt3 rdrt2 rdrt1 rdrt0 w 0x0244 pert r pert7 pert6 pert5 pert4 pert3 pert2 pert1 pert0 w 0x0245 ppst r ppst7 ppst6 ppst5 ppst4 ppst3 ppst2 ppst1 ppst0 w register name bit 7 6 5 4 3 2 1 bit 0 = unimplemented or reserved
port integration module (s12xspimv1) s12xs family reference manual, rev. 1.10 70 freescale semiconductor 0x0246 reserved r00000000 w 0x0247 pttrr r pttrr7 pttrr6 pttrr5 pttrr4 0 pttrr2 pttrr1 pttrr0 w 0x0248 pts r pts7 pts6 pts5 pts4 pts3 pts2 pts1 pts0 w 0x0249 ptis r ptis7 ptis6 ptis5 ptis4 ptis3 ptis2 ptis1 ptis0 w 0x024a ddrs r ddrs7 ddrs6 ddrs5 ddrs4 ddrs3 ddrs2 ddrs1 ddrs0 w 0x024b rdrs r rdrs7 rdrs6 rdrs5 rdrs4 rdrs3 rdrs2 rdrs1 rdrs0 w 0x024c pers r pers7 pers6 pers5 pers4 pers3 pers2 pers1 pers0 w 0x024d ppss r ppss7 ppss6 ppss5 ppss4 ppss3 ppss2 ppss1 ppss0 w 0x024e woms r woms7 woms6 woms5 woms4 woms3 woms2 woms1 woms0 w 0x024f reserved r00000000 w 0x0250 ptm r ptm7 ptm6 ptm5 ptm4 ptm3 ptm2 ptm1 ptm0 w 0x0251 ptim r ptim7 ptim6 ptim5 ptim4 ptim3 ptim2 ptim1 ptim0 w 0x0252 ddrm r ddrm7 ddrm6 ddrm5 ddrm4 ddrm3 ddrm2 ddrm1 ddrm0 w 0x0253 rdrm r rdrm7 rdrm6 rdrm5 rdrm4 rdrm3 rdrm2 rdrm1 rdrm0 w 0x0254 perm r perm7 perm6 perm5 perm4 perm3 perm2 perm1 perm0 w 0x0255 ppsm r ppsm7 ppsm6 ppsm5 ppsm4 ppsm3 ppsm2 ppsm1 ppsm0 w register name bit 7 6 5 4 3 2 1 bit 0 = unimplemented or reserved
port integration module (s12xspimv1) s12xs family reference manual, rev. 1.10 freescale semiconductor 71 0x0256 womm r womm7 womm6 womm5 womm4 womm3 womm2 womm1 womm0 w 0x0257 modrr r modrr7 modrr6 0 modrr4 0000 w 0x0258 ptp r ptp7 ptp6 ptp5 ptp4 ptp3 ptp2 ptp1 ptp0 w 0x0259 ptip r ptip7 ptip6 ptip5 ptip4 ptip3 ptip2 ptip1 ptip0 w 0x025a ddrp r ddrp7 ddrp6 ddrp5 ddrp4 ddrp3 ddrp2 ddrp1 ddrp0 w 0x025b rdrp r rdrp7 rdrp6 rdrp5 rdrp4 rdrp3 rdrp2 rdrp1 rdrp0 w 0x025c perp r perp7 perp6 perp5 perp4 perp3 perp2 perp1 perp0 w 0x025d ppsp r ppsp7 ppsp6 ppsp5 ppsp4 ppsp3 ppsp2 ppsp1 ppsp0 w 0x025e piep r piep7 piep6 piep5 piep4 piep3 piep2 piep1 piep0 w 0x025f pifp r pifp7 pifp6 pifp5 pifp4 pifp3 pifp2 pifp1 pifp0 w 0x0260 pth r pth7 pth6 pth5 pth4 pth3 pth2 pth1 pth0 w 0x0261 ptih r ptih7 ptih6 ptih5 ptih4 ptih3 ptih2 ptih1 ptih0 w 0x0262 ddrh r ddrh7 ddrh6 ddrh5 ddrh4 ddrh3 ddrh2 ddrh1 ddrh0 w 0x0263 rdrh r rdrh7 rdrh6 rdrh5 rdrh4 rdrh3 rdrh2 rdrh1 rdrh0 w 0x0264 perh r perh7 perh6 perh5 perh4 perh3 perh2 perh1 perh0 w register name bit 7 6 5 4 3 2 1 bit 0 = unimplemented or reserved
port integration module (s12xspimv1) s12xs family reference manual, rev. 1.10 72 freescale semiconductor 0x0265 ppsh r ppsh7 ppsh6 ppsh5 ppsh4 ppsh3 ppsh2 ppsh1 ppsh0 w 0x0266 pieh r pieh7 pieh6 pieh5 pieh4 pieh3 pieh2 pieh1 pieh0 w 0x0267 pifh r pifh7 pifh6 pifh5 pifh4 pifh3 pifh2 pifh1 pifh0 w 0x0268 ptj r ptj7 ptj6 0000 ptj1 ptj0 w 0x0269 ptij r ptij7 ptij6 0 0 0 0 ptij1 ptij0 w 0x026a ddrj r ddrj7 ddrj6 0000 ddrj1 ddrj0 w 0x026b rdrj r rdrj7 rdrj6 0000 rdrj1 rdrj0 w 0x026c perj r perj7 perj6 0000 perj1 perj0 w 0x026d ppsj r ppsj7 ppsj6 0000 ppsj1 ppsj0 w 0x026e piej r piej7 piej6 0000 piej1 piej0 w 0x026f pifj r pifj7 pifj6 0000 pifj1 pifj0 w 0x0270 pt0ad0 r pt0ad07 pt0ad06 pt0ad05 pt0ad04 pt0ad03 pt0ad02 pt0ad01 pt0ad00 w 0x0271 pt1ad0 r pt1ad07 pt1ad06 pt1ad05 pt1ad04 pt1ad03 pt1ad02 pt1ad01 pt1ad00 w 0x0272 ddr0ad0 r ddr0ad07 ddr0ad06 ddr0ad05 ddr0ad04 ddr0ad03 ddr0ad02 ddr0ad01 ddr0ad00 w 0x0273 ddr1ad0 r ddr1ad07 ddr1ad06 ddr1ad05 ddr1ad04 ddr1ad03 ddr1ad02 ddr1ad01 ddr1ad00 w 0x0274 rdr0ad0 r rdr0ad07 rdr0ad06 rdr0ad05 rdr0ad04 rdr0ad03 rdr0ad02 rdr0ad01 rdr0ad00 w register name bit 7 6 5 4 3 2 1 bit 0 = unimplemented or reserved
port integration module (s12xspimv1) s12xs family reference manual, rev. 1.10 freescale semiconductor 73 2.3.2 register descriptions the following table summarizes the effect of the various con?uration bits, i.e. data direction (ddr), output level (io), reduced drive (rdr), pull enable (pe), pull select (ps) on the pin function and pull device activity. the con?uration bit ps is used for two purposes: 1. con?ure the sensitive interrupt edge (rising or falling), if interrupt enabled. 2. select either a pull-up or pull-down device if pe is active. 0x0275 rdr1ad0 r rdr1ad07 rdr1ad06 rdr1ad05 rdr1ad04 rdr1ad03 rdr1ad02 rdr1ad01 rdr1ad00 w 0x0276 per0ad0 r per0ad07 per0ad06 per0ad05 per0ad04 per0ad03 per0ad02 per0ad01 per0ad00 w 0x0277 per1ad0 r per1ad07 per1ad06 per1ad05 per1ad04 per1ad03 per1ad02 per1ad01 per1ad00 w 0x0278 reserved r00000000 w 0x0279 reserved r00000000 w 0x027a reserved r00000000 w 0x027b reserved r00000000 w 0x027c reserved r00000000 w 0x027d reserved r00000000 w 0x027e reserved r00000000 w 0x027f reserved r00000000 w register name bit 7 6 5 4 3 2 1 bit 0 = unimplemented or reserved
port integration module (s12xspimv1) s12xs family reference manual, rev. 1.10 74 freescale semiconductor table 2-3. pin con?uration summary note all register bits in this module are completely synchronous to internal clocks during a register read. note figures of port data registers also display the alternative functions if applicable on the related pin as de?ed in table . names in brackets denote the availability of the function when using a speci? routing option. note figures of module routing registers also display the module instance or module channel associated with the related routing bit. ddr io rdr pe ps 1 1 always ??on port a, b, e, k, and ad. ie 2 2 applicable only on port p, h, and j. function pull device interrupt 0 x x 0 x 0 input disabled disabled 0 x x 1 0 0 input pull up disabled 0 x x 1 1 0 input pull down disabled 0 x x 0 0 1 input disabled falling edge 0 x x 0 1 1 input disabled rising edge 0 x x 1 0 1 input pull up falling edge 0 x x 1 1 1 input pull down rising edge 1 0 0 x x 0 output, full drive to 0 disabled disabled 1 1 0 x x 0 output, full drive to 1 disabled disabled 1 0 1 x x 0 output, reduced drive to 0 disabled disabled 1 1 1 x x 0 output, reduced drive to 1 disabled disabled 1 0 0 x 0 1 output, full drive to 0 disabled falling edge 1 1 0 x 1 1 output, full drive to 1 disabled rising edge 1 0 1 x 0 1 output, reduced drive to 0 disabled falling edge 1 1 1 x 1 1 output, reduced drive to 1 disabled rising edge
port integration module (s12xspimv1) s12xs family reference manual, rev. 1.10 freescale semiconductor 75 2.3.3 port a data register (porta) 2.3.4 port b data register (portb) address 0x0000 (prr) access: user read/write 1 1 read: anytime. the data source depends on the data direction value. write: anytime. 76543210 r pa 7 pa 6 pa 5 pa4 pa3 pa2 pa1 pa0 w reset 00000000 figure 2-1. port a data register (porta) table 2-4. porta register field descriptions field description 7-0 pa port a general purpose input/output data ?ata register the associated pin can be used as general purpose i/o. in general purpose output mode the register bit value is driven to the pin. if the associated data direction bit is set to 1, a read returns the value of the port register bit, otherwise the buffered pin input state is read. address 0x0001 (prr) access: user read/write 1 1 read: anytime. the data source depends on the data direction value. write: anytime. 76543210 r pb7 pb6 pb5 pb4 pb3 pb2 pb1 pb0 w reset 00000000 figure 2-2. port b data register (portb) table 2-5. portb register field descriptions field description 7-0 pb port b general purpose input/output data ?ata register the associated pin can be used as general purpose i/o. in general purpose output mode the register bit value is driven to the pin. if the associated data direction bit is set to 1, a read returns the value of the port register bit, otherwise the buffered pin input state is read.
port integration module (s12xspimv1) s12xs family reference manual, rev. 1.10 76 freescale semiconductor 2.3.5 port a data direction register (ddra) 2.3.6 port b data direction register (ddrb) address 0x0002 (prr) access: user read/write 1 1 read: anytime. the data source depends on the data direction value. write: anytime. 76543210 r ddra7 ddra6 ddra5 ddra4 ddra3 ddra2 ddra1 ddra0 w reset 00000000 figure 2-3. port a data direction register (ddra) table 2-6. ddra register field descriptions field description 7-0 ddra port a data direction this bit determines whether the associated pin is an input or output. 1 associated pin con?ured as output 0 associated pin con?ured as input address 0x0003 (prr) access: user read/write 1 1 read: anytime. the data source depends on the data direction value. write: anytime. 76543210 r ddrb7 ddrb6 ddrb5 ddrb4 ddrb3 ddrb2 ddrb1 ddrb0 w reset 00000000 figure 2-4. port b data direction register (ddrb) table 2-7. ddrb register field descriptions field description 7-0 ddrb port b data direction this bit determines whether the associated pin is an input or output. 1 associated pin con?ured as output 0 associated pin con?ured as input
port integration module (s12xspimv1) s12xs family reference manual, rev. 1.10 freescale semiconductor 77 2.3.7 pim reserved registers 2.3.8 port e data register (porte) address 0x0004 (prr) to 0x0007 (prr) access: user read 1 1 read: always reads 0x00 write: unimplemented 76543210 r00000000 w reset 00000000 = unimplemented or reserved figure 2-5. pim reserved registers address 0x0008 (prr) access: user read/write 1 1 read: anytime. the data source depends on the data direction value. write: anytime. 76543210 r pe7 pe6 pe5 pe4 pe3 pe2 pe1 pe0 w altern. function xclks eclk irq xirq eclkx2 reset 000000 2 2 these registers are reset to zero. two bus clock cycles after reset release the register values are updated with the associated pin values. 2 = unimplemented or reserved figure 2-6. port e data register (porte)
port integration module (s12xspimv1) s12xs family reference manual, rev. 1.10 78 freescale semiconductor 2.3.9 port e data direction register (ddre) table 2-8. porte register field descriptions field description 7 pe port e general purpose input/output data ?ata register, eclkx2 output, xclks input when not used with the alternative function, the associated pin can be used as general purpose i/o. in general purpose output mode the register bit value is driven to the pin. if the associated data direction bit is set to 1, a read returns the value of the port register bit, otherwise the buffered pin input state is read. the eclkx2 output function takes precedence over the general purpose i/o function if enabled. the external clock selection feature ( xclks) is only active during reset=0 6-5, 3-2 pe port e general purpose input/output data ?ata register the associated pin can be used as general purpose i/o. in general purpose output mode the register bit value is driven to the pin. if the associated data direction bit is set to 1, a read returns the value of the port register bit, otherwise the buffered pin input state is read. 4 pe port e general purpose input/output data ?ata register, eclk output when not used with the alternative function, the associated pin can be used as general purpose i/o. in general purpose output mode the register bit value is driven to the pin. if the associated data direction bit is set to 1, a read returns the value of the port register bit, otherwise the buffered pin input state is read. the eclk output function takes precedence over the general purpose i/o function if enabled. 1 pe port e general purpose input data and interrupt ?ata register, irq input. this pin can be used as general purpose and irq input. 0 pe port e general purpose input data and interrupt ?ata register, xirq input. this pin can be used as general purpose and xirq input. address 0x0009 (prr) access: user read/write 1 1 read: anytime. the data source depends on the data direction value. write: anytime. 76543210 r ddre7 ddre6 ddre5 ddre4 ddre3 ddre2 00 w reset 00000000 = unimplemented or reserved figure 2-7. port e data direction register (ddre)
port integration module (s12xspimv1) s12xs family reference manual, rev. 1.10 freescale semiconductor 79 2.3.10 ports abek, bkgd pin pull-up control register (pucr) table 2-9. ddre register field descriptions field description 7-2 ddre port e data direction this bit determines whether the associated pin is an input or output. 1 associated pin con?ured as output 0 associated pin con?ured as input address 0x000c (prr) access: user read/write 1 1 read: anytime in single-chip modes. write: anytime, except bkpue which is writable in special single-chip mode only. 76543210 r pupke bkpue 0 pupee 00 pupbe pupae w reset 11010000 = unimplemented or reserved figure 2-8. ports abek, bkgd pin pull-up control register (pucr) table 2-10. pucr register field descriptions field description 7 pupke port k pull-up enable ?nable pull-up devices on all port input pins this bit con?ures whether a pull-up device is activated on all associated port input pins. if a pin is used as output this bit has no effect. 1 pull-up device enabled 0 pull-up device disabled 6 bkpue bkgd pin pull-up enable ?nable pull-up device on pin this bit con?ures whether a pull-up device is activated, if the pin is used as input. if a pin is used as output this bit has no effect. 1 pull-up device enabled 0 pull-up device disabled 4 pupee port e pull-up enable ?nable pull-up devices on all port input pins except pins 5 and 6 this bit con?ures whether a pull-up device is activated on all associated port input pins. if a pin is used as output this bit has no effect. pins 5 and 6 have pull-down devices enabled only during reset. this bit has no effect on these pins. 1 pull-up device enabled 0 pull-up device disabled
port integration module (s12xspimv1) s12xs family reference manual, rev. 1.10 80 freescale semiconductor 2.3.11 ports abek reduced drive register (rdriv) this register is used to select reduced drive for the pins associated with ports a, b, e, and k. if enabled, the pins drive at approx. 1/5 of the full drive strength. 1 pupbe port b pull-up enable ?nable pull-up devices on all port input pins this bit con?ures whether a pull-up device is activated on all associated port input pins. if a pin is used as output this bit has no effect. 1 pull-up device enabled 0 pull-up device disabled 0 pupae port a pull-up enable ?nable pull-up devices on all port input pins this bit con?ures whether a pull-up device is activated on all associated port input pins. if a pin is used as output this bit has no effect. 1 pull-up device enabled 0 pull-up device disabled address 0x000d (prr) access: user read/write 1 1 read: anytime. the data source depends on the data direction value. write: anytime. 76543210 r rdpk 00 rdpe 00 rdpb rdpa w reset 00000000 = unimplemented or reserved figure 2-9. ports abek reduced drive register (rdriv) table 2-11. rdriv register field descriptions field description 7 rdpk port k reduced drive ?elect reduced drive for output port this bit con?ures the drive strength of all associated port output pins as either full or reduced. if a pin is used as input this bit has no effect. the reduced drive function is independent of which function is being used on a particular pin. 1 reduced drive selected (approx. 1/5 of the full drive strength) 0 full drive strength enabled 4 rdpe port e reduced drive ?elect reduced drive for output port this bit con?ures the drive strength of all associated port output pins as either full or reduced. if a pin is used as input this bit has no effect. the reduced drive function is independent of which function is being used on a particular pin. 1 reduced drive selected (approx. 1/5 of the full drive strength) 0 full drive strength enabled table 2-10. pucr register field descriptions (continued) field description
port integration module (s12xspimv1) s12xs family reference manual, rev. 1.10 freescale semiconductor 81 2.3.12 eclk control register (eclkctl) 1 rdpb port b reduced drive ?elect reduced drive for output port this bit con?ures the drive strength of all associated port output pins as either full or reduced. if a pin is used as input this bit has no effect. the reduced drive function is independent of which function is being used on a particular pin. 1 reduced drive selected (approx. 1/5 of the full drive strength) 0 full drive strength enabled 0 rdpa port a reduced drive ?elect reduced drive for output port this bit con?ures the drive strength of all associated port output pins as either full or reduced. if a pin is used as input this bit has no effect. the reduced drive function is independent of which function is being used on a particular pin. 1 reduced drive selected (approx. 1/5 of the full drive strength) 0 full drive strength enabled address 0x001c (prr) access: user read/write 1 1 read: anytime. write: anytime. 76543210 r neclk nclkx2 div16 ediv4 ediv3 ediv2 ediv1 ediv0 w reset: mode depen- dent 1000000 special single-chip 01000000 normal single-chip 11000000 = unimplemented or reserved figure 2-10. eclk control register (eclkctl) table 2-11. rdriv register field descriptions (continued) field description
port integration module (s12xspimv1) s12xs family reference manual, rev. 1.10 82 freescale semiconductor 2.3.13 pim reserved register table 2-12. eclkctl register field descriptions field description 7 neclk no eclk ?isable eclk output this bit controls the availability of a free-running clock on the eclk pin. this clock has a xed rate equivalent to the internal bus clock. 1 eclk disabled 0 eclk enabled 6 nclkx2 no eclkx2 ?isable eclkx2 output this bit controls the availability of a free-running clock on the eclkx2 pin. this clock has a ?ed rate of twice the internal bus clock. 1 eclkx2 disabled 0 eclkx2 enabled 5 div16 free-running eclk predivider ?ivide by 16 this bit enables a divide-by-16 stage on the selected ediv rate. 1 divider enabled: eclk rate = ediv rate divided by 16 0 divider disabled: eclk rate = ediv rate 4-0 ediv free-running eclk divider ?on?ure eclk rate these bits determine the rate of the free-running clock on the eclk pin. 00000 eclk rate = bus clock rate 00001 eclk rate = bus clock rate divided by 2 00010 eclk rate = bus clock rate divided by 3, ... 11111 eclk rate = bus clock rate divided by 32 address 0x001d (prr) access: user read 1 1 read: always reads 0x00 write: unimplemented 76543210 r00000000 w reset 00000000 = unimplemented or reserved figure 2-11. pim reserved register
port integration module (s12xspimv1) s12xs family reference manual, rev. 1.10 freescale semiconductor 83 2.3.14 irq control register (irqcr) 2.3.15 pim reserved register pimtest 1 this register is reserved for factory testing of the pim module and is not available in normal operation. writing to this register when in special modes can alter the pin functionality. address 0x001e access: user read/write 1 1 read: see individual bit descriptions below. write: see individual bit descriptions below. 76543210 r irqe irqen 000000 w reset 01000000 = unimplemented or reserved figure 2-12. irq control register (irqcr) table 2-13. irqcr register field descriptions field description 7 irqe irq select edge sensitive only special mode: read or write anytime. normal mode: read anytime, write once. 1 irq con?ured to respond only to falling edges. falling edges on the irq pin will be detected anytime irqe=1 and will be cleared only upon a reset or the servicing of the irq interrupt. 0 irq con?ured for low level recognition. 6 irqen irq enable read or write anytime. 1 irq pin is connected to interrupt logic. 0 irq pin is disconnected from interrupt logic. 1. implementation pim_xe.01.01 and later address 0x001f access: user read 1 76543210 r00000000 w reset 00000000 = unimplemented or reserved figure 2-13. pim reserved register
port integration module (s12xspimv1) s12xs family reference manual, rev. 1.10 84 freescale semiconductor 2.3.16 port k data register (portk) 2.3.17 port k data direction register (ddrk) 1 read: always reads 0x00 write: unimplemented address 0x0032 (prr) access: user read/write 1 1 read: anytime. the data source depends on the data direction value. write: anytime. 76543210 r pk7 0 pk5 pk4 pk3 pk2 pk1 pk0 w reset 00000000 figure 2-14. port k data register (portk) table 2-14. portk register field descriptions field description 7,5-0 pk port k general purpose input/output data ?ata register the associated pin can be used as general purpose i/o. in general purpose output mode the register bit value is driven to the pin. if the associated data direction bit is set to 1, a read returns the value of the port register bit, otherwise the buffered pin input state is read. address 0x0033 (prr) access: user read/write 1 1 read: anytime. the data source depends on the data direction value. write: anytime. 76543210 r ddrk7 0 ddrk5 ddrk4 ddrk3 ddrk2 ddrk1 ddrk0 w reset 00000000 figure 2-15. port k data direction register (ddrk)
port integration module (s12xspimv1) s12xs family reference manual, rev. 1.10 freescale semiconductor 85 2.3.18 port t data register (ptt) table 2-15. ddrk register field descriptions field description 7,5-0 ddrk port k data direction this bit determines whether the associated pin is an input or output. 1 associated pin con?ured as output 0 associated pin con?ured as input address 0x0240 access: user read/write 1 1 read: anytime. the data source depends on the data direction value. write: anytime. 76543210 r ptt7 ptt6 ptt5 ptt4 ptt3 ptt2 ptt1 ptt0 w altern. function ioc7 ioc6 ioc5 ioc4 ioc3 ioc2 ioc1 ioc0 (pwm7) (pwm6) (pwm5) (pwm4) vreg_api reset 00000000 figure 2-16. port t data register (ptt) table 2-16. ptt register field descriptions field description 7-6, 4 ptt port t general purpose input/output data ?ata register, tim output, routed pwm output when not used with the alternative function, the associated pin can be used as general purpose i/o. in general purpose output mode the register bit value is driven to the pin. if the associated data direction bit is set to 1, a read returns the value of the port register bit, otherwise the buffered pin input state is read. the tim output function takes precedence over the routed pwm and the general purpose i/o function if the related channel is enabled. the routed pwm function takes precedence over the general purpose i/o function if the related channel is enabled.
port integration module (s12xspimv1) s12xs family reference manual, rev. 1.10 86 freescale semiconductor 2.3.19 port t input register (ptit) 5 ptt port t general purpose input/output data ?ata register, tim output, routed pwm output, vreg_api output when not used with the alternative function, the associated pin can be used as general purpose i/o. in general purpose output mode the register bit value is driven to the pin. if the associated data direction bit is set to 1, a read returns the value of the port register bit, otherwise the buffered pin input state is read. the tim output function takes precedence over the routed pwm, vreg_api function and the general purpose i/o function if the related channel is enabled. the routed pwm function takes precedence over vreg_api and the general purpose i/o function if the related channel is enabled. the vreg_api takes precedence over the general purpose i/o function if enabled. 3-0 ptt port t general purpose input/output data ?ata register, tim output when not used with the alternative function, the associated pin can be used as general purpose i/o. in general purpose output mode the register bit value is driven to the pin. if the associated data direction bit is set to 1, a read returns the value of the port register bit, otherwise the buffered pin input state is read. the tim output function takes precedence over the general purpose i/o function if the related channel is enabled. address 0x0241 access: user read 1 1 read: anytime. write:never, writes to this register have no effect. 76543210 r ptit7 ptit6 ptit5 ptit4 ptit3 ptit2 ptit1 ptit0 w reset uuuuuuuu = unimplemented or reserved u = unaffected by reset figure 2-17. port t input register (ptit) table 2-17. ptit register field descriptions field description 7-0 ptit port t input data a read always returns the buffered input state of the associated pin. it can be used to detect overload or short circuit conditions on output pins. table 2-16. ptt register field descriptions (continued) field description
port integration module (s12xspimv1) s12xs family reference manual, rev. 1.10 freescale semiconductor 87 2.3.20 port t data direction register (ddrt) 2.3.21 port t reduced drive register (rdrt) address 0x0242 access: user read/write 1 1 read: anytime. write: anytime. 76543210 r ddrt7 ddrt6 ddrt5 ddrt4 ddrt3 ddrt2 ddrt1 ddrt0 w reset 00000000 figure 2-18. port t data direction register (ddrt) table 2-18. ddrt register field descriptions field description 7-6, 4 ddrt port t data direction this bit determines whether the pin is an input or output. the tim forces the i/o state to be an output for a timer port associated with an enabled output compare. else the routed pwm forces the i/o state to be an output for an enabled channel. in these cases the data direction bit will not change. 1 associated pin con?ured as output 0 associated pin con?ured as input 5 ddrt port t data direction this bit determines whether the pin is an input or output. the tim forces the i/o state to be an output for a timer port associated with an enabled output compare. else the routed pwm forces the i/o state to be an output for an enabled channel. else the vreg_api forces the i/o state to be an output if enabled. in these cases the data direction bit will not change. 1 associated pin con?ured as output 0 associated pin con?ured as input 3-0 ddrt port t data direction this bit determines whether the pin is an input or output. the tim forces the i/o state to be an output for a timer port associated with an enabled output compare. in this case the data direction bit will not change. 1 associated pin con?ured as output 0 associated pin con?ured as input address 0x0243 access: user read/write 1 76543210 r rdrt7 rdrt6 rdrt5 rdrt4 rdrt3 rdrt2 rdrt1 rdrt0 w reset 00000000 figure 2-19. port t reduced drive register (rdrt)
port integration module (s12xspimv1) s12xs family reference manual, rev. 1.10 88 freescale semiconductor 2.3.22 port t pull device enable register (pert) 2.3.23 port t polarity select register (ppst) 1 read: anytime. write: anytime. table 2-19. rdrt register field descriptions field description 7-0 rdrt port t reduced drive ?elect reduced drive for output pin this bit con?ures the drive strength of the associated output pin as either full or reduced. if a pin is used as input this bit has no effect. the reduced drive function is independent of which function is being used on a particular pin. 1 reduced drive selected (approx. 1/5 of the full drive strength) 0 full drive strength enabled address 0x0244 access: user read/write 1 1 read: anytime. write: anytime. 76543210 r pert7 pert6 pert5 pert4 pert3 pert2 pert1 pert0 w reset 00000000 figure 2-20. port t pull device enable register (pert) table 2-20. pert register field descriptions field description 7-0 pert port t pull device enable ?nable pull device on input pin this bit controls whether a pull device on the associated port input pin is active. if a pin is used as output this bit has no effect. the polarity is selected by the related polarity select register bit. 1 pull device enabled 0 pull device disabled address 0x0245 access: user read/write 1 1 read: anytime. write: anytime. 76543210 r ppst7 ppst6 ppst5 ppst4 ppst3 ppst2 ppst1 ppst0 w reset 00000000 figure 2-21. port t polarity select register (ppst)
port integration module (s12xspimv1) s12xs family reference manual, rev. 1.10 freescale semiconductor 89 2.3.24 pim reserved register 2.3.25 port t routing register (pttrr) this register configures the re-routing of pwm and tim channels on alternative pins. table 2-21. ppst register field descriptions field description 7-0 ppst port t pull device select ?on?ure pull device polarity on input pin this bit selects a pull-up or a pull-down device if enabled on the associated port input pin. 1 a pull-down device selected 0 a pull-up device selected address 0x0246 access: user read 1 1 read: always reads 0x00 write: unimplemented 76543210 r00000000 w reset 00000000 = unimplemented or reserved figure 2-22. pim reserved register address 0x0247 access: user read 1 1 read: anytime. write: anytime. 76543210 r pttrr7 pttrr6 pttrr5 pttrr4 0 pttrr2 pttrr1 pttrr0 w routing option pwm7 pwm6 pwm5 pwm4 ioc2 ioc1 ioc0 reset 00000000 = unimplemented or reserved figure 2-23. port t routing register (pttrr)
port integration module (s12xspimv1) s12xs family reference manual, rev. 1.10 90 freescale semiconductor table 2-22. pttrr register field descriptions field description 7 pttrr port t peripheral routing this register controls the routing of pwm channel 7. 1 pwm7 routed to pt7 0 pwm7 routed to pp7 6 pttrr port t peripheral routing this register controls the routing of pwm channel 6. 1 pwm6 routed to pt6 0 pwm6 routed to pp6 5 pttrr port t peripheral routing this register controls the routing of pwm channel 5. 1 pwm5 routed to pt5 0 pwm5 routed to pp5 4 pttrr port t peripheral routing this register controls the routing of pwm channel 4. 1 pwm4 routed to pt4 0 pwm4 routed to pp4 2 pttrr port t peripheral routing this register controls the routing of tim channel 2. 1 ioc2 routed to pp2 0 ioc2 routed to pt2 1 pttrr port t peripheral routing this register controls the routing of tim channel 1. 1 ioc1 routed to pp1 0 ioc1 routed to pt1 0 pttrr port t peripheral routing this register controls the routing of tim channel 0. 1 ioc0 routed to pp0 0 ioc0 routed to pt0
port integration module (s12xspimv1) s12xs family reference manual, rev. 1.10 freescale semiconductor 91 2.3.26 port s data register (pts) address 0x0248 access: user read/write 1 1 read: anytime. the data source depends on the data direction value. write: anytime. 76543210 r pts7 pts6 pts5 pts4 pts3 pts2 pts1 pts0 w altern. function ss0 sck0 mosi0 miso0 txd1 rxd1 txd0 rxd0 reset 00000000 figure 2-24. port s data register (pts) table 2-23. pts register field descriptions field description 7 pts port s general purpose input/output data ?ata register, spi0 ss input/output when not used with the alternative function, the associated pin can be used as general purpose i/o. in general purpose output mode the register bit value is driven to the pin. if the associated data direction bit is set to 1, a read returns the value of the port register bit, otherwise the buffered pin input state is read. the spi0 function takes precedence over the general purpose i/o function if enabled. 6 pts port s general purpose input/output data ?ata register, spi0 sck input/output when not used with the alternative function, the associated pin can be used as general purpose i/o. in general purpose output mode the register bit value is driven to the pin. if the associated data direction bit is set to 1, a read returns the value of the port register bit, otherwise the buffered pin input state is read. the spi0 function takes precedence over the general purpose i/o function if enabled. 5 pts port s general purpose input/output data ?ata register, spi0 mosi input/output when not used with the alternative function, the associated pin can be used as general purpose i/o. in general purpose output mode the register bit value is driven to the pin. if the associated data direction bit is set to 1, a read returns the value of the port register bit, otherwise the buffered pin input state is read. the spi0 function takes precedence over the general purpose i/o function if enabled. 4 pts port s general purpose input/output data ?ata register, spi0 miso input/output when not used with the alternative function, the associated pin can be used as general purpose i/o. in general purpose output mode the register bit value is driven to the pin. if the associated data direction bit is set to 1, a read returns the value of the port register bit, otherwise the buffered pin input state is read. the spi0 function takes precedence over the general purpose i/o function if enabled.
port integration module (s12xspimv1) s12xs family reference manual, rev. 1.10 92 freescale semiconductor 2.3.27 port s input register (ptis) 3 pts port s general purpose input/output data ?ata register, sci1 txd output when not used with the alternative function, the associated pin can be used as general purpose i/o. in general purpose output mode the register bit value is driven to the pin. if the associated data direction bit is set to 1, a read returns the value of the port register bit, otherwise the buffered pin input state is read. the sci1 function takes precedence over the general purpose i/o function if enabled. 2 pts port s general purpose input/output data ?ata register, sci1 rxd input when not used with the alternative function, the associated pin can be used as general purpose i/o. in general purpose output mode the register bit value is driven to the pin. if the associated data direction bit is set to 1, a read returns the value of the port register bit, otherwise the buffered pin input state is read. the sci1 function takes precedence over the general purpose i/o function if enabled. 1 pts port s general purpose input/output data ?ata register, sci0 txd output when not used with the alternative function, the associated pin can be used as general purpose i/o. in general purpose output mode the register bit value is driven to the pin. if the associated data direction bit is set to 1, a read returns the value of the port register bit, otherwise the buffered pin input state is read. the sci0 function takes precedence over the general purpose i/o function if enabled. 0 pts port s general purpose input/output data ?ata register, sci0 rxd input when not used with the alternative function, the associated pin can be used as general purpose i/o. in general purpose output mode the register bit value is driven to the pin. if the associated data direction bit is set to 1, a read returns the value of the port register bit, otherwise the buffered pin input state is read. the sci0 function takes precedence over the general purpose i/o function if enabled. address 0x0249 access: user read 1 1 read: anytime. write:never, writes to this register have no effect. 76543210 r ptis7 ptis6 ptis5 ptis4 ptis3 ptis2 ptis1 ptis0 w reset uuuuuuuu = unimplemented or reserved u = unaffected by reset figure 2-25. port s input register (ptis) table 2-23. pts register field descriptions (continued) field description
port integration module (s12xspimv1) s12xs family reference manual, rev. 1.10 freescale semiconductor 93 2.3.28 port s data direction register (ddrs) table 2-24. ptis register field descriptions field description 7-0 ptis port s input data a read always returns the buffered input state of the associated pin. it can be used to detect overload or short circuit conditions on output pins. address 0x0249 access: user read/write 1 1 read: anytime. write: anytime. 76543210 r ddrs7 ddrs6 ddrs5 ddrs4 ddrs3 ddrs2 ddrs1 ddrs0 w reset 00000000 figure 2-26. port s data direction register (ddrs) table 2-25. ddrs register field descriptions field description 7-4 ddrs port s data direction this bit determines whether the associated pin is an input or output. depending on the con?uration of the enabled spi0 the i/o state will be forced to be input or output. in this case the data direction bit will not change. 1 associated pin con?ured as output 0 associated pin con?ured as input 3-2 ddrs port s data direction this bit determines whether the associated pin is an input or output. depending on the con?uration of the enabled sci1 the i/o state will be forced to be input or output. in this case the data direction bit will not change. 1 associated pin con?ured as output 0 associated pin con?ured as input 1-0 ddrs port s data direction this bit determines whether the associated pin is an input or output. depending on the con?uration of the enabled sci0 the i/o state will be forced to be input or output. in this case the data direction bit will not change. 1 associated pin con?ured as output 0 associated pin con?ured as input
port integration module (s12xspimv1) s12xs family reference manual, rev. 1.10 94 freescale semiconductor 2.3.29 port s reduced drive register (rdrs) 2.3.30 port s pull device enable register (pers) address 0x024a access: user read/write 1 1 read: anytime. write: anytime. 76543210 r rdrs7 rdrs6 rdrs5 rdrs4 rdrs3 rdrs2 rdrs1 rdrs0 w reset 00000000 figure 2-27. port s reduced drive register (rdrs) table 2-26. rdrs register field descriptions field description 7-0 rdrs port s reduced drive ?elect reduced drive for output pin this bit con?ures the drive strength of the associated output pin as either full or reduced. if a pin is used as input this bit has no effect. the reduced drive function is independent of which function is being used on a particular pin. 1 reduced drive selected (approx. 1/5 of the full drive strength) 0 full drive strength enabled address 0x024b access: user read/write 1 1 read: anytime. write: anytime. 76543210 r pers7 pers6 pers5 pers4 pers3 pers2 pers1 pers0 w reset 11111111 figure 2-28. port s pull device enable register (pers) table 2-27. pers register field descriptions field description 7-0 pers port s pull device enable ?nable pull device on input pin or wired-or output pin this bit controls whether a pull device on the associated port input pin is active. if a pin is used as output this bit has only effect if used in wired-or mode. the polarity is selected by the related polarity select register bit. 1 pull device enabled 0 pull device disabled
port integration module (s12xspimv1) s12xs family reference manual, rev. 1.10 freescale semiconductor 95 2.3.31 port s polarity select register (ppss) 2.3.32 port s wired-or mode register (woms) address 0x024c access: user read/write 1 1 read: anytime. write: anytime. 76543210 r ppss7 ppss6 ppss5 ppss4 ppss3 ppss2 ppss1 ppss0 w reset 00000000 figure 2-29. port s polarity select register (ppss) table 2-28. ppss register field descriptions field description 7-0 ppss port s pull device select ?on?ure pull device polarity on input pin this bit selects a pull-up or a pull-down device if enabled on the associated port input pin. 1 a pull-down device selected 0 a pull-up device selected address 0x024c access: user read/write 1 1 read: anytime. write: anytime. 76543210 r woms7 woms6 woms5 woms4 woms3 woms2 woms1 woms0 w reset 00000000 figure 2-30. port s wired-or mode register (woms) table 2-29. woms register field descriptions field description 7-0 woms port s wired-or mode ?nable open-drain functionality on output pin this bit con?ures an output pin as wired-or (open-drain) or push-pull independent of the function used on the pins. in wired-or mode a logic ??is driven active low while a logic ??remains undriven. this allows a multipoint connection of several serial modules. the bit has no in?ence on pins used as input. 1 output buffer operates as open-drain output. 0 output buffer operates as push-pull output.
port integration module (s12xspimv1) s12xs family reference manual, rev. 1.10 96 freescale semiconductor 2.3.33 pim reserved register 2.3.34 port m data register (ptm) address 0x024f access: user read 1 1 read: always reads 0x00 write: unimplemented 76543210 r00000000 w reset 00000000 = unimplemented or reserved u = unaffected by reset figure 2-31. pim reserved register address 0x0250 access: user read/write 1 1 read: anytime. the data source depends on the data direction value. write: anytime. 76543210 r ptm7 ptm6 ptm5 ptm4 ptm3 ptm2 ptm1 ptm0 w altern. function (sck0) (mosi0) ( ss0) (miso0) txcan0 rxcan0 (txd1) (rxd1) reset 00000000 figure 2-32. port m data register (ptm) table 2-30. ptm register field descriptions field description 7-6 ptm port m general purpose input/output data ?ata register when not used with the alternative function, the associated pin can be used as general purpose i/o. in general purpose output mode the register bit value is driven to the pin. if the associated data direction bit is set to 1, a read returns the value of the port register bit, otherwise the buffered pin input state is read. 5 ptm port m general purpose input/output data ?ata register, routed spi0 sck input/output when not used with the alternative function, the associated pin can be used as general purpose i/o. in general purpose output mode the register bit value is driven to the pin. if the associated data direction bit is set to 1, a read returns the value of the port register bit, otherwise the buffered pin input state is read. the spi0 function takes precedence over the general purpose i/o function if enabled.
port integration module (s12xspimv1) s12xs family reference manual, rev. 1.10 freescale semiconductor 97 4 ptm port m general purpose input/output data ?ata register, routed spi0 mosi input/output when not used with the alternative function, the associated pin can be used as general purpose i/o. in general purpose output mode the register bit value is driven to the pin. if the associated data direction bit is set to 1, a read returns the value of the port register bit, otherwise the buffered pin input state is read. the spi0 function takes precedence over the general purpose i/o function if enabled. 3 ptm port m general purpose input/output data ?ata register, routed spi0 ss input/output when not used with the alternative function, the associated pin can be used as general purpose i/o. in general purpose output mode the register bit value is driven to the pin. if the associated data direction bit is set to 1, a read returns the value of the port register bit, otherwise the buffered pin input state is read. the spi0 function takes precedence over the general purpose i/o function if enabled. 2 ptm port m general purpose input/output data ?ata register, routed spi0 miso input/output when not used with the alternative function, the associated pin can be used as general purpose i/o. in general purpose output mode the register bit value is driven to the pin. if the associated data direction bit is set to 1, a read returns the value of the port register bit, otherwise the buffered pin input state is read. the spi0 function takes precedence over the general purpose i/o function if enabled. 1 ptm port m general purpose input/output data ?ata register, can0 txcan output, sci1 txd output when not used with the alternative function, the associated pin can be used as general purpose i/o. in general purpose output mode the register bit value is driven to the pin. if the associated data direction bit is set to 1, a read returns the value of the port register bit, otherwise the buffered pin input state is read. the can0 function takes precedence over the general purpose i/o function if enabled. the sci1 function takes precedence over the general purpose i/o function if enabled. 0 ptm port m general purpose input/output data ?ata register, can0 rxcan input, sci1 rxd input when not used with the alternative function, the associated pin can be used as general purpose i/o. in general purpose output mode the register bit value is driven to the pin. if the associated data direction bit is set to 1, a read returns the value of the port register bit, otherwise the buffered pin input state is read. the can0 function takes precedence over the general purpose i/o function if enabled. the sci1 function takes precedence over the general purpose i/o function if enabled. table 2-30. ptm register field descriptions (continued) field description
port integration module (s12xspimv1) s12xs family reference manual, rev. 1.10 98 freescale semiconductor 2.3.35 port m input register (ptim) 2.3.36 port m data direction register (ddrm) address 0x0251 access: user read 1 1 read: anytime. write:never, writes to this register have no effect. 76543210 r ptim7 ptim6 ptim5 ptim4 ptim3 ptim2 ptim1 ptim0 w reset uuuuuuuu = unimplemented or reserved u = unaffected by reset figure 2-33. port m input register (ptim) table 2-31. ptim register field descriptions field description 7-0 ptim port m input data a read always returns the buffered input state of the associated pin. it can be used to detect overload or short circuit conditions on output pins. address 0x0252 access: user read/write 1 1 read: anytime. write: anytime. 76543210 r ddrm7 ddrm6 ddrm5 ddrm4 ddrm3 ddrm2 ddrm1 ddrm0 w reset 00000000 figure 2-34. port m data direction register (ddrm)
port integration module (s12xspimv1) s12xs family reference manual, rev. 1.10 freescale semiconductor 99 2.3.37 port m reduced drive register (rdrm) table 2-32. ddrm register field descriptions field description 7-6 ddrm port m data direction this bit determines whether the associated pin is an input or output. 1 associated pin con?ured as output 0 associated pin con?ured as input 5-2 ddrm port m data direction this bit determines whether the associated pin is an input or output. depending on the con?uration of the enabled spi0 the i/o state will be forced to be input or output. in this case the data direction bit will not change. 1 associated pin con?ured as output 0 associated pin con?ured as input 1 ddrm port m data direction this bit determines whether the associated pin is an input or output. the enabled can0 or sci1 forces the i/o state to be an output. in this case the data direction bit will not change. 1 associated pin con?ured as output 0 associated pin con?ured as input 0 ddrm port m data direction this bit determines whether the associated pin is an input or output. the enabled can0 or sci1 forces the i/o state to be an input. in this case the data direction bit will not change. 1 associated pin con?ured as output 0 associated pin con?ured as input address 0x0253 access: user read/write 1 1 read: anytime. write: anytime. 76543210 r rdrm7 rdrm6 rdrm5 rdrm4 rdrm3 rdrm2 rdrm1 rdrm0 w reset 00000000 figure 2-35. port m reduced drive register (rdrm) table 2-33. rdrm register field descriptions field description 7-0 rdrm port m reduced drive ?elect reduced drive for output pin this bit con?ures the drive strength of the associated output pin as either full or reduced. if a pin is used as input this bit has no effect. the reduced drive function is independent of which function is being used on a particular pin. 1 reduced drive selected (approx. 1/5 of the full drive strength) 0 full drive strength enabled
port integration module (s12xspimv1) s12xs family reference manual, rev. 1.10 100 freescale semiconductor 2.3.38 port m pull device enable register (perm) 2.3.39 port m polarity select register (ppsm) address 0x0254 access: user read/write 1 1 read: anytime. write: anytime. 76543210 r perm7 perm6 perm5 perm4 perm3 perm2 perm1 perm0 w reset 00000000 figure 2-36. port m pull device enable register (perm) table 2-34. perm register field descriptions field description 7-0 perm port m pull device enable ?nable pull device on input pin or wired-or output pin this bit controls whether a pull device on the associated port input pin is active. if a pin is used as output this bit has only effect if used in wired-or mode. the polarity is selected by the related polarity select register bit. 1 pull device enabled 0 pull device disabled address 0x0255 access: user read/write 1 1 read: anytime. write: anytime. 76543210 r ppsm7 ppsm6 ppsm5 ppsm4 ppsm3 ppsm2 ppsm1 ppsm0 w reset 00000000 figure 2-37. port m polarity select register (ppsm) table 2-35. ppsm register field descriptions field description 7-0 ppsm port m pull device select ?on?ure pull device polarity on input pin this bit selects a pull-up or a pull-down device if enabled on the associated port input pin. if can0 is active the selection of a pull-down device on the rxcan input will have no effect. 1 a pull-down device selected 0 a pull-up device selected
port integration module (s12xspimv1) s12xs family reference manual, rev. 1.10 freescale semiconductor 101 2.3.40 port m wired-or mode register (womm) 2.3.41 module routing register (modrr) this register configures the re-routing of sci1 and spi0 on alternative ports. address 0x0256 access: user read/write 1 1 read: anytime. write: anytime. 76543210 r womm7 womm6 womm5 womm4 womm3 womm2 womm1 womm0 w reset 00000000 figure 2-38. port m wired-or mode register (womm) table 2-36. womm register field descriptions field description 7-0 womm port m wired-or mode ?nable open-drain functionality on output pin this bit con?ures an output pin as wired-or (open-drain) or push-pull independent of the function used on the pins. in wired-or mode a logic ??is driven active low while a logic ??remains undriven. this allows a multipoint connection of several serial modules. the bit has no in?ence on pins used as input. 1 output buffer operates as open-drain output. 0 output buffer operates as push-pull output. address 0x0257 access: user read/write 1 1 read: anytime. write: anytime. 76543210 r modrr7 modrr6 0 modrr4 0000 w routing option sci1 sci1 spi0 reset 00000000 = unimplemented or reserved figure 2-39. module routing register (modrr) table 2-37. sci1 routing modrrx related pins 7 6 txd rxd
port integration module (s12xspimv1) s12xs family reference manual, rev. 1.10 102 freescale semiconductor 2.3.42 port p data register (ptp) 0 0 ps3 ps2 0 1 pp2 pp0 1 0 pm1 pm0 1 1 reserved 1 reserved 1 1 defaults to reset value table 2-38. spi0 routing modrrx related pins 4 miso0 mosi0 sck0 ss0 0 ps4 ps5 ps6 ps7 1 pm2 pm4 pm5 pm3 address 0x0258 access: user read/write 1 1 read: anytime. the data source depends on the data direction value. write: anytime. 76543210 r ptp7 ptp6 ptp5 ptp4 ptp3 ptp2 ptp1 ptp0 w altern. function pwm7 pwm6 pwm5 pwm4 pwm3 pwm2 pwm1 pwm0 (ioc2) (ioc1) (ioc0) (txd1) (rxd1) reset 00000000 figure 2-40. port p data register (ptp) table 2-37. sci1 routing modrrx related pins
port integration module (s12xspimv1) s12xs family reference manual, rev. 1.10 freescale semiconductor 103 table 2-39. ptp register field descriptions field description 7 ptp port p general purpose input/output data ?ata register, pwm input/output, pin interrupt input/output when not used with the alternative function, the associated pin can be used as general purpose i/o. in general purpose output mode the register bit value is driven to the pin. if the associated data direction bit is set to 1, a read returns the value of the port register bit, otherwise the buffered pin input state is read. the pwm function takes precedence over the general purpose i/o function if the related channel or the emergency shut-down feature is enabled. pin interrupts can be generated if enabled in input or output mode. 6-3 ptp port p general purpose input/output data ?ata register, pwm output, pin interrupt input/output when not used with the alternative function, the associated pin can be used as general purpose i/o. in general purpose output mode the register bit value is driven to the pin. if the associated data direction bit is set to 1, a read returns the value of the port register bit, otherwise the buffered pin input state is read. the pwm function takes precedence over the general purpose i/o function if the related channel is enabled. pin interrupts can be generated if enabled in input or output mode. 2 ptp port p general purpose input/output data ?ata register, pwm output, routed tim output, routed sci1 txd output, pin interrupt input/output when not used with the alternative function, the associated pin can be used as general purpose i/o. in general purpose output mode the register bit value is driven to the pin. if the associated data direction bit is set to 1, a read returns the value of the port register bit, otherwise the buffered pin input state is read. the pwm function takes precedence over the tim, sci1 and general purpose i/o function if the related channel is enabled. the tim function takes precedence over sci1 and the general purpose i/o function if the related channel is enabled. the sci1 function takes precedence over the general purpose i/o function if enabled. pin interrupts can be generated if enabled in input or output mode.
port integration module (s12xspimv1) s12xs family reference manual, rev. 1.10 104 freescale semiconductor 2.3.43 port p input register (ptip) 1 ptp port p general purpose input/output data ?ata register, pwm output, routed tim output, pin interrupt input/output when not used with the alternative function, the associated pin can be used as general purpose i/o. in general purpose output mode the register bit value is driven to the pin. if the associated data direction bit is set to 1, a read returns the value of the port register bit, otherwise the buffered pin input state is read. the pwm function takes precedence over the tim and general purpose i/o function if the related channel is enabled. the tim function takes precedence over the general purpose i/o function if the related channel is enabled. pin interrupts can be generated if enabled in input or output mode. 0 ptp port p general purpose input/output data ?ata register, pwm output, routed tim output, routed sci1 rxd output, pin interrupt input/output when not used with the alternative function, the associated pin can be used as general purpose i/o. in general purpose output mode the register bit value is driven to the pin. if the associated data direction bit is set to 1, a read returns the value of the port register bit, otherwise the buffered pin input state is read. the pwm function takes precedence over the tim, sci1 and general purpose i/o function if the related channel is enabled. the tim function takes precedence over sci1 and the general purpose i/o function if the related channel is enabled. the sci1 function takes precedence over the general purpose i/o function if enabled. pin interrupts can be generated if enabled in input or output mode. address 0x0259 access: user read 1 1 read: anytime. write:never, writes to this register have no effect. 76543210 r ptip7 ptip6 ptip5 ptip4 ptip3 ptip2 ptip1 ptip0 w reset uuuuuuuu = unimplemented or reserved u = unaffected by reset figure 2-41. port p input register (ptip) table 2-40. ptip register field descriptions field description 7-0 ptip port p input data a read always returns the buffered input state of the associated pin. it can be used to detect overload or short circuit conditions on output pins. table 2-39. ptp register field descriptions (continued) field description
port integration module (s12xspimv1) s12xs family reference manual, rev. 1.10 freescale semiconductor 105 2.3.44 port p data direction register (ddrp) address 0x025a access: user read/write 1 1 read: anytime. write: anytime. 76543210 r ddrp7 ddrp6 ddrp5 ddrp4 ddrp3 ddrp2 ddrp1 ddrp0 w reset 00000000 figure 2-42. port p data direction register (ddrp) table 2-41. ddrp register field descriptions field description 7 ddrp port p data direction this bit determines whether the associated pin is an input or output. the pwm forces the i/o state to be an output for an enabled channel. if the pwm shutdown feature is enabled this pin is forced to be an input. in this case the data direction bit will not change. 1 associated pin con?ured as output 0 associated pin con?ured as input 6-3 ddrp port p data direction this bit determines whether the associated pin is an input or output. the pwm forces the i/o state to be an output for an enabled channel. in this case the data direction bit will not change. 1 associated pin con?ured as output 0 associated pin con?ured as input 2,0 ddrp port p data direction this bit determines whether the associated pin is an input or output. the pwm forces the i/o state to be an output for an enabled channel. else the tim forces the i/o state to be an output for a timer port associated with an enabled output compare. else depending on the con?uration of the enabled sci the i/o state will be forced to be input or output. in this case the data direction bit will not change. 1 associated pin con?ured as output 0 associated pin con?ured as input 1 ddrp port p data direction this bit determines whether the associated pin is an input or output. the pwm forces the i/o state to be an output for an enabled channel. else the tim forces the i/o state to be an output for a timer port associated with an enabled output compare. in this case the data direction bit will not change. 1 associated pin con?ured as output 0 associated pin con?ured as input
port integration module (s12xspimv1) s12xs family reference manual, rev. 1.10 106 freescale semiconductor 2.3.45 port p reduced drive register (rdrp) 2.3.46 port p pull device enable register (perp) address 0x025b access: user read/write 1 1 read: anytime. write: anytime. 76543210 r rdrp7 rdrp6 rdrp5 rdrp4 rdrp3 rdrp2 rdrp1 rdrp0 w reset 00000000 figure 2-43. port p reduced drive register (rdrp) table 2-42. rdrp register field descriptions field description 7-0 rdrp port p reduced drive ?elect reduced drive for output pin this bit con?ures the drive strength of the associated output pin as either full or reduced. if a pin is used as input this bit has no effect. the reduced drive function is independent of which function is being used on a particular pin. 1 reduced drive selected (approx. 1/5 of the full drive strength) 0 full drive strength enabled address 0x025c access: user read/write 1 1 read: anytime. write: anytime. 76543210 r ppsp7 ppsp6 ppsp5 ppsp4 ppsp3 ppsp2 ppsp1 ppsp0 w reset 00000000 figure 2-44. port p pull device enable register (perp) table 2-43. perp register field descriptions field description 7-0 perp port p pull device enable ?nable pull device on input pin this bit controls whether a pull device on the associated port input pin is active. if a pin is used as output this bit has no effect. the polarity is selected by the related polarity select register bit. 1 pull device enabled 0 pull device disabled
port integration module (s12xspimv1) s12xs family reference manual, rev. 1.10 freescale semiconductor 107 2.3.47 port p polarity select register (ppsp) 2.3.48 port p interrupt enable register (piep) read: anytime. address 0x025d access: user read/write 1 1 read: anytime. write: anytime. 76543210 r ppsp7 ppsp6 ppsp5 ppsp4 ppsp3 ppsp2 ppsp1 ppsp0 w reset 00000000 figure 2-45. port p polarity select register (ppsp) table 2-44. ppsp register field descriptions field description 7-0 ppsp port p pull device select ?on?ure pull device and pin interrupt edge polarity on input pin this bit selects a pull-up or a pull-down device if enabled on the associated port input pin. this bit also selects the polarity of the active pin interrupt edge. 1 a pull-down device selected; rising edge selected 0 a pull-up device selected; falling edge selected address 0x025e access: user read/write 1 1 read: anytime. write: anytime. 76543210 r piep7 piep6 piep5 piep4 piep3 piep2 piep1 piep0 w reset 00000000 figure 2-46. port p interrupt enable register (piep) table 2-45. piep register field descriptions field description 7-0 piep port p interrupt enable this bit enables or disables on the edge sensitive pin interrupt on the associated pin. 1 interrupt enabled 0 interrupt disabled (interrupt ?g masked)
port integration module (s12xspimv1) s12xs family reference manual, rev. 1.10 108 freescale semiconductor 2.3.49 port p interrupt flag register (pifp) 2.3.50 port h data register (pth) address 0x025f access: user read/write 1 1 read: anytime. write: anytime. 76543210 r pifp7 pifp6 pifp5 pifp4 pifp3 pifp2 pifp1 pifp0 w reset 00000000 figure 2-47. port p interrupt flag register (pifp) table 2-46. pifp register field descriptions field description 7-0 pifp port p interrupt ?g the ?g bit is set after an active edge was applied to the associated input pin. this can be a rising or a falling edge based on the state of the polarity select register. writing a logic ??to the corresponding bit ?ld clears the ?g. 1 active edge on the associated bit has occurred (an interrupt will occur if the associated enable bit is set) 0 no active edge occurred address 0x0260 access: user read/write 1 1 read: anytime. the data source depends on the data direction value. write: anytime. 76543210 r pth7 pth6 pth5 pth4 pth3 pth2 pth1 pth0 w reset 00000000 figure 2-48. port h data register (pth) table 2-47. pth register field descriptions field description 7-0 pth port h general purpose input/output data ?ata register, pin interrupt input/output the associated pin can be used as general purpose i/o. in general purpose output mode the register bit value is driven to the pin. if the associated data direction bit is set to 1, a read returns the value of the port register bit, otherwise the buffered pin input state is read. pin interrupts can be generated if enabled in input or output mode.
port integration module (s12xspimv1) s12xs family reference manual, rev. 1.10 freescale semiconductor 109 2.3.51 port h input register (ptih) 2.3.52 port h data direction register (ddrh) address 0x0261 access: user read 1 1 read: anytime. write:never, writes to this register have no effect. 76543210 r ptih7 ptih6 ptih5 ptih4 ptih3 ptih2 ptih1 ptih0 w reset uuuuuuuu = unimplemented or reserved u = unaffected by reset figure 2-49. port h input register (ptih) table 2-48. ptih register field descriptions field description 7-0 ptih port h input data a read always returns the buffered input state of the associated pin. it can be used to detect overload or short circuit conditions on output pins. address 0x0262 access: user read/write 1 1 read: anytime. write: anytime. 76543210 r ddrh7 ddrh6 ddrh5 ddrh4 ddrh3 ddrh2 ddrh1 ddrh0 w reset 00000000 figure 2-50. port h data direction register (ddrh) table 2-49. ddrh register field descriptions field description 7-0 ddrh port h data direction this bit determines whether the associated pin is an input or output. 1 associated pin con?ured as output 0 associated pin con?ured as input
port integration module (s12xspimv1) s12xs family reference manual, rev. 1.10 110 freescale semiconductor 2.3.53 port h reduced drive register (rdrh) 2.3.54 port h pull device enable register (perh) address 0x0263 access: user read/write 1 1 read: anytime. write: anytime. 76543210 r rdrh7 rdrh6 rdrh5 rdrh4 rdrh3 rdrh2 rdrh1 rdrh0 w reset 00000000 figure 2-51. port h reduced drive register (rdrh) table 2-50. rdrh register field descriptions field description 7-0 rdrh port h reduced drive ?elect reduced drive for output pin this bit con?ures the drive strength of the associated output pin as either full or reduced. if a pin is used as input this bit has no effect. the reduced drive function is independent of which function is being used on a particular pin. 1 reduced drive selected (approx. 1/5 of the full drive strength) 0 full drive strength enabled address 0x0264 access: user read/write 1 1 read: anytime. write: anytime. 76543210 r perh7 perh6 perh5 perh4 perh3 perh2 perh1 perh0 w reset 00000000 figure 2-52. port h pull device enable register (perh) table 2-51. perh register field descriptions field description 7-0 perh port h pull device enable ?nable pull device on input pin this bit controls whether a pull device on the associated port input pin is active. if a pin is used as output this bit has no effect. the polarity is selected by the related polarity select register bit. 1 pull device enabled 0 pull device disabled
port integration module (s12xspimv1) s12xs family reference manual, rev. 1.10 freescale semiconductor 111 2.3.55 port h polarity select register (ppsh) 2.3.56 port h interrupt enable register (pieh) read: anytime. address 0x025d access: user read/write 1 1 read: anytime. write: anytime. 76543210 r ppsh7 ppsh6 ppsh5 ppsh4 ppsh3 ppsh2 ppsh1 ppsh0 w reset 00000000 figure 2-53. port h polarity select register (ppsh) table 2-52. ppsh register field descriptions field description 7-0 ppsh port h pull device select ?on?ure pull device and pin interrupt edge polarity on input pin this bit selects a pull-up or a pull-down device if enabled on the associated port input pin. this bit also selects the polarity of the active pin interrupt edge. 1 a pull-down device selected; rising edge selected 0 a pull-up device selected; falling edge selected address 0x025e access: user read/write 1 1 read: anytime. write: anytime. 76543210 r pieh7 pieh6 pieh5 pieh4 pieh3 pieh2 pieh1 pieh0 w reset 00000000 figure 2-54. port h interrupt enable register (pieh) table 2-53. pieh register field descriptions field description 7-0 pieh port h interrupt enable this bit enables or disables on the edge sensitive pin interrupt on the associated pin. 1 interrupt enabled 0 interrupt disabled (interrupt ?g masked)
port integration module (s12xspimv1) s12xs family reference manual, rev. 1.10 112 freescale semiconductor 2.3.57 port h interrupt flag register (pifh) 2.3.58 port j data register (ptj) address 0x025f access: user read/write 1 1 read: anytime. write: anytime. 76543210 r pifh7 pifh6 pifh5 pifh4 pifh3 pifh2 pifh1 pifh0 w reset 00000000 figure 2-55. port h interrupt flag register (pifh) table 2-54. pifh register field descriptions field description 7-0 pifh port h interrupt ?g the ?g bit is set after an active edge was applied to the associated input pin. this can be a rising or a falling edge based on the state of the polarity select register. writing a logic ??to the corresponding bit ?ld clears the ?g. 1 active edge on the associated bit has occurred (an interrupt will occur if the associated enable bit is set) 0 no active edge occurred address 0x0268 access: user read/write 1 1 read: anytime. the data source depends on the data direction value. write: anytime. 76543210 r ptj7 ptj6 0000 ptj1 ptj0 w reset 00000000 figure 2-56. port j data register (ptj) table 2-55. ptj register field descriptions field description 7-6, 1-0 ptj port j general purpose input/output data ?ata register, pin interrupt input/output the associated pin can be used as general purpose i/o. in general purpose output mode the register bit value is driven to the pin. if the associated data direction bit is set to 1, a read returns the value of the port register bit, otherwise the buffered pin input state is read. pin interrupts can be generated if enabled in input or output mode.
port integration module (s12xspimv1) s12xs family reference manual, rev. 1.10 freescale semiconductor 113 2.3.59 port j input register (ptij) 2.3.60 port j data direction register (ddrj) address 0x0269 access: user read 1 1 read: anytime. write:never, writes to this register have no effect. 76543210 r ptij7 ptij6 0000 ptij1 ptij0 w reset uuuuuuuu = unimplemented or reserved u = unaffected by reset figure 2-57. port j input register (ptij) table 2-56. ptij register field descriptions field description 7-6, 1-0 ptij port j input data a read always returns the buffered input state of the associated pin. it can be used to detect overload or short circuit conditions on output pins. address 0x026a access: user read/write 1 1 read: anytime. write: anytime. 76543210 r ddrj7 ddrj6 0000 ddrj1 ddrj0 w reset 00000000 figure 2-58. port j data direction register (ddrj) table 2-57. ddrj register field descriptions field description 7-6, 1-0 ddrj port j data direction this bit determines whether the associated pin is an input or output. 1 associated pin con?ured as output 0 associated pin con?ured as input
port integration module (s12xspimv1) s12xs family reference manual, rev. 1.10 114 freescale semiconductor 2.3.61 port j reduced drive register (rdrj) 2.3.62 port j pull device enable register (perj) address 0x026b access: user read/write 1 1 read: anytime. write: anytime. 76543210 r rdrj7 rdrj6 0000 rdrj1 rdrj0 w reset 00000000 figure 2-59. port j reduced drive register (rdrj) table 2-58. rdrj register field descriptions field description 7-6, 1-0 rdrj port j reduced drive ?elect reduced drive for outputs this bit con?ures the drive strength of the associated output pin as either full or reduced. if a pin is used as input this bit has no effect. the reduced drive function is independent of which function is being used on a particular pin. 1 reduced drive selected (approx. 1/5 of the full drive strength). 0 full drive strength enabled. address 0x026c access: user read/write 1 1 read: anytime. write: anytime. 76543210 r perj7 perj6 0000 perj1 perj0 w reset 11111111 figure 2-60. port j pull device enable register (perj) table 2-59. perj register field descriptions field description 7-6, 1-0 perj port j pull device enable ?nable pull device on input pin this bit controls whether a pull device on the associated port input pin is active. if a pin is used as output this bit has no effect. the polarity is selected by the related polarity select register bit. 1 pull device enabled 0 pull device disabled
port integration module (s12xspimv1) s12xs family reference manual, rev. 1.10 freescale semiconductor 115 2.3.63 port j polarity select register (ppsj) 2.3.64 port j interrupt enable register (piej) read: anytime. address 0x026d access: user read/write 1 1 read: anytime. write: anytime. 76543210 r ppsj7 ppsj6 0000 ppsj1 ppsj0 w reset 00000000 figure 2-61. port j polarity select register (ppsj) table 2-60. ppsj register field descriptions field description 7-6, 1-0 ppsj port j pull device select ?on?ure pull device and pin interrupt edge polarity on input pin this bit selects a pull-up or a pull-down device if enabled on the associated port input pin. this bit also selects the polarity of the active pin interrupt edge. 1 a pull-down device selected; rising edge selected 0 a pull-up device selected; falling edge selected address 0x026e access: user read/write 1 1 read: anytime. write: anytime. 76543210 r piej7 piej6 0000 piej1 piej0 w reset 00000000 figure 2-62. port j interrupt enable register (piej) table 2-61. piej register field descriptions field description 7-6, 1-0 piej port j interrupt enable this bit enables or disables on the edge sensitive pin interrupt on the associated pin. 1 interrupt enabled 0 interrupt disabled (interrupt ?g masked)
port integration module (s12xspimv1) s12xs family reference manual, rev. 1.10 116 freescale semiconductor 2.3.65 port j interrupt flag register (pifj) 2.3.66 port ad0 data register 0 (pt0ad0) address 0x026f access: user read/write 1 1 read: anytime. write: anytime. 76543210 r pifj7 pifj6 0000 pifj1 pifj0 w reset 00000000 figure 2-63. port j interrupt flag register (pifj) table 2-62. pifj register field descriptions field description 7-6, 1-0 pifj port j interrupt ?g the ?g bit is set after an active edge was applied to the associated input pin. this can be a rising or a falling edge based on the state of the polarity select register. writing a logic ??to the corresponding bit ?ld clears the ?g. 1 active edge on the associated bit has occurred (an interrupt will occur if the associated enable bit is set) 0 no active edge occurred address 0x0270 access: user read/write 1 1 read: anytime. the data source depends on the data direction value. write: anytime. 76543210 r pt0ad07 pt0ad06 pt0ad05 pt0ad04 pt0ad03 pt0ad02 pt0ad01 pt0ad00 w altern. function an15 an14 an13 an12 an11 an10 an9 an8 reset 00000000 figure 2-64. port ad0 data register 0 (pt0ad0) table 2-63. pt0ad0 register field descriptions field description 7-0 pt0ad0 port ad0 general purpose input/output data ?ata register, atd an analog input when not used with the alternative function, the associated pin can be used as general purpose i/o. in general purpose output mode the register bit value is driven to the pin. if the associated data direction bit is set to 1, a read returns the value of the port register bit, otherwise the buffered pin input state is read.
port integration module (s12xspimv1) s12xs family reference manual, rev. 1.10 freescale semiconductor 117 2.3.67 port ad0 data register 1 (pt1ad0) 2.3.68 port ad0 data direction register 0 (ddr0ad0) address 0x0271 access: user read/write 1 1 read: anytime. the data source depends on the data direction value. write: anytime. 76543210 r pt1ad07 pt1ad06 pt1ad05 pt1ad04 pt1ad03 pt1ad02 pt1ad01 pt1ad00 w altern. function an7 an6 an5 an4 an3 an2 an1 an0 reset 00000000 figure 2-65. port ad0 data register 1 (pt1ad0) table 2-64. pt1ad0 register field descriptions field description 7-0 pt1ad0 port ad0 general purpose input/output data ?ata register, atd an analog input when not used with the alternative function, the associated pin can be used as general purpose i/o. in general purpose output mode the register bit value is driven to the pin. if the associated data direction bit is set to 1, a read returns the value of the port register bit, otherwise the buffered pin input state is read. address 0x0272 access: user read/write 1 1 read: anytime. write: anytime. 76543210 r ddr0ad07 ddr0ad06 ddr0ad05 ddr0ad04 ddr0ad03 ddr0ad02 ddr0ad01 ddr0ad00 w reset 00000000 figure 2-66. port ad0 data direction register 0 (ddr0ad0) table 2-65. ddr0ad0 register field descriptions field description 7-0 ddr0ad0 port ad0 data direction this bit determines whether the associated pin is an input or output. to use the digital input function the atd digital input enable register (atd0dien) has to be set to logic level ?? 1 associated pin con?ured as output 0 associated pin con?ured as input
port integration module (s12xspimv1) s12xs family reference manual, rev. 1.10 118 freescale semiconductor 2.3.69 port ad0 data direction register 1 (ddr1ad0) 2.3.70 port ad0 reduced drive register 0 (rdr0ad0) address 0x0273 access: user read/write 1 1 read: anytime. write: anytime. 76543210 r ddr1ad07 ddr1ad06 ddr1ad05 ddr1ad04 ddr1ad03 ddr1ad02 ddr1ad01 ddr1ad00 w reset 00000000 figure 2-67. port ad0 data direction register 1 (ddr1ad0) table 2-66. ddr1ad0 register field descriptions field description 7-0 ddr1ad0 port ad0 data direction this bit determines whether the associated pin is an input or output. to use the digital input function the atd digital input enable register (atd0dien) has to be set to logic level ?? 1 associated pin con?ured as output 0 associated pin con?ured as input address 0x0274 access: user read/write 1 1 read: anytime. write: anytime. 76543210 r rdr0ad07 rdr0ad06 rdr0ad05 rdr0ad04 rdr0ad03 rdr0ad02 rdr0ad01 rdr0ad00 w reset 00000000 figure 2-68. port ad0 reduced drive register 0 (rdr0ad0) table 2-67. rdr0ad0 register field descriptions field description 7-0 rdr0ad0 port ad0 reduced drive ?elect reduced drive for output pin this bit con?ures the drive strength of the associated output pin as either full or reduced. if a pin is used as input this bit has no effect. the reduced drive function is independent of which function is being used on a particular pin. 1 reduced drive selected (approx. 1/5 of the full drive strength) 0 full drive strength enabled
port integration module (s12xspimv1) s12xs family reference manual, rev. 1.10 freescale semiconductor 119 2.3.71 port ad0 reduced drive register 1 (rdr1ad0) 2.3.72 port ad0 pull up enable register 0 (per0ad0) address 0x0275 access: user read/write 1 1 read: anytime. write: anytime. 76543210 r rdr1ad07 rdr1ad06 rdr1ad05 rdr1ad04 rdr1ad03 rdr1ad02 rdr1ad01 rdr1ad00 w reset 00000000 figure 2-69. port ad0 reduced drive register 1 (rdr1ad0) table 2-68. rdr1ad0 register field descriptions field description 7-0 rdr1ad0 port ad0 reduced drive ?elect reduced drive for output pin this bit con?ures the drive strength of the associated output pin as either full or reduced. if a pin is used as input this bit has no effect. the reduced drive function is independent of which function is being used on a particular pin. 1 reduced drive selected (approx. 1/5 of the full drive strength) 0 full drive strength enabled address 0x0276 access: user read/write 1 1 read: anytime. write: anytime. 76543210 r per0ad07 per0ad06 per0ad05 per0ad04 per0ad03 per0ad02 per0ad01 per0ad00 w reset 00000000 figure 2-70. port ad0 pull device up register 0 (per0ad0) table 2-69. per0ad0 register field descriptions field description 7-0 per0ad0 port ad0 pull device enable ?nable pull-up device on input pin this bit controls whether a pull device on the associated port input pin is active. if a pin is used as output this bit has no effect. the polarity is selected by the related polarity select register bit. 1 pull device enabled 0 pull device disabled
port integration module (s12xspimv1) s12xs family reference manual, rev. 1.10 120 freescale semiconductor 2.3.73 port ad0 pull up enable register 1 (per1ad0) 2.3.74 pim reserved registers 2.4 functional description 2.4.1 general each pin except pe0, pe1, and bkgd can act as general purpose i/o. in addition each pin can act as an output or input of a peripheral module. address 0x0277 access: user read/write 1 1 read: anytime. write: anytime. 76543210 r per1ad07 per1ad06 per1ad05 per1ad04 per1ad03 per1ad02 per1ad01 per1ad00 w reset 00000000 figure 2-71. port ad0 pull up enable register 1 (per1ad0) table 2-70. per1ad0 register field descriptions field description 7-0 per1ad0 port ad0 pull device enable ?nable pull-up device on input pin this bit controls whether a pull device on the associated port input pin is active. if a pin is used as output this bit has no effect. the polarity is selected by the related polarity select register bit. 1 pull device enabled 0 pull device disabled address 0x0278-0x27f access: user read 1 1 read: always reads 0x00 write: unimplemented 76543210 r00000000 w reset 00000000 = unimplemented or reserved u = unaffected by reset figure 2-72. pim reserved registers
port integration module (s12xspimv1) s12xs family reference manual, rev. 1.10 freescale semiconductor 121 2.4.2 registers a set of con?uration registers is common to all ports with exception of the atd port ( table 2-71 ). all registers can be written at any time, however a speci? con?uration might not become active. for example selecting a pull-up device: this device does not become active while the port is used as a push-pull output. 2.4.2.1 data register (portx, ptx) this register holds the value driven out to the pin if the pin is used as a general purpose i/o. writing to this register has only an effect on the pin if the pin is used as general purpose output. when reading this address, the buffered state of the pin is returned if the associated data direction register bit is set to ?? if the data direction register bits are set to logic level ?? the contents of the data register is returned. this is independent of any other con?uration ( figure 2-73 ). 2.4.2.2 input register (ptix) this is a read-only register and always returns the buffered state of the pin ( figure 2-73 ). 2.4.2.3 data direction register (ddrx) this register de?es whether the pin is used as a input or an output. if a peripheral module controls the pin the contents of the data direction register is ignored ( figure 2-73 ). independent of the pin usage with a peripheral module this register determines the source of data when reading the associated data register address ( 2.4.2.1/2-121 ). table 2-71. register availability per port 1 1 each cell represents one register with individual con?uration bits port data input data direction reduced drive pull enable polarity select wired- or mode interrupt enable interrupt flag routing ayes-yesyesyes----- byes-yes ----- eyes-yes ----- kyes-yes ----- t yes yes yes yes yes yes - - - yes s yes yes yes yes yes yes yes - - - m yes yes yes yes yes yes yes - - yes p yes yes yes yes yes yes - yes yes - h yes yes yes yes yes yes - yes yes - j yes yes yes yes yes yes - yes yes - adyes-yesyesyes-----
port integration module (s12xspimv1) s12xs family reference manual, rev. 1.10 122 freescale semiconductor note due to internal synchronization circuits, it can take up to 2 bus clock cycles until the correct value is read on port data or port input registers, when changing the data direction register. figure 2-73. illustration of i/o pin functionality 2.4.2.4 reduced drive register (rdrx) if the pin is used as an output this register allows the con?uration of the drive strength independent of the use with a peripheral module. 2.4.2.5 pull device enable register (perx) this register turns on a pull-up or pull-down device on the related pins determined by the associated polarity select register ( 2.4.2.5/2-122 ). the pull device becomes active only if the pin is used as an input or as a wired-or output. some peripheral modules only allow certain con?urations of pull devices to become active. refer to the respective bit descriptions. 2.4.2.6 polarity select register (ppsx) this register selects either a pull-up or pull-down device if enabled. it only becomes active if the pin is used as an input. a pull-up device can be activated if the pin is used as a wired-or output. pt ddr output enable module enable 1 0 1 1 0 0 pin pti data out module
port integration module (s12xspimv1) s12xs family reference manual, rev. 1.10 freescale semiconductor 123 2.4.2.7 wired-or mode register (womx) if the pin is used as an output this register turns off the active high drive. this allows wired-or type connections of outputs. 2.4.2.8 interrupt enable register (piex) if the pin is used as an interrupt input this register serves as a mask to the interrupt ?g to enable/disable the interrupt. 2.4.2.9 interrupt ?g register (pifx) if the pin is used as an interrupt input this register holds the interrupt ?g after a valid pin event. 2.4.2.10 module routing registers (modrr, pttrr) these registers allow software re-con?uration of the pinouts of the different package options for speci? peripherals: modrr supports the re-routing of the sci1 and spi0 pins to alternative ports pttrr supports the re-routing of the pwm and tim channels to alternative ports 2.4.3 pins and ports note please refer to the device pinout section to determine the pin availability in the different package options. 2.4.3.1 bkgd pin the bkgd pin is associated with the bdm module. during reset, the bkgd pin is used as modc input. 2.4.3.2 port a, b port a pins pa[7:0] and port b pins pb[7:0] can be used for general-purpose i/o. 2.4.3.3 port e port e is associated with the free-running clock outputs eclk, eclkx2 and interrupt inputs irq and xirq. port e pins pe[7:2] can be used for either general-purpose i/o or with the alternative functions. port e pin pe[7] an be used for either general-purpose i/o or as the free-running clock eclkx2 output running at the core clock rate. port e pin pe[4] an be used for either general-purpose i/o or as the free-running clock eclk output running at the bus clock rate or at the programmed divided clock rate.
port integration module (s12xspimv1) s12xs family reference manual, rev. 1.10 124 freescale semiconductor port e pin pe[1] can be used for either general-purpose input or as the level- or falling edge-sensitive irq interrupt input. irq will be enabled by setting the irqen con?uration bit ( 2.3.14/2-83 ) and clearing the i-bit in the cpu condition code register. it is inhibited at reset so this pin is initially con?ured as a simple input with a pull-up. port e pin pe[0] can be used for either general-purpose input or as the level-sensitive xirq interrupt input. xirq can be enabled by clearing the x-bit in the cpu condition code register. it is inhibited at reset so this pin is initially con?ured as a high-impedance input with a pull-up. 2.4.3.4 port k port k pins pk[7,5:0] can be used for general-purpose i/o. 2.4.3.5 port t this port is associated with tim and pwm. port t pins pt[7:4] can be used for either general-purpose i/o, or with the pwm or with the channels of the standard timer subsystem. port t pins pt[3:0] can be used for either general-purpose i/o, or with the channels of the standard timer subsystem. the tim pins ioc2-0 can be re-routed. 2.4.3.6 port s this port is associated with spi0, sci0 and sci1. port s pins ps[7:4] can be used either for general-purpose i/o, or with the spi0 subsystem. port s pins ps[3:2] can be used either for general-purpose i/o, or with the sci1 subsystem. port s pins ps[1:0] can be used either for general-purpose i/o, or with the sci0 subsystem. the spi0 and sci1 pins can be re-routed. 2.4.3.7 port m this port is associated with can0 and sci1. port m pins pm[7:6] can be used for either general purpose i/o. port m pins pm[1:0] can be used for either general purpose i/o, or with the can0 or with the sci1 subsystem. port m pins pm[5:2] can be used for general purpose i/o. 2.4.3.8 port p this port is associated with the pwm, tim and sci1.
port integration module (s12xspimv1) s12xs family reference manual, rev. 1.10 freescale semiconductor 125 port p pins pp[7:3] can be used for either general purpose i/o with pin interrupt capability, or with the pwm or with the channels of the standard timer.subsystem. port p pins pp[2,0] can be used for either general purpose i/o, or with the pwm or with the tim or with the sci1 subsystem. port p pin pp[1] can be used for either general purpose i/o, or with the pwm or with the tim subsystem. 2.4.3.9 port h port h pins ph[7:0] can be used for general purpose i/o with pin interrupt capability. 2.4.3.10 port j port j pins pj[7,6,1,0] can be used for general purpose i/o with pin-interrupt capability. 2.4.3.11 port ad this port is associated with the atd. port ad pins pad[15:0] can be used for either general purpose i/o, or with the atd0 subsystem. 2.4.4 pin interrupts ports p, h and j offer pin interrupt capability. the interrupt enable as well as the sensitivity to rising or falling edges can be individually con?ured on a per-pin basis. all bits/pins in a port share the same interrupt vector. interrupts can be used with the pins con?ured as inputs or outputs. an interrupt is generated when a bit in the port interrupt ?g register and its corresponding port interrupt enable bit are both set. the pin interrupt feature is also capable to wake up the cpu when it is in stop or wait mode. a digital ?ter on each pin prevents pulses ( figure 2-75 ) shorter than a speci?d time from generating an interrupt. the minimum time varies over process conditions, temperature and voltage ( figure 2-74 and table 2-72 ). figure 2-74. interrupt glitch filter on port p, h and j (pps=0) glitch, ?tered out, no interrupt ?g set valid pulse, interrupt ?g set t pign t pval uncertain
port integration module (s12xspimv1) s12xs family reference manual, rev. 1.10 126 freescale semiconductor table 2-72. pulse detection criteria figure 2-75. pulse illustration a valid edge on an input is detected if 4 consecutive samples of a passive level are followed by 4 consecutive samples of an active level directly or indirectly. the ?ters are continuously clocked by the bus clock in run and wait mode. in stop mode the clock is generated by an rc-oscillator in the port integration module. to maximize current saving the rc oscillator runs only if the following condition is true on any pin individually: sample count <= 4 and interrupt enabled (pie=1) and interrupt ?g not set (pif=0). 2.5 initialization information 2.5.1 port data and data direction register writes it is not recommended to write portx/ptx and ddrx in a word access. when changing the register pins from inputs to outputs, the data may have extra transitions during the write access. initialize the port data register before enabling the outputs. pulse mode stop stop 1 1 these values include the spread of the oscillator frequency over tempera- ture, voltage and process. unit ignored t pulse 3 bus clocks t pulse t pign uncertain 3 < t pulse < 4 bus clocks t pign < t pulse < t pval valid t pulse 4 bus clocks t pulse t pval t pulse
s12xs family reference manual, rev. 1.10 freescale semiconductor 127 chapter 3 memory mapping control (s12xmmcv4) revision history 3.1 introduction this section describes the functionality of the module mapping control (mmc) sub-block of the s12x platform. the block diagram of the mmc is shown in figure 3-1 . the mmc module controls the multi-master priority accesses, the selection of internal resources . internal buses, including internal memories and peripherals, are controlled in this module. the local address space for each master is translated to a global memory space. rev. no. (item no.) date (submitted by) sections affected substantial change(s) v04.08 04-may-07 - clarifying rpage usage for less than 12kb ramsize. - some cleanups v04.09 01-feb-08 - minor changes v04.10 17-feb-09 - minor changes
memory mapping control (s12xmmcv4) s12xs family reference manual, rev. 1.10 128 freescale semiconductor 3.1.1 terminology 3.1.2 features the main features of this block are: paging capability to support a global 8mb memory address space bus arbitration between the masters cpu, bdm simultaneous accesses to different resources 1 (internal, and peripherals) (see figure 3-1 ) resolution of target bus access collision mcu operation mode control mcu security control separate memory map schemes for each master cpu, bdm rom control bits to enable the on-chip flash or rom selection generation of system reset when cpu accesses an unimplemented address (i.e., an address which does not belong to any of the on-chip modules) in single-chip modes table 3-1. acronyms and abbreviations logic level ? voltage that corresponds to boolean true state logic level ? voltage that corresponds to boolean false state 0x represents hexadecimal number x represents logic level don? care byte 8-bit data word 16-bit data local address based on the 64kb memory space (16-bit address) global address based on the 8mb memory space (23-bit address) aligned address address on even boundary mis-aligned address address on odd boundary bus clock system clock. refer to crg block guide. single-chip modes normal single-chip mode special single-chip mode normal modes normal single-chip mode special modes special single-chip mode ns normal single-chip mode ss special single-chip mode unimplemented areas areas which are accessible by the pages (rpage,ppage,epage) and not implemented prr port replacement registers pru port replacement unit located on the emulator side mcu microcontroller unit nvm non-volatile memory; flash, data flash or rom ifr information row sector located on the top of nvm. for test purposes. 1. resources are also called targets.
memory mapping control (s12xmmcv4) s12xs family reference manual, rev. 1.10 freescale semiconductor 129 3.1.3 s12x memory mapping the s12x architecture implements a number of memory mapping schemes including a cpu 8mb global map, de?ed using a global page (gpage) register and dedicated 23-bit address load/store instructions. a bdm 8mb global map, de?ed using a global page (bdmgpr) register and dedicated 23-bit address load/store instructions. a (cpu or bdm) 64kb local map, de?ed using speci? resource page (rpage, epage and ppage) registers and the default instruction set. the 64kb visible at any instant can be considered as the local map accessed by the 16-bit (cpu or bdm) address. the mmc module performs translation of the different memory mapping schemes to the speci? global (physical) memory implementation. 3.1.4 modes of operation this subsection lists and brie? describes all operating modes supported by the mmc. 3.1.4.1 power saving modes run mode mmc is functional during normal run mode. wait mode mmc is functional during wait mode. stop mode mmc is inactive during stop mode. 3.1.4.2 functional modes single chip modes in normal and special single chip mode the internal memory is used. 3.1.5 block diagram figure 3-1 shows a block diagram of the mmc.
memory mapping control (s12xmmcv4) s12xs family reference manual, rev. 1.10 130 freescale semiconductor figure 3-1. mmc block diagram 3.2 external signal description the user is advised to refer to the soc guide for port con?uration and location of external bus signals. some pins may not be bonded out in all implementations. table 3-2 outlines the pin names and functions. it also provides a brief description of their operation. table 3-2. external input signals associated with the mmc signal i/o description availability modc i mode input latched after reset (active low) cpu bdm target bus controller dbg mmc address decoder & priority peripherals pgmflash data flash ram
memory mapping control (s12xmmcv4) s12xs family reference manual, rev. 1.10 freescale semiconductor 131 3.3 memory map and registers 3.3.1 module memory map a summary of the registers associated with the mmc block is shown in figure 3-2 . detailed descriptions of the registers and bits are given in the subsections that follow. 3.3.2 register descriptions address register name bit 7 6 5 4 3 2 1 bit 0 0x000a reserved r 0 0 0 0 0 0 0 0 w 0x000b mode r modc 0000000 w 0x0010 gpage r 0 gp6 gp5 gp4 gp3 gp2 gp1 gp0 w 0x0011 direct r dp15 dp14 dp13 dp12 dp11 dp10 dp9 dp8 w 0x0012 reserved r 0 0 0 0 0 0 0 0 w 0x0013 mmcctl1 r mgramon 0 dfifron pgmifron 0000 w 0x0014 reserved r 0 0 0 0 0 0 0 0 w 0x0015 ppage r pix7 pix6 pix5 pix4 pix3 pix2 pix1 pix0 w 0x0016 rpage r rp7 rp6 rp5 rp4 rp3 rp2 rp1 rp0 w 0x0017 epage r ep7 ep6 ep5 ep4 ep3 ep2 ep1 ep0 w = unimplemented or reserved figure 3-2. mmc register summary
memory mapping control (s12xmmcv4) s12xs family reference manual, rev. 1.10 132 freescale semiconductor 3.3.2.1 mode register (mode) read: anytime. write: only if a transition is allowed (see figure 3-5 ). the mode bits of the mode register are used to establish the mcu operating mode. figure 3-4. figure 3-5. mode transition diagram when mcu is unsecured address: 0x000b prr 76543210 r modc 0000000 w reset modc 1 0000000 1. external signal (see table 3-2 ). = unimplemented or reserved figure 3-3. mode register (mode) table 3-3. mode field descriptions field description 7 modc mode select bit ?this bit controls the current operating mode during reset high (inactive). the external mode pin modc determines the operating mode during reset low (active). the state of the pin is latched into the respective register bit after the reset signal goes inactive (see figure 3-3 ). write restrictions exist to disallow transitions between certain modes. figure 3-5 illustrates all allowed mode changes. attempting non authorized transitions will not change the mode bits, but it will block further writes to these register bits except in special modes. write accesses to the mode register are blocked when the device is secured. normal single-chip 1 special single-chip 0 reset (ss) 0 reset 1 (ns) reset transition done by external pins (modc) transition done by write access to the mode register 1 state state state
memory mapping control (s12xmmcv4) s12xs family reference manual, rev. 1.10 freescale semiconductor 133 3.3.2.2 global page index register (gpage) read: anytime write: anytime the global page index register is used to construct a 23 bit address in the global map format. it is only used when the cpu is executing a global instruction (gldaa, gldab, gldd, glds, gldx, gldy,gstaa, gstab, gstd, gsts, gstx, gsty) (see cpu block guide). the generated global address is the result of concatenation of the cpu local address [15:0] with the gpage register [22:16] (see figure 3-7 ). figure 3-7. gpage address mapping example 3-1. this example demonstrates usage of the gpage register ldx #0x5000 ;set gpage offset to the value of 0x5000 movb #0x14, gpage ;initialize gpage register with the value of 0x14 gldaa x ;load accu a from the global address 0x14_5000 address: 0x0010 76543210 r0 gp6 gp5 gp4 gp3 gp2 gp1 gp0 w reset 00000000 = unimplemented or reserved figure 3-6. global page index register (gpage) table 3-4. gpage field descriptions field description 6? gp[6:0] global page index bits 6? these page index bits are used to select which of the 128 64kb pages is to be accessed. bit16 bit 0 bit15 bit22 cpu address [15:0] gpage register [6:0] global address [22:0]
memory mapping control (s12xmmcv4) s12xs family reference manual, rev. 1.10 134 freescale semiconductor 3.3.2.3 direct page register (direct) read: anytime write: anytime in special modes, one time only in other modes. this register determines the position of the 256b direct page within the memory map.it is valid for both global and local mapping scheme. figure 3-9. direct address mapping bits [22:16] of the global address will be formed by the gpage[6:0] bits in case the cpu executes a global instruction in direct addressing mode or by the appropriate local address to the global address expansion (refer to section 3.4.2.1.1, ?xpansion of the local address map ). example 3-2. this example demonstrates usage of the direct addressing mode movb #0x80,direct ;set direct register to 0x80. write once only. ;global data accesses to the range 0xxx_80xx can be direct. ;logical data accesses to the range 0x80xx are direct. ldy <00 ;load the y index register from 0x8000 (direct access). ;< operator forces direct access on some assemblers but in ;many cases assemblers are ?irect page aware?and can ;automatically select direct mode. address: 0x0011 76543210 r dp15 dp14 dp13 dp12 dp11 dp10 dp9 dp8 w reset 00000000 figure 3-8. direct register (direct) table 3-5. direct field descriptions field description 7? dp[15:8] direct page index bits 15? ?these bits are used by the cpu when performing accesses using the direct addressing mode. the bits from this register form bits [15:8] of the address (see figure 3-9 ). bit15 bit0 bit7 bit22 cpu address [15:0] global address [22:0] bit8 bit16 dp [15:8]
memory mapping control (s12xmmcv4) s12xs family reference manual, rev. 1.10 freescale semiconductor 135 3.3.2.4 mmc control register (mmcctl1) read: anytime. . write: refer to each bit description. 3.3.2.5 program page index register (ppage) read: anytime address: 0x0013 prr 76543210 r mgramon 0 dfifron pgmifron 0000 w reset 00000000 = unimplemented or reserved figure 3-10. mmc control register (mmcctl1) table 3-6. mmcctl1 field descriptions field description 7 mgramon flash memory controller scratch ram visible in the global memory map write: anytime this bit is used to made the flash memory controller scratch ram visible in the global memory map. 0 not visible in the global memory map. 1 visible in the global memory map. 5 dfifron data flash information row (ifr) visible in the global memory map write: anytime this bit is used to made the ifr sector of the data flash visible in the global memory map. 0 not visible in the global memory map. 1 visible in the global memory map. 4 pgmifron program flash information row (ifr) visible in the global memory map write: anytime this bit is used to map the ifr sector of the program flash to address range 0x40_000-0x40_3fff of the global memory map. 0 not visible in the global memory map. 1 visible in the global memory map. address: 0x0015 76543210 r pix7 pix6 pix5 pix4 pix3 pix2 pix1 pix0 w reset 11111110 figure 3-11. program page index register (ppage)
memory mapping control (s12xmmcv4) s12xs family reference manual, rev. 1.10 136 freescale semiconductor write: anytime these eight index bits are used to page 16kb blocks into the flash page window located in the local (cpu or bdm) memory map from address 0x8000 to address 0xbfff (see figure 3-12 ). this supports accessing up to 4mb of flash (in the global map) within the 64kb local map. the ppage register is effectively used to construct paged flash addresses in the local map format. the cpu has special access to read and write this register directly during execution of call and rtc instructions.. figure 3-12. ppage address mapping note writes to this register using the special access of the call and rtc instructions will be complete before the end of the instruction execution. the reset value of 0xfe ensures that there is linear flash space available between addresses 0x4000 and 0xffff out of reset. the ?ed 16k page from 0xc000-0xffff is the page number 0xff. 3.3.2.6 ram page index register (rpage) table 3-7. ppage field descriptions field description 7? pix[7:0] program page index bits 7? ?these page index bits are used to select which of the 256 flash or rom array pages is to be accessed in the program page window. address: 0x0016 76543210 r rp7 rp6 rp5 rp4 rp3 rp2 rp1 rp0 w reset 11111101 figure 3-13. ram page index register (rpage) bit14 bit0 1 address [13:0] ppage register [7:0] global address [22:0] bit13 bit21 address: cpu local address or bdm local address
memory mapping control (s12xmmcv4) s12xs family reference manual, rev. 1.10 freescale semiconductor 137 read: anytime write: anytime these eight index bits are used to page 4kb blocks into the ram page window located in the local (cpu or bdm) memory map from address 0x1000 to address 0x1fff (see figure 3-14 ) . this supports accessing up to 1022kb of ram (in the global map) within the 64kb local map. the ram page index register is effectively used to construct paged ram addresses in the local map format . figure 3-14. rpage address mapping note because ram page 0 has the same global address as the register space, it is possible to write to registers through the ram space when rpage = 0x00. the reset value of 0xfd ensures that there is a linear ram space available between addresses 0x1000 and 0x3fff out of reset. the ?ed 4k page from 0x2000?x2fff of ram is equivalent to page 254 (page number 0xfe). the ?ed 4k page from 0x3000?x3fff of ram is equivalent to page 255 (page number 0xff). note the page 0xfd (reset value) contains unimplemented area in the range not occupied by ram if ramsize is less than 12kb (refer to section 3.4.2.3, ?mplemented memory map ). table 3-8. rpage field descriptions field description 7? rp[7:0] ram page index bits 7? these page index bits are used to select which of the 256 ram array pages is to be accessed in the ram page window. bit18 bit0 bit11 0 address [11:0] rpage register [7:0] global address [22:0] bit12 bit19 0 address: cpu local address or bdm local address 0
memory mapping control (s12xmmcv4) s12xs family reference manual, rev. 1.10 138 freescale semiconductor the two xed 4kb pages (0xfe, 0xff) contain unimplemented area in the range not occupied by ram if ramsize is less than 8kb (refer to section 3.4.2.3, ?mplemented memory map ).
memory mapping control (s12xmmcv4) s12xs family reference manual, rev. 1.10 freescale semiconductor 139 3.3.2.7 data flash page index register (epage) read: anytime write: anytime these eight index bits are used to page 1kb blocks into the data flash page window located in the local (cpu or bdm) memory map from address 0x0800 to address 0x0bff (see figure 3-16 ). this supports accessing up to 256kb of data flash (in the global map) within the 64kb local map. the data flash page index register is effectively used to construct paged data flash addresses in the local map format. figure 3-16. epage address mapping the reset value of 0xfe ensures that there is a linear data flash space available between addresses 0x0800 and 0x0fff out of reset. the ?ed 1k page 0x0c00?x0fff of data flash is equivalent to page 255 (page number 0xff). address: 0x0017 76543210 r ep7 ep6 ep5 ep4 ep3 ep2 ep1 ep0 w reset 11111110 figure 3-15. data flash page index register (epage) table 3-9. epage field descriptions field description 7? ep[7:0] data flash page index bits 7? ?these page index bits are used to select which of the 256 data flash array pages is to be accessed in the data flash page window. bit16 bit0 bit9 address [9:0] epage register [7:0] global address [22:0] bit10 bit17 0 0 1 00 address: cpu local address or bdm local address
memory mapping control (s12xmmcv4) s12xs family reference manual, rev. 1.10 140 freescale semiconductor 3.4 functional description the mmc block performs several basic functions of the s12x sub-system operation: mcu operation modes, priority control, address mapping, select signal generation and access limitations for the system. each aspect is described in the following subsections. 3.4.1 mcu operating mode normal single-chip mode there is no external bus in this mode. the mcu program is executed from the internal memory and no external accesses are allowed. special single-chip mode this mode is generally used for debugging single-chip operation, boot-strapping or security related operations. the active background debug mode is in control of the cpu code execution and the bdm ?mware is waiting for serial commands sent through the bkgd pin. there is no external bus in this mode. 3.4.2 memory map scheme 3.4.2.1 cpu and bdm memory map scheme the bdm ?mware lookup tables and bdm register memory locations share addresses with other modules; however they are not visible in the global memory map during users code execution. the bdm memory resources are enabled only during the read_bd and write_bd access cycles to distinguish between accesses to the bdm memory area and accesses to the other modules. (refer to bdm block guide for further details). when the mcu enters active bdm mode, the bdm ?mware lookup tables and the bdm registers become visible in the local memory map in the range 0xff00-0xffff (global address 0x7f_ff00 - 0x7f_ffff) and the cpu begins execution of ?mware commands or the bdm begins execution of hardware commands. the resources which share memory space with the bdm module will not be visible in the global memory map during active bdm mode. please note that after the mcu enters active bdm mode the bdm ?mware lookup tables and the bdm registers will also be visible between addresses 0xbf00 and 0xbfff if the ppage register contains value of 0xff.
memory mapping control (s12xmmcv4) s12xs family reference manual, rev. 1.10 freescale semiconductor 141 figure 3-17. expansion of the local address map 0x7f_ffff 0x00_0000 0x14_0000 0x10_0000 0x00_0800 epage rpage ppage cpu and bdm local memory map global memory map 0xffff reset vectors 0xc000 0x8000 unpaged 0x4000 0x1000 0x0000 16kb flash window 0x0c00 0x2000 0x0800 8kb ram 4kb ram window reserved 2kb registers 1kb data flash window 16kb flash unpaged 16kb flash 2kb registers 2kb ram 253*4kb paged ram 256*1kb paged data flash 253 *16kb paged flash 16kb flash (ppage 0xfd) 8kb ram 16kb flash (ppage 0xfe) 16kb flash (ppage 0xff) 0x00_1000 0x0f_e000 0x13_fc00 0x40_0000 0x7f_4000 0x7f_8000 0x7f_c000 1m minus 2kb 256kb 4mb 2.75mb unimplemented space
memory mapping control (s12xmmcv4) s12xs family reference manual, rev. 1.10 142 freescale semiconductor 3.4.2.1.1 expansion of the local address map expansion of the cpu local address map the program page index register in mmc allows accessing up to 4mb of flash or rom in the global memory map by using the eight page index bits to page 256 16kb blocks into the program page window located from address 0x8000 to address 0xbfff in the local cpu memory map. the page value for the program page window is stored in the ppage register. the value of the ppage register can be read or written by normal memory accesses as well as by the call and rtc instructions (see section 3.5.1, ?all and rtc instructions ). control registers, vector space and parts of the on-chip memories are located in unpaged portions of the 64kb local cpu address space. the starting address of an interrupt service routine must be located in unpaged memory unless the user is certain that the ppage register will be set to the appropriate value when the service routine is called. however an interrupt service routine can call other routines that are in paged memory. the upper 16kb block of the local cpu memory space (0xc000?xffff) is unpaged. it is recommended that all reset and interrupt vectors point to locations in this area or to the other unpaged sections of the local cpu memory map. the ram page index register allows accessing up to 1mb minus 2kb of ram in the global memory map by using the eight rpage index bits to page 4kb blocks into the ram page window located in the local cpu memory space from address 0x1000 to address 0x1fff. the data flash page index register epage allows accessing up to 256kb of data flash in the system by using the eight epage index bits to page 1kb blocks into the data flash page window located in the local cpu memory space from address 0x0800 to address 0x0bff.
memory mapping control (s12xmmcv4) s12xs family reference manual, rev. 1.10 freescale semiconductor 143 expansion of the bdm local address map ppage, rpage, and epage registers are also used for the expansion of the bdm local address to the global address. these registers can be read and written by the bdm. the bdm expansion scheme is the same as the cpu expansion scheme. 3.4.2.2 global addresses based on the global page cpu global addresses based on the global page the seven global page index bits allow access to the full 8mb address map that can be accessed with 23 address bits. this provides an alternative way to access all of the various pages of flash, ram and data flash. the gpage register is used only when the cpu is executing a global instruction (see section 3.3.2.2, ?lobal page index register (gpage) ). the generated global address is the result of concatenation of the cpu local address [15:0] with the gpage register [22:16] (see figure 3-7 ). bdm global addresses based on the global page the seven bdmgpr global page index bits allow access to the full 8mb address map that can be accessed with 23 address bits. this provides an alternative way to access all of the various pages of flash, ram and data flash. the bdm global page index register (bdmgpr) is used only in the case the cpu is executing a ?mware command which uses a global instruction (like gldd, gstd) or by a bdm hardware command (like write_w, write_byte, read_w, read_byte). see the bdm block guide for further details. the generated global address is a result of concatenation of the bdm local address with the bdmgpr register [22:16] in the case of a hardware command or concatenation of the cpu local address and the bdmgpr register [22:16] in the case of a ?mware command (see figure 3-18 ).
memory mapping control (s12xmmcv4) s12xs family reference manual, rev. 1.10 144 freescale semiconductor figure 3-18. bdmgpr address mapping 3.4.2.3 implemented memory map the global memory spaces reserved for the internal resources (ram, data flash, and flash) are not determined by the mmc module. size of the individual internal resources are however xed in the design of the device cannot be changed by the user. please refer to the soc guide for further details. figure 3-19 and table 3-10 show the memory spaces occupied by the on-chip resources. please note that the memory spaces have ?ed top addresses. table 3-10. global implemented memory space internal resource $address ram ram_low = 0x10_0000 minus ramsize 1 1 ramsize is the hexadecimal value of ram size in bytes data flash df_high = 0x10_0000 plus dflashsize 2 2 dflashsize is the hexadecimal value of dflash size in bytes flash flash_low = 0x80_0000 minus flashsize 3 3 flashsize is the hexadecimal value of flash size in bytes bit16 bit0 bit15 bit22 bdm local address bdmgpr register [6:0] global address [22:0] bit16 bit0 bit15 bit22 cpu local address bdmgpr register [6:0] global address [22:0] bdm hardware command bdm firmware command
memory mapping control (s12xmmcv4) s12xs family reference manual, rev. 1.10 freescale semiconductor 145 in single-chip modes accesses by the cpu (except for ?mware commands) to any of the unimplemented areas (see figure 3-19 ) will result in an illegal access reset (system reset) in case of no mpu error. bdm accesses to the unimplemented areas are allowed but the data will be unde?ed.no misaligned word access from the bdm module will occur; these accesses are blocked in the bdm module (refer to bdm block guide). misaligned word access to the last location of ram is performed but the data will be unde?ed. misaligned word access to the last location of any global page (64kb) by any global instruction, is performed by accessing the last byte of the page and the ?st byte of the same page, considering the above mentioned misaligned access cases.
memory mapping control (s12xmmcv4) s12xs family reference manual, rev. 1.10 146 freescale semiconductor figure 3-19. s12x cpu & bdm global address mapping 0x7f_ffff 0x00_0000 0x13_ffff 0x0f_ffff data flash ram 0x00_07ff epage rpage ppage 0x3f_ffff cpu and bdm local memory map global memory map flashsize ramsize 0xffff reset vectors 0xc000 0x8000 unpaged 0x4000 0x1000 0x0000 16k flash window 0x0c00 0x2000 0x0800 8k ram 4k ram window reserved 2k registers 1k data flash window 16k flash unpaged 16k flash 2k registers unimplemented ram ram_low flash flash_low unimplemented flash unimplemented space df_high data flash resources dflashsize
memory mapping control (s12xmmcv4) s12xs family reference manual, rev. 1.10 freescale semiconductor 147 3.4.3 chip bus control the mmc controls the address buses and the data buses that interface the s12x masters (cpu, bdm ) with the rest of the system (master buses). in addition the mmc handles all cpu read data bus swapping operations. all internal resources are connected to speci? target buses (see figure 3-20 ). figure 3-20. mmc block diagram cpu bdm target bus controller dbg mmc address decoder & priority peripherals pgmflash data flash ram s12x1 s12x0 xbus0
memory mapping control (s12xmmcv4) s12xs family reference manual, rev. 1.10 148 freescale semiconductor 3.4.3.1 master bus prioritization regarding access con?cts on target buses the arbitration scheme allows only one master to be connected to a target at any given time. the following rules apply when prioritizing accesses from different masters to the same target bus: cpu always has priority over bdm . bdm has priority over cpu when its access is stalled for more than 128 cycles. in the later case the suspect master will be stalled after ?ishing the current operation and the bdm will gain access to the bus. 3.5 initialization/application information 3.5.1 call and rtc instructions call and rtc instructions are uninterruptible cpu instructions that automate page switching in the program page window. the call instruction is similar to the jsr instruction, but the subroutine that is called can be located anywhere in the local address space or in any flash or rom page visible through the program page window. the call instruction calculates and stacks a return address, stacks the current ppage value and writes a new instruction-supplied value to the ppage register. the ppage value controls which of the 256 possible pages is visible through the 16kb program page window in the 64kb local cpu memory map. execution then begins at the address of the called subroutine. during the execution of the call instruction, the cpu performs the following steps: 1. writes the current ppage value into an internal temporary register and writes the new instruction- supplied ppage value into the ppage register 2. calculates the address of the next instruction after the call instruction (the return address) and pushes this 16-bit value onto the stack 3. pushes the temporarily stored ppage value onto the stack 4. calculates the effective address of the subroutine, re?ls the queue and begins execution at the new address this sequence is uninterruptible. there is no need to inhibit interrupts during the call instruction execution. a call instruction can be performed from any address to any other address in the local cpu memory space. the ppage value supplied by the instruction is part of the effective address of the cpu. for all addressing mode variations (except indexed-indirect modes) the new page value is provided by an immediate operand in the instruction. in indexed-indirect variations of the call instruction a pointer speci?s memory locations where the new page value and the address of the called subroutine are stored. using indirect addressing for both the new page value and the address within the page allows usage of values calculated at run time rather than immediate values that must be known at the time of assembly. the rtc instruction terminates subroutines invoked by a call instruction. the rtc instruction unstacks the ppage value and the return address and re?ls the queue. execution resumes with the next instruction after the call instruction.
memory mapping control (s12xmmcv4) s12xs family reference manual, rev. 1.10 freescale semiconductor 149 during the execution of an rtc instruction the cpu performs the following steps: 1. pulls the previously stored ppage value from the stack 2. pulls the 16-bit return address from the stack and loads it into the pc 3. writes the ppage value into the ppage register 4. re?ls the queue and resumes execution at the return address this sequence is uninterruptible. the rtc can be executed from anywhere in the local cpu memory space. the call and rtc instructions behave like jsr and rts instruction, they however require more execution cycles. usage of jsr/rts instructions is therefore recommended when possible and call/rtc instructions should only be used when needed. the jsr and rts instructions can be used to access subroutines that are already present in the local cpu memory map (i.e. in the same page in the program memory page window for example). however calling a function located in a different page requires usage of the call instruction. the function must be terminated by the rtc instruction. because the rtc instruction restores contents of the ppage register from the stack, functions terminated with the rtc instruction must be called using the call instruction even when the correct page is already present in the memory map. this is to make sure that the correct ppage value will be present on stack at the time of the rtc instruction execution.
memory mapping control (s12xmmcv4) s12xs family reference manual, rev. 1.10 150 freescale semiconductor
s12xs family reference manual, rev. 1.10 freescale semiconductor 151 chapter 4 interrupt (s12xintv2) 4.1 introduction the xint module decodes the priority of all system exception requests and provides the applicable vector for processing the exception to either the cpu or the xgate module. the xint module supports: i bit and x bit maskable interrupt requests one non-maskable unimplemented op-code trap one non-maskable software interrupt (swi) or background debug mode request one non-maskable system call interrupt (sys) three non-maskable access violation interrupt one spurious interrupt vector request three system reset vector requests each of the i bit maskable interrupt requests can be assigned to one of seven priority levels supporting a ?xible priority scheme. for interrupt requests that are con?ured to be handled by the cpu, the priority scheme can be used to implement nested interrupt capability where interrupts from a lower level are automatically blocked if a higher level interrupt is being processed. interrupt requests con?ured to be handled by the xgate module can be nested one level deep. note the hprio register and functionality of the original s12 interrupt module is no longer supported, since it is superseded by the 7-level interrupt request priority scheme. table 4-1. revision history revision number revision date sections affected description of changes v02.00 01 jul 2005 4.1.2/4-152 initial v2 release, added new features: - xgate threads can be interrupted. - sys instruction vector. - access violation interrupt vectors. v02.04 11 jan 2007 4.3.2.2/4-157 4.3.2.4/4-158 - added notes for devices without xgate module. v02.05 20 mar 2007 4.4.6/4-164 - fixed priority de?ition for software exceptions. v02.06 07 jan 2008 4.5.3.1/4-166 - added clari?ation of ?ake-up from stop or wait by xirq with x bit set feature.
interrupt (s12xintv2) s12xs family reference manual, rev. 1.10 152 freescale semiconductor 4.1.1 glossary the following terms and abbreviations are used in the document. 4.1.2 features interrupt vector base register (ivbr) one spurious interrupt vector (at address vector base 1 + 0x0010). one non-maskable system call interrupt vector request (at address vector base + 0x0012). three non-maskable access violation interrupt vector requests (at address vector base + 0x0014 ? 0x0018). 2?09 i bit maskable interrupt vector requests (at addresses vector base + 0x001a?x00f2). each i bit maskable interrupt request has a con?urable priority level and can be con?ured to be handled by either the cpu or the xgate module 2 . i bit maskable interrupts can be nested, depending on their priority levels. one x bit maskable interrupt vector request (at address vector base + 0x00f4). one non-maskable software interrupt request (swi) or background debug mode vector request (at address vector base + 0x00f6). one non-maskable unimplemented op-code trap (trap) vector (at address vector base + 0x00f8). three system reset vectors (at addresses 0xfffa?xfffe). determines the highest priority xgate and interrupt vector requests, drives the vector to the xgate module or to the bus on cpu request, respectively. wakes up the system from stop or wait mode when an appropriate interrupt request occurs or whenever xirq is asserted, even if x interrupt is masked. xgate can wake up and execute code, even with the cpu remaining in stop or wait mode. table 4-2. terminology term meaning ccr condition code register (in the s12x cpu) dma direct memory access int interrupt ipl interrupt processing level isr interrupt service routine mcu micro-controller unit xgate refers to the xgate co-processor; xgate is an optional feature irq refers to the interrupt request associated with the irq pin xirq refers to the interrupt request associated with the xirq pin 1. the vector base is a 16-bit address which is accumulated from the contents of the interrupt vector base register (ivbr, used as upper byte) and 0x00 (used as lower byte). 2. the irq interrupt can only be handled by the cpu
interrupt (s12xintv2) s12xs family reference manual, rev. 1.10 freescale semiconductor 153 4.1.3 modes of operation run mode this is the basic mode of operation. wait mode in wait mode, the xint module is frozen. it is however capable of either waking up the cpu if an interrupt occurs or waking up the xgate if an xgate request occurs. please refer to section 4.5.3, ?ake up from stop or wait mode for details. stop mode in stop mode, the xint module is frozen. it is however capable of either waking up the cpu if an interrupt occurs or waking up the xgate if an xgate request occurs. please refer to section 4.5.3, ?ake up from stop or wait mode for details. freeze mode (bdm active) in freeze mode (bdm active), the interrupt vector base register is overridden internally. please refer to section 4.3.2.1, ?nterrupt vector base register (ivbr) for details.
interrupt (s12xintv2) s12xs family reference manual, rev. 1.10 154 freescale semiconductor 4.1.4 block diagram figure 4-1 shows a block diagram of the xint module. figure 4-1. xint block diagram 4.2 external signal description the xint module has no external signals. wake up current rqst ivbr one set per channel xgate interrupts xgate requests interrupt requests interrupt requests cpu vector address new ipl ipl (up to 108 channels) rqst xgate request route, priolvln priority level = bits from the channel con?uration in the associated con?uration register int_xgprio = xgate interrupt priority ivbr = interrupt vector base ipl = interrupt processing level priolvl0 priolvl1 priolvl2 int_xgprio peripheral vector id to xgate module priority decoder to cpu priority decoder non i bit maskable channels wake up xgate irq channel
interrupt (s12xintv2) s12xs family reference manual, rev. 1.10 freescale semiconductor 155 4.3 memory map and register de?ition this section provides a detailed description of all registers accessible in the xint module. 4.3.1 module memory map table 4-3 gives an overview over all xint module registers. table 4-3. xint memory map address use access 0x0120 reserved 0x0121 interrupt vector base register (ivbr) r/w 0x0122?x0125 reserved 0x0126 xgate interrupt priority con?uration register (int_xgprio) r/w 0x0127 interrupt request con?uration address register (int_cfaddr) r/w 0x0128 interrupt request con?uration data register 0 (int_cfdata0) r/w 0x0129 interrupt request con?uration data register 1 (int_cfdata1) r/w 0x012a interrupt request con?uration data register 2 (int_cfdata2 r/w 0x012b interrupt request con?uration data register 3 (int_cfdata3) r/w 0x012c interrupt request con?uration data register 4 (int_cfdata4) r/w 0x012d interrupt request con?uration data register 5 (int_cfdata5) r/w 0x012e interrupt request con?uration data register 6 (int_cfdata6) r/w 0x012f interrupt request con?uration data register 7 (int_cfdata7) r/w
interrupt (s12xintv2) s12xs family reference manual, rev. 1.10 156 freescale semiconductor 4.3.2 register descriptions this section describes in address order all the xint module registers and their individual bits. address register name bit 7 654321 bit 0 0x0121 ivbr r ivb_addr[7:0]7 w 0x0126 int_xgprio r 00000 xilvl[2:0] w 0x0127 int_cfaddr r int_cfaddr[7:4] 0000 w 0x0128 int_cfdata0 r rqst 0000 priolvl[2:0] w 0x0129 int_cfdata1 r rqst 0000 priolvl[2:0] w 0x012a int_cfdata2 r rqst 0000 priolvl[2:0] w 0x012b int_cfdata3 r rqst 0000 priolvl[2:0] w 0x012c int_cfdata4 r rqst 0000 priolvl[2:0] w 0x012d int_cfdata5 r rqst 0000 priolvl[2:0] w 0x012e int_cfdata6 r rqst 0000 priolvl[2:0] w 0x012f int_cfdata7 r rqst 0000 priolvl[2:0] w = unimplemented or reserved figure 4-2. xint register summary
interrupt (s12xintv2) s12xs family reference manual, rev. 1.10 freescale semiconductor 157 4.3.2.1 interrupt vector base register (ivbr) read: anytime write: anytime 4.3.2.2 xgate interrupt priority con?uration register (int_xgprio) read: anytime write: anytime address: 0x0121 76543210 r ivb_addr[7:0] w reset 1 1 1 11111 figure 4-3. interrupt vector base register (ivbr) table 4-4. ivbr field descriptions field description 7? ivb_addr[7:0] interrupt vector base address bits these bits represent the upper byte of all vector addresses. out of reset these bits are set to 0xff (i.e., vectors are located at 0xff10?xfffe) to ensure compatibility to previous s12 microcontrollers. note: a system reset will initialize the interrupt vector base register with ?xff before it is used to determine the reset vector address. therefore, changing the ivbr has no effect on the location of the three reset vectors (0xfffa?xfffe). note: if the bdm is active (i.e., the cpu is in the process of executing bdm ?mware code), the contents of ivbr are ignored and the upper byte of the vector address is ?ed as ?xff? address: 0x0126 76543210 r00000 xilvl[2:0] w reset 0 0 0 00001 = unimplemented or reserved figure 4-4. xgate interrupt priority con?uration register (int_xgprio) table 4-5. int_xgprio field descriptions field description 2? xilvl[2:0] xgate interrupt priority level ?the xilvl[2:0] bits configure the shared interrupt level of the xgate interrupts coming from the xgate module. out of reset the priority is set to the lowest active level (??. note: if the xgate module is not available on the device, write accesses to this register are ignored and read accesses to this register will return all 0.
interrupt (s12xintv2) s12xs family reference manual, rev. 1.10 158 freescale semiconductor 4.3.2.3 interrupt request con?uration address register (int_cfaddr) read: anytime write: anytime 4.3.2.4 interrupt request con?uration data registers (int_cfdata0?) the eight register window visible at addresses int_cfdata0? contains the con?uration data for the block of eight interrupt requests (out of 128) selected by the interrupt con?uration address register (int_cfaddr) in ascending order. int_cfdata0 represents the interrupt con?uration data register of the vector with the lowest address in this block, while int_cfdata7 represents the interrupt con?uration data register of the vector with the highest address, respectively. table 4-6. xgate interrupt priority levels priority xilvl2 xilvl1 xilvl0 meaning 0 0 0 interrupt request is disabled low 0 0 1 priority level 1 0 1 0 priority level 2 0 1 1 priority level 3 1 0 0 priority level 4 1 0 1 priority level 5 1 1 0 priority level 6 high 1 1 1 priority level 7 address: 0x0127 76543210 r int_cfaddr[7:4] 0000 w reset 0 0 0 10000 = unimplemented or reserved figure 4-5. interrupt con?uration address register (int_cfaddr) table 4-7. int_cfaddr field descriptions field description 7? int_cfaddr[7:4] interrupt request con?uration data register select bits ?these bits determine which of the 128 con?uration data registers are accessible in the 8 register window at int_cfdata0?. the hexadecimal value written to this register corresponds to the upper nibble of the lower byte of the address of the interrupt vector, i.e., writing 0xe0 to this register selects the con?uration data register block for the 8 interrupt vector requests starting with vector at address (vector base + 0x00e0) to be accessible as int_cfdata0?. note: writing all 0s selects non-existing con?uration registers. in this case write accesses to int_cfdata0? will be ignored and read accesses will return all 0.
interrupt (s12xintv2) s12xs family reference manual, rev. 1.10 freescale semiconductor 159 address: 0x0128 76543210 r rqst 0000 priolvl[2:0] w reset 0 0 0 00001 1 1 please refer to the notes following the priolvl[2:0] description below. = unimplemented or reserved figure 4-6. interrupt request con?uration data register 0 (int_cfdata0) address: 0x0129 76543210 r rqst 0000 priolvl[2:0] w reset 0 0 0 00001 1 1 please refer to the notes following the priolvl[2:0] description below. = unimplemented or reserved figure 4-7. interrupt request con?uration data register 1 (int_cfdata1) address: 0x012a 76543210 r rqst 0000 priolvl[2:0] w reset 0 0 0 00001 1 1 please refer to the notes following the priolvl[2:0] description below. = unimplemented or reserved figure 4-8. interrupt request con?uration data register 2 (int_cfdata2) address: 0x012b 76543210 r rqst 0000 priolvl[2:0] w reset 0 0 0 00001 1 1 please refer to the notes following the priolvl[2:0] description below. = unimplemented or reserved figure 4-9. interrupt request con?uration data register 3 (int_cfdata3)
interrupt (s12xintv2) s12xs family reference manual, rev. 1.10 160 freescale semiconductor read: anytime write: anytime address: 0x012c 76543210 r rqst 0000 priolvl[2:0] w reset 0 0 0 00001 1 1 please refer to the notes following the priolvl[2:0] description below. = unimplemented or reserved figure 4-10. interrupt request con?uration data register 4 (int_cfdata4) address: 0x012d 76543210 r rqst 0000 priolvl[2:0] w reset 0 0 0 00001 1 1 please refer to the notes following the priolvl[2:0] description below. = unimplemented or reserved figure 4-11. interrupt request con?uration data register 5 (int_cfdata5) address: 0x012e 76543210 r rqst 0000 priolvl[2:0] w reset 0 0 0 00001 1 1 please refer to the notes following the priolvl[2:0] description below. = unimplemented or reserved figure 4-12. interrupt request con?uration data register 6 (int_cfdata6) address: 0x012f 76543210 r rqst 0000 priolvl[2:0] w reset 0 0 0 00001 1 1 please refer to the notes following the priolvl[2:0] description below. = unimplemented or reserved figure 4-13. interrupt request con?uration data register 7 (int_cfdata7)
interrupt (s12xintv2) s12xs family reference manual, rev. 1.10 freescale semiconductor 161 4.4 functional description the xint module processes all exception requests to be serviced by the cpu module. these exceptions include interrupt vector requests and reset vector requests. each of these exception types and their overall priority level is discussed in the subsections below. table 4-8. int_cfdata0? field descriptions field description 7 rqst xgate request enable this bit determines if the associated interrupt request is handled by the cpu or by the xgate module. 0 interrupt request is handled by the cpu 1 interrupt request is handled by the xgate module note: the irq interrupt cannot be handled by the xgate module. for this reason, the con?uration register for vector (vector base + 0x00f2) = irq vector address) does not contain a rqst bit. writing a 1 to the location of the rqst bit in this register will be ignored and a read access will return 0. note: if the xgate module is not available on the device, writing a 1 to the location of the rqst bit in this register will be ignored and a read access will return 0. 2? priolvl[2:0] interrupt request priority level bits the priolvl[2:0] bits con?ure the interrupt request priority level of the associated interrupt request. out of reset all interrupt requests are enabled at the lowest active level (?? to provide backwards compatibility with previous s12 interrupt controllers. please also refer to table 4-9 for available interrupt request priority levels. note: write accesses to con?uration data registers of unused interrupt channels will be ignored and read accesses will return all 0. for information about what interrupt channels are used in a speci? mcu, please refer to the device reference manual of that mcu. note: when vectors (vector base + 0x00f0?x00fe) are selected by writing 0xf0 to int_cfaddr, writes to int_cfdata2? (0x00f4?x00fe) will be ignored and read accesses will return all 0s. the corresponding vectors do not have con?uration data registers associated with them. note: when vectors (vector base + 0x0010?x001e) are selected by writing 0x10 to int_cfaddr, writes to int_cfdata1?nt_cfdata4 (0x0012?x0018) will be ignored and read accesses will return all 0s. the corresponding vectors do not have con?uration data registers associated with them. note: write accesses to the con?uration register for the spurious interrupt vector request (vector base + 0x0010) will be ignored and read accesses will return 0x07 (request is handled by the cpu, priolvl = 7). table 4-9. interrupt priority levels priority priolvl2 priolvl1 priolvl0 meaning 0 0 0 interrupt request is disabled low 0 0 1 priority level 1 0 1 0 priority level 2 0 1 1 priority level 3 1 0 0 priority level 4 1 0 1 priority level 5 1 1 0 priority level 6 high 1 1 1 priority level 7
interrupt (s12xintv2) s12xs family reference manual, rev. 1.10 162 freescale semiconductor 4.4.1 s12x exception requests the cpu handles both reset requests and interrupt requests. the xint module contains registers to con?ure the priority level of each i bit maskable interrupt request which can be used to implement an interrupt priority scheme. this also includes the possibility to nest interrupt requests. a priority decoder is used to evaluate the priority of a pending interrupt request. 4.4.2 interrupt prioritization after system reset all interrupt requests with a vector address lower than or equal to (vector base + 0x00f2) are enabled, are set up to be handled by the cpu and have a pre-con?ured priority level of 1. exceptions to this rule are the non-maskable interrupt requests and the spurious interrupt vector request at (vector base + 0x0010) which cannot be disabled, are always handled by the cpu and have a ?ed priority levels. a priority level of 0 effectively disables the associated i bit maskable interrupt request. if more than one interrupt request is con?ured to the same interrupt priority level the interrupt request with the higher vector address wins the prioritization. the following conditions must be met for an i bit maskable interrupt request to be processed. 1. the local interrupt enabled bit in the peripheral module must be set. 2. the setup in the con?uration register associated with the interrupt request channel must meet the following conditions: a) the xgate request enable bit must be 0 to have the cpu handle the interrupt request. b) the priority level must be set to non zero. c) the priority level must be greater than the current interrupt processing level in the condition code register (ccr) of the cpu (priolvl[2:0] > ipl[2:0]). 3. the i bit in the condition code register (ccr) of the cpu must be cleared. 4. there is no access violation interrupt request pending. 5. there is no sys, swi, bdm, trap, or xirq request pending. note all non i bit maskable interrupt requests always have higher priority than i bit maskable interrupt requests. if an i bit maskable interrupt request is interrupted by a non i bit maskable interrupt request, the currently active interrupt processing level (ipl) remains unaffected. it is possible to nest non i bit maskable interrupt requests, e.g., by nesting swi or trap calls. 4.4.2.1 interrupt priority stack the current interrupt processing level (ipl) is stored in the condition code register (ccr) of the cpu. this way the current ipl is automatically pushed to the stack by the standard interrupt stacking procedure. the new ipl is copied to the ccr from the priority level of the highest priority active interrupt request channel which is con?ured to be handled by the cpu. the copying takes place when the interrupt vector is fetched. the previous ipl is automatically restored by executing the rti instruction.
interrupt (s12xintv2) s12xs family reference manual, rev. 1.10 freescale semiconductor 163 4.4.3 xgate requests if the xgate module is implemented on the device, the xint module is also used to process all exception requests to be serviced by the xgate module. the overall priority level of those exceptions is discussed in the subsections below. 4.4.3.1 xgate request prioritization an interrupt request channel is con?ured to be handled by the xgate module, if the rqst bit of the associated con?uration register is set to 1 (please refer to section 4.3.2.4, ?nterrupt request con?uration data registers (int_cfdata0?) ). the priority level con?uration (priolvl) for this channel becomes the xgate priority which will be used to determine the highest priority xgate request to be serviced next by the xgate module. additionally, xgate interrupts may be raised by the xgate module by setting one or more of the xgate channel interrupt ?gs (by using the sif instruction). this will result in an cpu interrupt with vector address vector base + (2 * channel id number), where the channel id number corresponds to the highest set channel interrupt ?g, if the xgie and channel rqst bits are set. the shared interrupt priority for the xgate interrupt requests is taken from the xgate interrupt priority con?uration register (please refer to section 4.3.2.2, ?gate interrupt priority con?uration register (int_xgprio) ). if more than one xgate interrupt request channel becomes active at the same time, the channel with the highest vector address wins the prioritization. 4.4.4 priority decoders the xint module contains priority decoders to determine the priority for all interrupt requests pending for the respective target. there are two priority decoders, one for each interrupt request target, cpu or xgate. the function of both priority decoders is basically the same with one exception: the priority decoder for the xgate module does not take the current xgate thread processing level into account. instead, xgate requests are handed to the xgate module including a 1-bit priority identi?r. the xgate module uses this additional information to decide if the new request can interrupt a currently running thread. the 1-bit priority identi?r corresponds to the most signi?ant bit of the priority level con?uration of the requesting channel. this means that xgate requests with priority levels 4, 5, 6 or 7 can interrupt running xgate threads with priority levels 1, 2 and 3. a cpu interrupt vector is not supplied until the cpu requests it. therefore, it is possible that a higher priority interrupt request could override the original exception which caused the cpu to request the vector. in this case, the cpu will receive the highest priority vector and the system will process this exception instead of the original request. if the interrupt source is unknown (for example, in the case where an interrupt request becomes inactive after the interrupt has been recognized, but prior to the vector request), the vector address supplied to the cpu will default to that of the spurious interrupt vector.
interrupt (s12xintv2) s12xs family reference manual, rev. 1.10 164 freescale semiconductor note care must be taken to ensure that all exception requests remain active until the system begins execution of the applicable service routine; otherwise, the exception request may not get processed at all or the result may be a spurious interrupt request (vector at address (vector base + 0x0010)). 4.4.5 reset exception requests the xint module supports three system reset exception request types (for details please refer to the clock and reset generator module (crg)): 1. pin reset, power-on reset, low-voltage reset, or illegal address reset 2. clock monitor reset request 3. cop watchdog reset request 4.4.6 exception priority the priority (from highest to lowest) and address of all exception vectors issued by the xint module upon request by the cpu is shown in table 4-10 . generally, all non-maskable interrupts have higher priorities than maskable interrupts. please note that between the three software interrupts (unimplemented op-code trap request, swi/bgnd request, sys request) there is no real priority de?ed because they cannot occur simultaneously (the s12xcpu executes one instruction at a time). table 4-10. exception vector map and priority vector address 1 1 16 bits vector address based source 0xfffe pin reset, power-on reset, low-voltage reset, illegal address reset 0xfffc clock monitor reset 0xfffa cop watchdog reset (vector base + 0x00f8) unimplemented op-code trap (vector base + 0x00f6) software interrupt instruction (swi) or bdm vector request (vector base + 0x0012) system call interrupt instruction (sys) (vector base + 0x0018) (reserved for future use) (vector base + 0x0016) xgate access violation interrupt request 2 2 only implemented if device features both a memory protection unit (mpu) and an xgate co-processor (vector base + 0x0014) cpu access violation interrupt request 3 3 only implemented if device features a memory protection unit (mpu) (vector base + 0x00f4) xirq interrupt request (vector base + 0x00f2) irq interrupt request (vector base + 0x00f0?x001a) device speci? i bit maskable interrupt sources (priority determined by the associated con?uration registers, in descending order) (vector base + 0x0010) spurious interrupt
interrupt (s12xintv2) s12xs family reference manual, rev. 1.10 freescale semiconductor 165 4.5 initialization/application information 4.5.1 initialization after system reset, software should: initialize the interrupt vector base register if the interrupt vector table is not located at the default location (0xff10?xfff9). initialize the interrupt processing level con?uration data registers (int_cfaddr, int_cfdata0?) for all interrupt vector requests with the desired priority levels and the request target (cpu or xgate module). it might be a good idea to disable unused interrupt requests. if the xgate module is used, setup the xgate interrupt priority register (int_xgprio) and con?ure the xgate module (please refer the xgate block guide for details). enable i maskable interrupts by clearing the i bit in the ccr. enable the x maskable interrupt by clearing the x bit in the ccr (if required). 4.5.2 interrupt nesting the interrupt request priority level scheme makes it possible to implement priority based interrupt request nesting for the i bit maskable interrupt requests handled by the cpu. i bit maskable interrupt requests can be interrupted by an interrupt request with a higher priority, so that there can be up to seven nested i bit maskable interrupt requests at a time (refer to figure 4- 14 for an example using up to three nested interrupt requests). i bit maskable interrupt requests cannot be interrupted by other i bit maskable interrupt requests per default. in order to make an interrupt service routine (isr) interruptible, the isr must explicitly clear the i bit in the ccr (cli). after clearing the i bit, i bit maskable interrupt requests with higher priority can interrupt the current isr. an isr of an interruptible i bit maskable interrupt request could basically look like this: service interrupt, e.g., clear interrupt ?gs, copy data, etc. clear i bit in the ccr by executing the instruction cli (thus allowing interrupt requests with higher priority) process data return from interrupt by executing the instruction rti
interrupt (s12xintv2) s12xs family reference manual, rev. 1.10 166 freescale semiconductor figure 4-14. interrupt processing example 4.5.3 wake up from stop or wait mode 4.5.3.1 cpu wake up from stop or wait mode every i bit maskable interrupt request which is con?ured to be handled by the cpu is capable of waking the mcu from stop or wait mode. to determine whether an i bit maskable interrupts is quali?d to wake up the cpu or not, the same settings as in normal run mode are applied during stop or wait mode: if the i bit in the ccr is set, all i bit maskable interrupts are masked from waking up the mcu. an i bit maskable interrupt is ignored if it is con?ured to a priority level below or equal to the current ipl in ccr. i bit maskable interrupt requests which are con?ured to be handled by the xgate module are not capable of waking up the cpu. the x bit maskable interrupt request can wake up the mcu from stop or wait mode at anytime, even if the x bit in ccr is set. if the x bit maskable interrupt request is used to wake-up the mcu with the x bit in the ccr set, the associated isr is not called. the cpu then resumes program execution with the instruction following the wai or stop instruction. this features works following the same rules like any interrupt request, i.e. care must be taken that the x interrupt request used for wake-up remains active at least until the system begins execution of the instruction following the wai or stop instruction; otherwise, wake-up may not occur. 4.5.3.2 xgate wake up from stop or wait mode interrupt request channels which are con?ured to be handled by the xgate module are capable of waking up the xgate module. interrupt request channels handled by the xgate module do not affect the state of the cpu. 0 reset 4 0 7 6 5 4 3 2 1 0 l4 7 0 4 l1 (pending) l7 l3 (pending) rti 4 0 3 0 rti rti 1 0 0 rti stacked ipl processing levels ipl in ccr
s12xs family reference manual, rev. 1.10 freescale semiconductor 167 chapter 5 background debug module (s12xbdmv2) 5.1 introduction this section describes the functionality of the background debug module (bdm) sub-block of the hcs12x core platform. the background debug module (bdm) sub-block is a single-wire, background debug system implemented in on-chip hardware for minimal cpu intervention. all interfacing with the bdm is done via the bkgd pin. the bdm has enhanced capability for maintaining synchronization between the target and host while allowing more ?xibility in clock rates. this includes a sync signal to determine the communication rate and a handshake signal to indicate when an operation is complete. the system is backwards compatible to the bdm of the s12 family with the following exceptions: taggo command no longer supported by bdm external instruction tagging feature now part of dbg module bdm register map and register content extended/modi?d global page access functionality enabled but not active out of reset in emulation modes (if modes available) clksw bit set out of reset in emulation modes (if modes available). family id readable from ?mware rom at global address 0x7fff0f (value for hcs12x devices is 0xc1) 5.1.1 features the bdm includes these distinctive features: single-wire communication with host development system enhanced capability for allowing more ?xibility in clock rates sync command to determine communication rate go_until command hardware handshake protocol to increase the performance of the serial communication table 5-1. revision history revision number revision date sections affected description of changes v02.00 07 mar 2006 - first version of s12xbdmv2 v02.01 14 may 2008 - introduced standardized revision history table
background debug module (s12xbdmv2) s12xs family reference manual, rev. 1.10 168 freescale semiconductor active out of reset in special single chip mode nine hardware commands using free cycles, if available, for minimal cpu intervention hardware commands not requiring active bdm 14 ?mware commands execute from the standard bdm ?mware lookup table software control of bdm operation during wait mode software selectable clocks global page access functionality enabled but not active out of reset in emulation modes (if modes available) clksw bit set out of reset in emulation modes (if modes available). when secured, hardware commands are allowed to access the register space in special single chip mode, if the non-volatile memory erase test fail. family id readable from ?mware rom at global address 0x7fff0f (value for hcs12x devices is 0xc1) bdm hardware commands are operational until system stop mode is entered (all bus masters are in stop mode) 5.1.2 modes of operation bdm is available in all operating modes but must be enabled before ?mware commands are executed. some systems may have a control bit that allows suspending thefunction during background debug mode. 5.1.2.1 regular run modes all of these operations refer to the part in run mode and not being secured. the bdm does not provide controls to conserve power during run mode. normal modes general operation of the bdm is available and operates the same in all normal modes. special single chip mode in special single chip mode, background operation is enabled and active out of reset. this allows programming a system with blank memory. emulation modes (if modes available) in emulation mode, background operation is enabled but not active out of reset. this allows debugging and programming a system in this mode more easily. 5.1.2.2 secure mode operation if the device is in secure mode, the operation of the bdm is reduced to a small subset of its regular run mode operation. secure operation prevents bdm and cpu accesses to non-volatile memory (flash and/or eeprom) other than allowing erasure. for more information please see section 5.4.1, ?ecurity .
background debug module (s12xbdmv2) s12xs family reference manual, rev. 1.10 freescale semiconductor 169 5.1.2.3 low-power modes the bdm can be used until all bus masters (e.g., cpu or xgate or others depending on which masters are available on the soc) are in stop mode. when cpu is in a low power mode (wait or stop mode) all bdm ?mware commands as well as the hardware background command can not be used respectively are ignored. in this case the cpu can not enter bdm active mode, and only hardware read and write commands are available. also the cpu can not enter a low power mode during bdm active mode. if all bus masters are in stop mode, the bdm clocks are stopped as well. when bdm clocks are disabled and one of the bus masters exits from stop mode the bdm clocks will restart and bdm will have a soft reset (clearing the instruction register, any command in progress and disable the ack function). the bdm is now ready to receive a new command. 5.1.3 block diagram a block diagram of the bdm is shown in figure 5-1 . figure 5-1. bdm block diagram 5.2 external signal description a single-wire interface pin called the background debug interface (bkgd) pin is used to communicate with the bdm system. during reset, this pin is a mode select input which selects between normal and special modes of operation. after reset, this pin becomes the dedicated serial interface pin for the background debug mode. enbdm clksw bdmact trace sdv 16-bit shift register bkgd host system serial interface data control unsec register block register bdmsts instruction code and execution standard bdm firmware lookup table secured bdm firmware lookup table bus interface and control logic address data control clocks
background debug module (s12xbdmv2) s12xs family reference manual, rev. 1.10 170 freescale semiconductor 5.3 memory map and register de?ition 5.3.1 module memory map table 5-2 shows the bdm memory map when bdm is active. 5.3.2 register descriptions a summary of the registers associated with the bdm is shown in figure 5-2 . registers are accessed by host-driven communications to the bdm hardware using read_bd and write_bd commands. table 5-2. bdm memory map global address module size (bytes) 0x7fff00?x7fff0b bdm registers 12 0x7fff0c?x7fff0e bdm ?mware rom 3 0x7fff0f family id (part of bdm ?mware rom) 1 0x7fff10?x7fffff bdm ?mware rom 240 global address register name bit 7 6 5 4 3 2 1 bit 0 0x7fff00 reserved r x x x x x x 0 0 w 0x7fff01 bdmsts r enbdm bdmact 0 sdv trace clksw unsec 0 w 0x7fff02 reserved r x x x x x x x x w 0x7fff03 reserved r x x x x x x x x w 0x7fff04 reserved r x x x x x x x x w 0x7fff05 reserved r x x x x x x x x w 0x7fff06 bdmccrl r ccr7 ccr6 ccr5 ccr4 ccr3 ccr2 ccr1 ccr0 w = unimplemented, reserved = implemented (do not alter) x = indeterminate 0 = always read zero figure 5-2. bdm register summary
background debug module (s12xbdmv2) s12xs family reference manual, rev. 1.10 freescale semiconductor 171 5.3.2.1 bdm status register (bdmsts) figure 5-3. bdm status register ( bdmsts) 0x7fff07 bdmccrh r 0 0 0 0 0 ccr10 ccr9 ccr8 w 0x7fff08 bdmgpr r bgae bgp6 bgp5 bgp4 bgp3 bgp2 bgp1 bgp0 w 0x7fff09 reserved r 0 0 0 0 0 0 0 0 w 0x7fff0a reserved r 0 0 0 0 0 0 0 0 w 0x7fff0b reserved r 0 0 0 0 0 0 0 0 w register global address 0x7fff01 7 6 54 3 2 1 0 r enbdm bdmact 0sdv trace clksw unsec 0 w reset special single-chip mode 0 1 1 enbdm is read as 1 by a debugging environment in special single chip mode when the device is not secured or secured but fully erased (non-volatile memory). this is because the enbdm bit is set by the standard ?mware before a bdm command can be fully transmitted and executed. 1 00 0 0 0 3 3 unsec is read as 1 by a debugging environment in special single chip mode when the device is secured and fully erased, else it is 0 and can only be read if not secure (see also bit description). 0 emulation modes (if modes available) 1 0 00 0 1 2 2 clksw is read as 1 by a debugging environment in emulation modes when the device is not secured and read as 0 when secured if emulation modes available. 0 0 all other modes 0 0 00 0 0 0 0 = unimplemented, reserved = implemented (do not alter) 0 = always read zero global address register name bit 7 6 5 4 3 2 1 bit 0 = unimplemented, reserved = implemented (do not alter) x = indeterminate 0 = always read zero figure 5-2. bdm register summary (continued)
background debug module (s12xbdmv2) s12xs family reference manual, rev. 1.10 172 freescale semiconductor read: all modes through bdm operation when not secured write: all modes through bdm operation when not secured, but subject to the following: enbdm should only be set via a bdm hardware command if the bdm ?mware commands are needed. (this does not apply in special single chip and emulation modes). bdmact can only be set by bdm hardware upon entry into bdm. it can only be cleared by the standard bdm ?mware lookup table upon exit from bdm active mode. clksw can only be written via bdm hardware write_bd commands. all other bits, while writable via bdm hardware or standard bdm ?mware write commands, should only be altered by the bdm hardware or standard ?mware lookup table as part of bdm command execution. table 5-3. bdmsts field descriptions field description 7 enbdm enable bdm ?this bit controls whether the bdm is enabled or disabled. when enabled, bdm can be made active to allow ?mware commands to be executed. when disabled, bdm cannot be made active but bdm hardware commands are still allowed. 0 bdm disabled 1 bdm enabled note: enbdm is set by the ?mware out of reset in special single chip mode. in emulation modes (if modes available) the enbdm bit is set by bdm hardware out of reset. in special single chip mode with the device secured, this bit will not be set by the ?mware until after the non-volatile memory erase verify tests are complete. in emulation modes (if modes available) with the device secured, the bdm operations are blocked. 6 bdmact bdm active status ?this bit becomes set upon entering bdm. the standard bdm ?mware lookup table is then enabled and put into the memory map. bdmact is cleared by a carefully timed store instruction in the standard bdm ?mware as part of the exit sequence to return to user code and remove the bdm memory from the map. 0 bdm not active 1 bdm active 4 sdv shift data valid this bit is set and cleared by the bdm hardware. it is set after data has been transmitted as part of a ?mware or hardware read command or after data has been received as part of a ?mware or hardware write command. it is cleared when the next bdm command has been received or bdm is exited. sdv is used by the standard bdm ?mware to control program ?w execution. 0 data phase of command not complete 1 data phase of command is complete 3 trace trace1 bdm firmware command is being executed ?this bit gets set when a bdm trace1 ?mware command is ?st recognized. it will stay set until bdm ?mware is exited by one of the following bdm commands: go or go_until. 0 trace1 command is not being executed 1 trace1 command is being executed
background debug module (s12xbdmv2) s12xs family reference manual, rev. 1.10 freescale semiconductor 173 2 clksw clock switch the clksw bit controls which clock the bdm operates with. it is only writable from a hardware bdm command. a minimum delay of 150 cycles at the clock speed that is active during the data portion of the command send to change the clock source should occur before the next command can be send. the delay should be obtained no matter which bit is modi?d to effectively change the clock source (either pllsel bit or clksw bit). this guarantees that the start of the next bdm command uses the new clock for timing subsequent bdm communications. table 5-4 shows the resulting bdm clock source based on the clksw and the pllsel (pll select in the crg module, the bit is part of the clksel register) bits. note: the bdm alternate clock source can only be selected when clksw = 0 and pllsel = 1. the bdm serial interface is now fully synchronized to the alternate clock source, when enabled. this eliminates frequency restriction on the alternate clock which was required on previous versions. refer to the device speci?ation to determine which clock connects to the alternate clock source input. note: if the acknowledge function is turned on, changing the clksw bit will cause the ack to be at the new rate for the write command which changes it. note: in emulation modes (if modes available), the clksw bit will be set out of reset. 1 unsec unsecure ?if the device is secured this bit is only writable in special single chip mode from the bdm secure ?mware. it is in a zero state as secure mode is entered so that the secure bdm ?mware lookup table is enabled and put into the memory map overlapping the standard bdm ?mware lookup table. the secure bdm ?mware lookup table veri?s that the non-volatile memories (e.g. on-chip eeprom and/or flash eeprom) are erased. this being the case, the unsec bit is set and the bdm program jumps to the start of the standard bdm ?mware lookup table and the secure bdm ?mware lookup table is turned off. if the erase test fails, the unsec bit will not be asserted. 0 system is in a secured mode. 1 system is in a unsecured mode. note: when unsec is set, security is off and the user can change the state of the secure bits in the on-chip flash eeprom. note that if the user does not change the state of the bits to ?nsecured?mode, the system will be secured again when it is next taken out of reset.after reset this bit has no meaning or effect when the security byte in the flash eeprom is con?ured for unsecure mode. table 5-4. bdm clock sources pllsel clksw bdmclk 0 0 bus clock dependent on oscillator 0 1 bus clock dependent on oscillator 1 0 alternate clock (refer to the device speci?ation to determine the alternate clock source) 1 1 bus clock dependent on the pll table 5-3. bdmsts field descriptions (continued) field description
background debug module (s12xbdmv2) s12xs family reference manual, rev. 1.10 174 freescale semiconductor 5.3.2.2 bdm ccr low holding register (bdmccrl) figure 5-4. bdm ccr low holding register (bdmccrl) read: all modes through bdm operation when not secured write: all modes through bdm operation when not secured note when bdm is made active, the cpu stores the content of its ccr l register in the bdmccrl register. however, out of special single-chip reset, the bdmccrl is set to 0xd8 and not 0xd0 which is the reset value of the ccr l register in this cpu mode. out of reset in all other modes the bdmccrl register is read zero. when entering background debug mode, the bdm ccr low holding register is used to save the low byte of the condition code register of the users program. it is also used for temporary storage in the standard bdm ?mware mode. the bdm ccr low holding register can be written to modify the ccr value. 5.3.2.3 bdm ccr high holding register (bdmccrh) figure 5-5. bdm ccr high holding register (bdmccrh) read: all modes through bdm operation when not secured write: all modes through bdm operation when not secured when entering background debug mode, the bdm ccr high holding register is used to save the high byte of the condition code register of the users program. the bdm ccr high holding register can be written to modify the ccr value. register global address 0x7fff06 7 6 5 4 3 2 1 0 r ccr7 ccr6 ccr5 ccr4 ccr3 ccr2 ccr1 ccr0 w reset special single-chip mode 1 1 0 0 1 0 0 0 all other modes 0 0 0 0 0 0 0 0 register global address 0x7fff07 7 6 5 4 3 2 1 0 r 0 0 0 0 0 ccr10 ccr9 ccr8 w reset 0 0 0 0 0 0 0 0 = unimplemented or reserved
background debug module (s12xbdmv2) s12xs family reference manual, rev. 1.10 freescale semiconductor 175 5.3.2.4 bdm global page index register (bdmgpr) figure 5-6. bdm global page register (bdmgpr) read: all modes through bdm operation when not secured write: all modes through bdm operation when not secured 5.3.3 family id assignment the family id is a 8-bit value located in the ?mware rom (at global address: 0x7fff0f). the read-only value is a unique family id which is 0xc1 for s12x devices. 5.4 functional description the bdm receives and executes commands from a host via a single wire serial interface. there are two types of bdm commands: hardware and ?mware commands. hardware commands are used to read and write target system memory locations and to enter active background debug mode, see section 5.4.3, ?dm hardware commands . target system memory includes all memory that is accessible by the cpu. firmware commands are used to read and write cpu resources and to exit from active background debug mode, see section 5.4.4, ?tandard bdm firmware commands . the cpu resources referred to are the accumulator (d), x index register (x), y index register (y), stack pointer (sp), and program counter (pc). hardware commands can be executed at any time and in any mode excluding a few exceptions as highlighted (see section 5.4.3, ?dm hardware commands ) and in secure mode (see section 5.4.1, ?ecurity ). firmware commands can only be executed when the system is not secure and is in active background debug mode (bdm). register global address 0x7fff08 7 6 5 4 3 2 1 0 r bgae bgp6 bgp5 bgp4 bgp3 bgp2 bgp1 bgp0 w reset 0 0 0 0 0 0 0 0 table 5-5. bdmgpr field descriptions field description 7 bgae bdm global page access enable bit bgae enables global page access for bdm hardware and ?mware read/write instructions the bdm hardware commands used to access the bdm registers (read_bd_ and write_bd_) can not be used for global accesses even if the bgae bit is set. 0 bdm global access disabled 1 bdm global access enabled 6? bgp[6:0] bdm global page index bits 6? ?these bits de?e the extended address bits from 22 to 16. for more detailed information regarding the global page window scheme, please refer to the s12x_mmc block guide.
background debug module (s12xbdmv2) s12xs family reference manual, rev. 1.10 176 freescale semiconductor 5.4.1 security if the user resets into special single chip mode with the system secured, a secured mode bdm ?mware lookup table is brought into the map overlapping a portion of the standard bdm ?mware lookup table. the secure bdm ?mware veri?s that the on-chip non-volatile memory (e.g. eeprom and flash eeprom) is erased. this being the case, the unsec and enbdm bit will get set. the bdm program jumps to the start of the standard bdm ?mware and the secured mode bdm ?mware is turned off and all bdm commands are allowed. if the non-volatile memory does not verify as erased, the bdm ?mware sets the enbdm bit, without asserting unsec, and the ?mware enters a loop. this causes the bdm hardware commands to become enabled, but does not enable the ?mware commands. this allows the bdm hardware to be used to erase the non-volatile memory. bdm operation is not possible in any other mode than special single chip mode when the device is secured. the device can be unsecured via bdm serial interface in special single chip mode only. for more information regarding security, please see the s12x_9sec block guide. 5.4.2 enabling and activating bdm the system must be in active bdm to execute standard bdm ?mware commands. bdm can be activated only after being enabled. bdm is enabled by setting the enbdm bit in the bdm status (bdmsts) register. the enbdm bit is set by writing to the bdm status (bdmsts) register, via the single-wire interface, using a hardware command such as write_bd_byte. after being enabled, bdm is activated by one of the following 1 : hardware background command cpu bgnd instruction external instruction tagging mechanism 2 breakpoint force or tag mechanism 2 when bdm is activated, the cpu ?ishes executing the current instruction and then begins executing the ?mware in the standard bdm ?mware lookup table. when bdm is activated by a breakpoint, the type of breakpoint used determines if bdm becomes active before or after execution of the next instruction. note if an attempt is made to activate bdm before being enabled, the cpu resumes normal instruction execution after a brief delay. if bdm is not enabled, any hardware background commands issued are ignored by the bdm and the cpu is not delayed. in active bdm, the bdm registers and standard bdm ?mware lookup table are mapped to addresses 0x7fff00 to 0x7fffff. bdm registers are mapped to addresses 0x7fff00 to 0x7fff0b. the bdm uses these registers which are readable anytime by the bdm. however, these registers are not readable by user programs. 1. bdm is enabled and active immediately out of special single-chip reset. 2. this method is provided by the s12x_dbg module.
background debug module (s12xbdmv2) s12xs family reference manual, rev. 1.10 freescale semiconductor 177 5.4.3 bdm hardware commands hardware commands are used to read and write target system memory locations and to enter active background debug mode. target system memory includes all memory that is accessible by the cpu on the soc which can be on-chip ram, non-volatile memory (e.g. eeprom, flash eeprom), i/o and control registers, and all external memory. hardware commands are executed with minimal or no cpu intervention and do not require the system to be in active bdm for execution, although, they can still be executed in this mode. when executing a hardware command, the bdm sub-block waits for a free bus cycle so that the background access does not disturb the running application program. if a free cycle is not found within 128 clock cycles, the cpu is momentarily frozen so that the bdm can steal a cycle. when the bdm ?ds a free cycle, the operation does not intrude on normal cpu operation provided that it can be completed in a single cycle. however, if an operation requires multiple cycles the cpu is frozen until the operation is complete, even though the bdm found a free cycle. the bdm hardware commands are listed in table 5-6 . the read_bd and write_bd commands allow access to the bdm register locations. these locations are not normally in the system memory map but share addresses with the application in memory. to distinguish between physical memory locations that share the same address, bdm memory resources are enabled just for the read_bd and write_bd access cycle. this allows the bdm to access bdm locations unobtrusively, even if the addresses con?ct with the application memory map. table 5-6. hardware commands command opcode (hex) data description background 90 none enter background mode if ?mware is enabled. if enabled, an ack will be issued when the part enters active background mode. ack_enable d5 none enable handshake. issues an ack pulse after the command is executed. ack_disable d6 none disable handshake. this command does not issue an ack pulse. read_bd_byte e4 16-bit address 16-bit data out read from memory with standard bdm ?mware lookup table in map. odd address data on low byte; even address data on high byte. read_bd_word ec 16-bit address 16-bit data out read from memory with standard bdm ?mware lookup table in map. must be aligned access. read_byte e0 16-bit address 16-bit data out read from memory with standard bdm ?mware lookup table out of map. odd address data on low byte; even address data on high byte. read_word e8 16-bit address 16-bit data out read from memory with standard bdm ?mware lookup table out of map. must be aligned access. write_bd_byte c4 16-bit address 16-bit data in write to memory with standard bdm ?mware lookup table in map. odd address data on low byte; even address data on high byte. write_bd_word cc 16-bit address 16-bit data in write to memory with standard bdm ?mware lookup table in map. must be aligned access. write_byte c0 16-bit address 16-bit data in write to memory with standard bdm ?mware lookup table out of map. odd address data on low byte; even address data on high byte.
background debug module (s12xbdmv2) s12xs family reference manual, rev. 1.10 178 freescale semiconductor 5.4.4 standard bdm firmware commands firmware commands are used to access and manipulate cpu resources. the system must be in active bdm to execute standard bdm ?mware commands, see section 5.4.2, ?nabling and activating bdm . normal instruction execution is suspended while the cpu executes the ?mware located in the standard bdm ?mware lookup table. the hardware command background is the usual way to activate bdm. as the system enters active bdm, the standard bdm ?mware lookup table and bdm registers become visible in the on-chip memory map at 0x7fff00?x7fffff, and the cpu begins executing the standard bdm ?mware. the standard bdm ?mware watches for serial commands and executes them as they are received. the ?mware commands are shown in table 5-7 . write_word c8 16-bit address 16-bit data in write to memory with standard bdm ?mware lookup table out of map. must be aligned access. note: if enabled, ack will occur when data is ready for transmission for all bdm read commands and will occur after the write is complete for all bdm write commands. table 5-6. hardware commands (continued) command opcode (hex) data description
background debug module (s12xbdmv2) s12xs family reference manual, rev. 1.10 freescale semiconductor 179 5.4.5 bdm command structure hardware and ?mware bdm commands start with an 8-bit opcode followed by a 16-bit address and/or a 16-bit data word depending on the command. all the read commands return 16 bits of data despite the byte or word implication in the command name. 8-bit reads return 16-bits of data, of which, only one byte will contain valid data. if reading an even address, the valid data will appear in the msb. if reading an odd address, the valid data will appear in the lsb. table 5-7. firmware commands command 1 1 if enabled, ack will occur when data is ready for transmission for all bdm read commands and will occur after the write is complete for all bdm write commands. opcode (hex) data description read_next 2 2 when the ?mware command read_next or write_next is used to access the bdm address space the bdm resources are accessed rather than user code. writing bdm ?mware is not possible. 62 16-bit data out increment x index register by 2 (x = x + 2), then read word x points to. read_pc 63 16-bit data out read program counter. read_d 64 16-bit data out read d accumulator. read_x 65 16-bit data out read x index register. read_y 66 16-bit data out read y index register. read_sp 67 16-bit data out read stack pointer. write_next

42 16-bit data in increment x index register by 2 (x = x + 2), then write word to location pointed to by x. write_pc 43 16-bit data in write program counter. write_d 44 16-bit data in write d accumulator. write_x 45 16-bit data in write x index register. write_y 46 16-bit data in write y index register. write_sp 47 16-bit data in write stack pointer. go 08 none go to user program. if enabled, ack will occur when leaving active background mode. go_until 3 3 system stop disables the ack function and ignored commands will not have an ack-pulse (e.g., cpu in stop or wait mode). the go_until command will not get an acknowledge if cpu executes the wait or stop instruction before the ?ntil condition (bdm active again) is reached (see section 5.4.7, ?erial interface hardware handshake protocol last note). 0c none go to user program. if enabled, ack will occur upon returning to active background mode. trace1 10 none execute one user instruction then return to active bdm. if enabled, ack will occur upon returning to active background mode. taggo -> go 18 none (previous enable tagging and go to user program.) this command will be deprecated and should not be used anymore. opcode will be executed as a go command.
background debug module (s12xbdmv2) s12xs family reference manual, rev. 1.10 180 freescale semiconductor 16-bit misaligned reads and writes are generally not allowed. if attempted by bdm hardware command, the bdm will ignore the least signi?ant bit of the address and will assume an even address from the remaining bits. for devices with external bus: the following cycle count information is only valid when the external wait function is not used (see wait bit of ebi sub-block). during an external wait the bdm can not steal a cycle. hence be careful with the external wait function if the bdm serial interface is much faster than the bus, because of the bdm soft-reset after time-out (see section 5.4.11, ?erial communication time out ). for hardware data read commands, the external host must wait at least 150 bus clock cycles after sending the address before attempting to obtain the read data. this is to be certain that valid data is available in the bdm shift register, ready to be shifted out. for hardware write commands, the external host must wait 150 bus clock cycles after sending the data to be written before attempting to send a new command. this is to avoid disturbing the bdm shift register before the write has been completed. the 150 bus clock cycle delay in both cases includes the maximum 128 cycle delay that can be incurred as the bdm waits for a free cycle before stealing a cycle. for ?mware read commands, the external host should wait at least 48 bus clock cycles after sending the command opcode and before attempting to obtain the read data. this includes the potential of extra cycles when the access is external and stretched (+1 to maximum +7 cycles) or to registers of the pru (port replacement unit) in emulation modes (if modes available). the 48 cycle wait allows enough time for the requested data to be made available in the bdm shift register, ready to be shifted out. note this timing has increased from previous bdm modules due to the new capability in which the bdm serial interface can potentially run faster than the bus. on previous bdm modules this extra time could be hidden within the serial time. for ?mware write commands, the external host must wait 36 bus clock cycles after sending the data to be written before attempting to send a new command. this is to avoid disturbing the bdm shift register before the write has been completed. the external host should wait at least for 76 bus clock cycles after a trace1 or go command before starting any new serial command. this is to allow the cpu to exit gracefully from the standard bdm ?mware lookup table and resume execution of the user code. disturbing the bdm shift register prematurely may adversely affect the exit from the standard bdm ?mware lookup table. note if the bus rate of the target processor is unknown or could be changing or the external wait function is used, it is recommended that the ack (acknowledge function) is used to indicate when an operation is complete. when using ack, the delay times are automated.
background debug module (s12xbdmv2) s12xs family reference manual, rev. 1.10 freescale semiconductor 181 figure 5-7 represents the bdm command structure. the command blocks illustrate a series of eight bit times starting with a falling edge. the bar across the top of the blocks indicates that the bkgd line idles in the high state. the time for an 8-bit command is 8 16 target clock cycles. 1 figure 5-7. bdm command structure 5.4.6 bdm serial interface the bdm communicates with external devices serially via the bkgd pin. during reset, this pin is a mode select input which selects between normal and special modes of operation. after reset, this pin becomes the dedicated serial interface pin for the bdm. the bdm serial interface is timed using the clock selected by the clksw bit in the status register see section 5.3.2.1, ?dm status register (bdmsts) . this clock will be referred to as the target clock in the following explanation. the bdm serial interface uses a clocking scheme in which the external host generates a falling edge on the bkgd pin to indicate the start of each bit time. this falling edge is sent for every bit whether data is transmitted or received. data is transferred most signi?ant bit (msb) ?st at 16 target clock cycles per bit. the interface times out if 512 clock cycles occur between falling edges from the host. the bkgd pin is a pseudo open-drain pin and has an weak on-chip active pull-up that is enabled at all times. it is assumed that there is an external pull-up and that drivers connected to bkgd do not typically drive the high level. since r-c rise time could be unacceptably long, the target system and host provide brief driven-high (speedup) pulses to drive bkgd to a logic 1. the source of this speedup pulse is the host for transmit cases and the target for receive cases. 1. target clock cycles are cycles measured using the target mcus serial clock rate. see section 5.4.6, ?dm serial interface and section 5.3.2.1, ?dm status register (bdmsts) for information on how serial clock rate is selected. hardware hardware firmware firmware go, 48-bc bc = bus clock cycles command address 150-bc delay next delay 8 bits at ~ 16 tc/bit 16 bits at ~ 16 tc/bit 16 bits at ~ 16 tc/bit command address data next data read write read write trace command next command data 76-bc delay next command 150-bc delay 36-bc delay command command command command data next command tc = target clock cycles
background debug module (s12xbdmv2) s12xs family reference manual, rev. 1.10 182 freescale semiconductor the timing for host-to-target is shown in figure 5-8 and that of target-to-host in figure 5-9 and figure 5-10 . all four cases begin when the host drives the bkgd pin low to generate a falling edge. since the host and target are operating from separate clocks, it can take the target system up to one full clock cycle to recognize this edge. the target measures delays from this perceived start of the bit time while the host measures delays from the point it actually drove bkgd low to start the bit up to one target clock cycle earlier. synchronization between the host and target is established in this manner at the start of every bit time. figure 5-8 shows an external host transmitting a logic 1 and transmitting a logic 0 to the bkgd pin of a target system. the host is asynchronous to the target, so there is up to a one clock-cycle delay from the host-generated falling edge to where the target recognizes this edge as the beginning of the bit time. ten target clock cycles later, the target senses the bit level on the bkgd pin. internal glitch detect logic requires the pin be driven high no later that eight target clock cycles after the falling edge for a logic 1 transmission. since the host drives the high speedup pulses in these two cases, the rising edges look like digitally driven signals. figure 5-8. bdm host-to-target serial bit timing the receive cases are more complicated. figure 5-9 shows the host receiving a logic 1 from the target system. since the host is asynchronous to the target, there is up to one clock-cycle delay from the host- generated falling edge on bkgd to the perceived start of the bit time in the target. the host holds the bkgd pin low long enough for the target to recognize it (at least two target clock cycles). the host must release the low drive before the target drives a brief high speedup pulse seven target clock cycles after the perceived start of the bit time. the host should sample the bit level about 10 target clock cycles after it started the bit time. target senses bit 10 cycles synchronization uncertainty bdm clock (target mcu) host transmit 1 host transmit 0 perceived start of bit time earliest start of next bit
background debug module (s12xbdmv2) s12xs family reference manual, rev. 1.10 freescale semiconductor 183 figure 5-9. bdm target-to-host serial bit timing (logic 1) high-impedance earliest start of next bit r-c rise 10 cycles 10 cycles host samples bkgd pin perceived start of bit time bkgd pin bdm clock (target mcu) host drive to bkgd pin target system speedup pulse high-impedance high-impedance
background debug module (s12xbdmv2) s12xs family reference manual, rev. 1.10 184 freescale semiconductor figure 5-10 shows the host receiving a logic 0 from the target. since the host is asynchronous to the target, there is up to a one clock-cycle delay from the host-generated falling edge on bkgd to the start of the bit time as perceived by the target. the host initiates the bit time but the target ?ishes it. since the target wants the host to receive a logic 0, it drives the bkgd pin low for 13 target clock cycles then brie? drives it high to speed up the rising edge. the host samples the bit level about 10 target clock cycles after starting the bit time. figure 5-10. bdm target-to-host serial bit timing (logic 0) 5.4.7 serial interface hardware handshake protocol bdm commands that require cpu execution are ultimately treated at the mcu bus rate. since the bdm clock source can be asynchronously related to the bus frequency, when clksw = 0, it is very helpful to provide a handshake protocol in which the host could determine when an issued command is executed by the cpu. the alternative is to always wait the amount of time equal to the appropriate number of cycles at the slowest possible rate the clock could be running. this sub-section will describe the hardware handshake protocol. the hardware handshake protocol signals to the host controller when an issued command was successfully executed by the target. this protocol is implemented by a 16 serial clock cycle low pulse followed by a brief speedup pulse in the bkgd pin. this pulse is generated by the target mcu when a command, issued by the host, has been successfully executed (see figure 5-11 ). this pulse is referred to as the ack pulse. after the ack pulse has ?ished: the host can start the bit retrieval if the last issued command was a read command, or start a new command if the last command was a write command or a control command (background, go, go_until or trace1). the ack pulse is not issued earlier than 32 serial clock cycles after the bdm command was issued. the end of the bdm command is assumed to be the 16th tick of the last bit. this minimum delay assures enough time for the host to perceive the ack pulse. note also that, there is no upper limit for the delay between the command and the related ack pulse, since the command execution depends upon the cpu bus frequency, which in some cases could be very slow earliest start of next bit bdm clock (target mcu) host drive to bkgd pin bkgd pin perceived start of bit time 10 cycles 10 cycles host samples bkgd pin target system drive and speedup pulse speedup pulse high-impedance
background debug module (s12xbdmv2) s12xs family reference manual, rev. 1.10 freescale semiconductor 185 compared to the serial communication rate. this protocol allows a great ?xibility for the pod designers, since it does not rely on any accurate time measurement or short response time to any event in the serial communication. figure 5-11. target acknowledge pulse (ack) note if the ack pulse was issued by the target, the host assumes the previous command was executed. if the cpu enters wait or stop prior to executing a hardware command, the ack pulse will not be issued meaning that the bdm command was not executed. after entering wait or stop mode, the bdm command is no longer pending. figure 5-12 shows the ack handshake protocol in a command level timing diagram. the read_byte instruction is used as an example. first, the 8-bit instruction opcode is sent by the host, followed by the address of the memory location to be read. the target bdm decodes the instruction. a bus cycle is grabbed (free or stolen) by the bdm and it executes the read_byte operation. having retrieved the data, the bdm issues an ack pulse to the host controller, indicating that the addressed byte is ready to be retrieved. after detecting the ack pulse, the host initiates the byte retrieval process. note that data is sent in the form of a word and the host needs to determine which is the appropriate byte based on whether the address was odd or even. figure 5-12. handshake protocol at command level 16 cycles bdm clock (target mcu) target transmits ack pulse high-impedance bkgd pin minimum delay from the bdm command 32 cycles earliest start of next bit speedup pulse 16th tick of the last command bit high-impedance read_byte bdm issues the bkgd pin byte address bdm executes the read_byte command host target host target bdm decodes the command ack pulse (out of scale) host target (2) bytes are retrieved new bdm command
background debug module (s12xbdmv2) s12xs family reference manual, rev. 1.10 186 freescale semiconductor differently from the normal bit transfer (where the host initiates the transmission), the serial interface ack handshake pulse is initiated by the target mcu by issuing a negative edge in the bkgd pin. the hardware handshake protocol in figure 5-11 speci?s the timing when the bkgd pin is being driven, so the host should follow this timing constraint in order to avoid the risk of an electrical con?ct in the bkgd pin. note the only place the bkgd pin can have an electrical con?ct is when one side is driving low and the other side is issuing a speedup pulse (high). other ?ighs are pulled rather than driven. however, at low rates the time of the speedup pulse can become lengthy and so the potential con?ct time becomes longer as well. the ack handshake protocol does not support nested ack pulses. if a bdm command is not acknowledge by an ack pulse, the host needs to abort the pending command ?st in order to be able to issue a new bdm command. when the cpu enters wait or stop while the host issues a hardware command (e.g., write_byte), the target discards the incoming command due to the wait or stop being detected. therefore, the command is not acknowledged by the target, which means that the ack pulse will not be issued in this case. after a certain time the host (not aware of stop or wait) should decide to abort any possible pending ack pulse in order to be sure a new command can be issued. therefore, the protocol provides a mechanism in which a command, and its corresponding ack, can be aborted. note the ack pulse does not provide a time out. this means for the go_until command that it can not be distinguished if a stop or wait has been executed (command discarded and ack not issued) or if the ?ntil?condition (bdm active) is just not reached yet. hence in any case where the ack pulse of a command is not issued the possible pending command should be aborted before issuing a new command. see the handshake abort procedure described in section 5.4.8, ?ardware handshake abort procedure . 5.4.8 hardware handshake abort procedure the abort procedure is based on the sync command. in order to abort a command, which had not issued the corresponding ack pulse, the host controller should generate a low pulse in the bkgd pin by driving it low for at least 128 serial clock cycles and then driving it high for one serial clock cycle, providing a speedup pulse. by detecting this long low pulse in the bkgd pin, the target executes the sync protocol, see section 5.4.9, ?ync ?request timed reference pulse , and assumes that the pending command and therefore the related ack pulse, are being aborted. therefore, after the sync protocol has been completed the host is free to issue new bdm commands. for firmware read or write commands it can not be guaranteed that the pending command is aborted when issuing a sync before the corresponding ack pulse. there is a short latency time from the time the read or write access begins until it is ?ished and the corresponding ack pulse is issued. the latency time depends on the ?mware read or write command that is issued and if the serial interface is running on a different clock rate than the bus. when the sync command starts during this latency time the read or write command will not be aborted, but the corresponding ack pulse will be aborted. a pending go, trace1 or
background debug module (s12xbdmv2) s12xs family reference manual, rev. 1.10 freescale semiconductor 187 go_until command can not be aborted. only the corresponding ack pulse can be aborted by the sync command. although it is not recommended, the host could abort a pending bdm command by issuing a low pulse in the bkgd pin shorter than 128 serial clock cycles, which will not be interpreted as the sync command. the ack is actually aborted when a negative edge is perceived by the target in the bkgd pin. the short abort pulse should have at least 4 clock cycles keeping the bkgd pin low, in order to allow the negative edge to be detected by the target. in this case, the target will not execute the sync protocol but the pending command will be aborted along with the ack pulse. the potential problem with this abort procedure is when there is a con?ct between the ack pulse and the short abort pulse. in this case, the target may not perceive the abort pulse. the worst case is when the pending command is a read command (i.e., read_byte). if the abort pulse is not perceived by the target the host will attempt to send a new command after the abort pulse was issued, while the target expects the host to retrieve the accessed memory byte. in this case, host and target will run out of synchronism. however, if the command to be aborted is not a read command the short abort pulse could be used. after a command is aborted the target assumes the next negative edge, after the abort pulse, is the ?st bit of a new bdm command. note the details about the short abort pulse are being provided only as a reference for the reader to better understand the bdm internal behavior. it is not recommended that this procedure be used in a real application. since the host knows the target serial clock frequency, the sync command (used to abort a command) does not need to consider the lower possible target frequency. in this case, the host could issue a sync very close to the 128 serial clock cycles length. providing a small overhead on the pulse length in order to assure the sync pulse will not be misinterpreted by the target. see section 5.4.9, ?ync ?request timed reference pulse . figure 5-13 shows a sync command being issued after a read_byte, which aborts the read_byte command. note that, after the command is aborted a new command could be issued by the host computer. figure 5-13. ack abort procedure at the command level note figure 5-13 does not represent the signals in a true timing scale figure 5-14 shows a con?ct between the ack pulse and the sync request pulse. this con?ct could occur if a pod device is connected to the target bkgd pin and the target is already in debug active mode. read_byte read_status bkgd pin memory address new bdm command new bdm command host target host target host target sync response from the target (out of scale) bdm decode and starts to execute the read_byte command read_byte cmd is aborted by the sync request (out of scale)
background debug module (s12xbdmv2) s12xs family reference manual, rev. 1.10 188 freescale semiconductor consider that the target cpu is executing a pending bdm command at the exact moment the pod is being connected to the bkgd pin. in this case, an ack pulse is issued along with the sync command. in this case, there is an electrical con?ct between the ack speedup pulse and the sync pulse. since this is not a probable situation, the protocol does not prevent this con?ct from happening. figure 5-14. ack pulse and sync request con?ct note this information is being provided so that the mcu integrator will be aware that such a con?ct could eventually occur. the hardware handshake protocol is enabled by the ack_enable and disabled by the ack_disable bdm commands. this provides backwards compatibility with the existing pod devices which are not able to execute the hardware handshake protocol. it also allows for new pod devices, that support the hardware handshake protocol, to freely communicate with the target device. if desired, without the need for waiting for the ack pulse. the commands are described as follows: ack_enable enables the hardware handshake protocol. the target will issue the ack pulse when a cpu command is executed by the cpu. the ack_enable command itself also has the ack pulse as a response. ack_disable disables the ack pulse protocol. in this case, the host needs to use the worst case delay time at the appropriate places in the protocol. the default state of the bdm after reset is hardware handshake protocol disabled. all the read commands will ack (if enabled) when the data bus cycle has completed and the data is then ready for reading out by the bkgd serial pin. all the write commands will ack (if enabled) after the data has been received by the bdm through the bkgd serial pin and when the data bus cycle is complete. see section 5.4.3, ?dm hardware commands and section 5.4.4, ?tandard bdm firmware commands for more information on the bdm commands. bdm clock (target mcu) target mcu drives to bkgd pin bkgd pin 16 cycles speedup pulse high-impedance host drives sync to bkgd pin ack pulse host sync request pulse at least 128 cycles electrical con?ct host and target drive to bkgd pin
background debug module (s12xbdmv2) s12xs family reference manual, rev. 1.10 freescale semiconductor 189 the ack_enable sends an ack pulse when the command has been completed. this feature could be used by the host to evaluate if the target supports the hardware handshake protocol. if an ack pulse is issued in response to this command, the host knows that the target supports the hardware handshake protocol. if the target does not support the hardware handshake protocol the ack pulse is not issued. in this case, the ack_enable command is ignored by the target since it is not recognized as a valid command. the background command will issue an ack pulse when the cpu changes from normal to background mode. the ack pulse related to this command could be aborted using the sync command. the go command will issue an ack pulse when the cpu exits from background mode. the ack pulse related to this command could be aborted using the sync command. the go_until command is equivalent to a go command with exception that the ack pulse, in this case, is issued when the cpu enters into background mode. this command is an alternative to the go command and should be used when the host wants to trace if a breakpoint match occurs and causes the cpu to enter active background mode. note that the ack is issued whenever the cpu enters bdm, which could be caused by a breakpoint match or by a bgnd instruction being executed. the ack pulse related to this command could be aborted using the sync command. the trace1 command has the related ack pulse issued when the cpu enters background active mode after one instruction of the application program is executed. the ack pulse related to this command could be aborted using the sync command. 5.4.9 sync ?request timed reference pulse the sync command is unlike other bdm commands because the host does not necessarily know the correct communication speed to use for bdm communications until after it has analyzed the response to the sync command. to issue a sync command, the host should perform the following steps: 1. drive the bkgd pin low for at least 128 cycles at the lowest possible bdm serial communication frequency (the lowest serial communication frequency is determined by the crystal oscillator or the clock chosen by clksw.) 2. drive bkgd high for a brief speedup pulse to get a fast rise time (this speedup pulse is typically one cycle of the host clock.) 3. remove all drive to the bkgd pin so it reverts to high impedance. 4. listen to the bkgd pin for the sync response pulse. upon detecting the sync request from the host, the target performs the following steps: 1. discards any incomplete command received or bit retrieved. 2. waits for bkgd to return to a logic one. 3. delays 16 cycles to allow the host to stop driving the high speedup pulse. 4. drives bkgd low for 128 cycles at the current bdm serial communication frequency. 5. drives a one-cycle high speedup pulse to force a fast rise time on bkgd. 6. removes all drive to the bkgd pin so it reverts to high impedance. the host measures the low time of this 128 cycle sync response pulse and determines the correct speed for subsequent bdm communications. typically, the host can determine the correct communication speed
background debug module (s12xbdmv2) s12xs family reference manual, rev. 1.10 190 freescale semiconductor within a few percent of the actual target speed and the communication protocol can easily tolerate speed errors of several percent. as soon as the sync request is detected by the target, any partially received command or bit retrieved is discarded. this is referred to as a soft-reset, equivalent to a time-out in the serial communication. after the sync response, the target will consider the next negative edge (issued by the host) as the start of a new bdm command or the start of new sync request. another use of the sync command pulse is to abort a pending ack pulse. the behavior is exactly the same as in a regular sync command. note that one of the possible causes for a command to not be acknowledged by the target is a host-target synchronization problem. in this case, the command may not have been understood by the target and so an ack response pulse will not be issued. 5.4.10 instruction tracing when a trace1 command is issued to the bdm in active bdm, the cpu exits the standard bdm ?mware and executes a single instruction in the user code. once this has occurred, the cpu is forced to return to the standard bdm ?mware and the bdm is active and ready to receive a new command. if the trace1 command is issued again, the next user instruction will be executed. this facilitates stepping or tracing through the user code one instruction at a time. if an interrupt is pending when a trace1 command is issued, the interrupt stacking operation occurs but no user instruction is executed. once back in standard bdm ?mware execution, the program counter points to the ?st instruction in the interrupt service routine. be aware when tracing through the user code that the execution of the user code is done step by step but all peripherals are free running. hence possible timing relations between cpu code execution and occurrence of events of other peripherals no longer exist. do not trace the cpu instruction bgnd used for soft breakpoints. tracing the bgnd instruction will result in a return address pointing to bdm ?mware address space. when tracing through user code which contains stop or wait instructions the following will happen when the stop or wait instruction is traced: the cpu enters stop or wait mode and the trace1 command can not be ?ished before leaving the low power mode. this is the case because bdm active mode can not be entered after cpu executed the stop instruction. however all bdm hardware commands except the background command are operational after tracing a stop or wait instruction and still being in stop or wait mode. if system stop mode is entered (all bus masters are in stop mode) no bdm command is operational. as soon as stop or wait mode is exited the cpu enters bdm active mode and the saved pc value points to the entry of the corresponding interrupt service routine. in case the handshake feature is enabled the corresponding ack pulse of the trace1 command will be discarded when tracing a stop or wait instruction. hence there is no ack pulse when bdm active mode is entered as part of the trace1 command after cpu exited from stop or wait mode. all valid commands sent during cpu being in stop or wait mode or after cpu exited from stop or wait mode will have an ack pulse. the handshake feature becomes disabled only when system
background debug module (s12xbdmv2) s12xs family reference manual, rev. 1.10 freescale semiconductor 191 stop mode has been reached. hence after a system stop mode the handshake feature must be enabled again by sending the ack_enable command. 5.4.11 serial communication time out the host initiates a host-to-target serial transmission by generating a falling edge on the bkgd pin. if bkgd is kept low for more than 128 target clock cycles, the target understands that a sync command was issued. in this case, the target will keep waiting for a rising edge on bkgd in order to answer the sync request pulse. if the rising edge is not detected, the target will keep waiting forever without any time-out limit. consider now the case where the host returns bkgd to logic one before 128 cycles. this is interpreted as a valid bit transmission, and not as a sync request. the target will keep waiting for another falling edge marking the start of a new bit. if, however, a new falling edge is not detected by the target within 512 clock cycles since the last falling edge, a time-out occurs and the current command is discarded without affecting memory or the operating mode of the mcu. this is referred to as a soft-reset. if a read command is issued but the data is not retrieved within 512 serial clock cycles, a soft-reset will occur causing the command to be disregarded. the data is not available for retrieval after the time-out has occurred. this is the expected behavior if the handshake protocol is not enabled. however, consider the behavior where the bdm is running in a frequency much greater than the cpu frequency. in this case, the command could time out before the data is ready to be retrieved. in order to allow the data to be retrieved even with a large clock frequency mismatch (between bdm and cpu) when the hardware handshake protocol is enabled, the time out between a read command and the data retrieval is disabled. therefore, the host could wait for more then 512 serial clock cycles and still be able to retrieve the data from an issued read command. however, once the handshake pulse (ack pulse) is issued, the time-out feature is re- activated, meaning that the target will time out after 512 clock cycles. therefore, the host needs to retrieve the data within a 512 serial clock cycles time frame after the ack pulse had been issued. after that period, the read command is discarded and the data is no longer available for retrieval. any negative edge in the bkgd pin after the time-out period is considered to be a new command or a sync request. note that whenever a partially issued command, or partially retrieved data, has occurred the time out in the serial communication is active. this means that if a time frame higher than 512 serial clock cycles is observed between two consecutive negative edges and the command being issued or data being retrieved is not complete, a soft-reset will occur causing the partially received command or data retrieved to be disregarded. the next negative edge in the bkgd pin, after a soft-reset has occurred, is considered by the target as the start of a new bdm command, or the start of a sync request pulse.
background debug module (s12xbdmv2) s12xs family reference manual, rev. 1.10 192 freescale semiconductor
s12xs family reference manual, rev. 1.10 freescale semiconductor 193 chapter 6 s12x debug (s12xdbgv3) module table 6-1. revision history 6.1 introduction the s12xdbg module provides an on-chip trace buffer with ?xible triggering capability to allow non- intrusive debug of application software. the s12xdbg module is optimized for the s12x 16-bit architecture and allows debugging of cpu12x module operations. typically the s12xdbg module is used in conjunction with the s12xbdm module, whereby the user con?ures the s12xdbg module for a debugging session over the bdm interface. once con?ured the s12xdbg module is armed and the device leaves bdm mode returning control to the user program, which is then monitored by the s12xdbg module. alternatively the s12xdbg module can be con?ured over a serial interface using swi routines. 6.1.1 glossary revision number revision date sections affected description of changes v03.20 14 sep 2007 6.3.2.7/6-203 - clari?d reserved state sequencer encodings. v03.21 23 oct 2007 6.4.2.2/6-216 6.4.2.4/6-217 - added single databyte comparison limitation information - added statement about interrupt vector fetches whilst tagging. v03.22 12 nov 2007 6.4.5.2/6-221 6.4.5.5/6-225 - removed loop1 tracing restriction note. - added pin reset effect note. v03.23 13 nov 2007 general - text readability improved, typo removed. v03.24 04 jan 2008 6.4.5.3/6-223 - corrected bit name. v03.25 14 may 2008 - updated revision history table format. corrected other paragraph formats. table 6-2. glossary of terms term de?ition cof change of flow. change in the program ?w due to a conditional branch, indexed jump or interrupt bdm background debug mode dug device user guide, describing the features of the device into which the dbg is integrated word 16 bit data entity data line 64 bit data entity
s12x debug (s12xdbgv3) module s12xs family reference manual, rev. 1.10 194 freescale semiconductor 6.1.2 overview the comparators monitor the bus activity of the cpu12x. when a match occurs the control logic can trigger the state sequencer to a new state. on a transition to the final state, bus tracing is triggered and/or a breakpoint can be generated. independent of comparator matches a transition to final state with associated tracing and breakpoint can be triggered by writing to the trig control bit. the trace buffer is visible through a 2-byte window in the register address map and can be read out using standard 16-bit word reads. tracing is disabled when the mcu system is secured. 6.1.3 features four comparators (a, b, c, and d) comparators a and c compare the full address bus and full 16-bit data bus comparators a and c feature a data bus mask register comparators b and d compare the full address bus only each comparator can be con?ured to monitor cpu12x buses each comparator features selection of read or write access cycles comparators b and d allow selection of byte or word access cycles comparisons can be used as triggers for the state sequencer three comparator modes simple address/data comparator match mode inside address range mode, addmin address addmax outside address range match mode, address < addmin or address > addmax two types of triggers tagged ?this triggers just before a speci? instruction begins execution force ?this triggers on the ?st instruction boundary after a match occurs. the following types of breakpoints cpu12x breakpoint entering bdm on breakpoint (bdm) cpu12x breakpoint executing swi on breakpoint (swi) trig immediate software trigger independent of comparators four trace modes normal: change of ?w (cof) pc information is stored (see section 6.4.5.2.1 ) for change of ?w de?ition. cpu cpu12x module tag tags can be attached to cpu opcodes as they enter the instruction pipe. if the tagged opcode reaches the execution stage a tag hit occurs. table 6-2. glossary of terms (continued) term de?ition
s12x debug (s12xdbgv3) module s12xs family reference manual, rev. 1.10 freescale semiconductor 195 loop1: same as normal but inhibits consecutive duplicate source address entries detail: address and data for all cycles except free cycles and opcode fetches are stored pure pc: all program counter addresses are stored. 4-stage state sequencer for trace buffer control tracing session trigger linked to final state of state sequencer begin, end, and mid alignment of tracing to trigger 6.1.4 modes of operation the s12xdbg module can be used in all mcu functional modes. during bdm hardware accesses and whilst the bdm module is active, cpu12x monitoring is disabled. thus breakpoints, comparators, and cpu12x bus tracing are disabled . when the cpu12x enters active bdm mode through a background command, with the s12xdbg module armed, the s12xdbg remains armed. the s12xdbg module tracing is disabled if the mcu is secure. however, breakpoints can still be generated if the mcu is secure. table 6-3. mode dependent restriction summary bdm enable bdm active mcu secure comparator matches enabled breakpoints possible tagging possible tracing possible x x 1 yes yes yes no 0 0 0 yes only swi yes yes 0 1 0 active bdm not possible when not enabled 1 0 0 yes yes yes yes 110 no no no no
s12x debug (s12xdbgv3) module s12xs family reference manual, rev. 1.10 196 freescale semiconductor 6.1.5 block diagram figure 6-1. debug module block diagram 6.2 external signal description the s12xdbg sub-module features no external signals. 6.3 memory map and registers 6.3.1 module memory map a summary of the registers associated with the s12xdbg sub-block is shown in table 6-2 . detailed descriptions of the registers and bits are given in the subsections that follow. address name bit 7 6 5 4 3 2 1 bit 0 0x0020 dbgc1 r arm 0 reserved bdm dbgbrk reserved comrv w trig 0x0021 dbgsr r tbf 0 0 0 0 ssf2 ssf1 ssf0 w 0x0022 dbgtcr r reserved tsource trange trcmod talign w 0x0023 dbgc2 r0000 cdcm abcm w figure 6-2. quick reference to s12xdbg registers s12xcpu bus trace buffer bus interface trigger match0 state comparator b comparator c comparator d comparator a state sequencer match1 match2 match3 trace read trace data (dbg read data bus) control secure breakpoint requests comparator match control trigger tag & trigger control logic tag s taghits state s12xcpu
s12x debug (s12xdbgv3) module s12xs family reference manual, rev. 1.10 freescale semiconductor 197 6.3.2 register descriptions this section consists of the s12xdbg control and trace buffer register descriptions in address order. each comparator has a bank of registers that are visible through an 8-byte window between 0x0028 and 0x002f in the s12xdbg module register address map. when arm is set in dbgc1, the only bits in the s12xdbg module registers that can be written are arm, trig, and comrv[1:0] 0x0024 dbgtbh r bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 w 0x0025 dbgtbl r bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 w 0x0026 dbgcnt r 0 cnt w 0x0027 dbgscrx r0000 sc3 sc2 sc1 sc0 w 0x0027 dbgmfr r 0 0 0 0 mc3 mc2 mc1 mc0 w 0x0028 1 dbgxctl (compa/c) r0 ndb tag brk rw rwe reserved compe w 0x0028 2 dbgxctl (compb/d) r sze sz tag brk rw rwe reserved compe w 0x0029 dbgxah r0 bit 22 21 20 19 18 17 bit 16 w 0x002a dbgxam r bit 15 14 13 12 11 10 9 bit 8 w 0x002b dbgxal r bit 7 6 5 4 3 2 1 bit 0 w 0x002c dbgxdh r bit 15 14 13 12 11 10 9 bit 8 w 0x002d dbgxdl r bit 7 6 5 4 3 2 1 bit 0 w 0x002e dbgxdhm r bit 15 14 13 12 11 10 9 bit 8 w 0x002f dbgxdlm r bit 7 6 5 4 3 2 1 bit 0 w 1 this represents the contents if the comparator a or c control register is blended into this address. 2 this represents the contents if the comparator b or d control register is blended into this address address name bit 7 6 5 4 3 2 1 bit 0 figure 6-2. quick reference to s12xdbg registers
s12x debug (s12xdbgv3) module s12xs family reference manual, rev. 1.10 198 freescale semiconductor 6.3.2.1 debug control register 1 (dbgc1) read: anytime write: bits 7, 1, 0 anytime bit 6 can be written anytime but always reads back as 0. bits 5:2 anytime s12xdbg is not armed. note if a write access to dbgc1 with the arm bit position set occurs simultaneously to a hardware disarm from an internal trigger event, then the arm bit is cleared due to the hardware disarm. note when disarming the s12xdbg by clearing arm with software, the contents of bits[5:2] are not affected by the write, since up until the write operation, arm = 1 preventing these bits from being written. these bits must be cleared using a second write if required. address: 0x0020 76543210 r arm 0 reserved bdm dbgbrk reserved comrv w trig reset 00000000 figure 6-3. debug control register (dbgc1) table 6-4. dbgc1 field descriptions field description 7 arm arm bit ?the arm bit controls whether the s12xdbg module is armed. this bit can be set and cleared by user software and is automatically cleared on completion of a tracing session, or if a breakpoint is generated with tracing not enabled. on setting this bit the state sequencer enters state1. 0 debugger disarmed 1 debugger armed 6 trig immediate trigger request bit ?this bit when written to 1 requests an immediate trigger independent of comparator signal status. when tracing is complete a forced breakpoint may be generated depending upon dbgbrk and bdm bit settings. this bit always reads back a 0. writing a 0 to this bit has no effect. if tsource is clear no tracing is carried out. if tracing has already commenced using begin- or mid trigger alignment, it continues until the end of the tracing session as de?ed by the talign bit settings, thus trig has no affect. in secure mode tracing is disabled and writing to this bit has no effect. 0 do not trigger until the state sequencer enters the final state. 1 trigger immediately . 5 reserved this bit is reserved, setting it has no meaning or effect. 4 bdm background debug mode enable ?this bit determines if an s12x breakpoint causes the system to enter background debug mode (bdm) or initiate a software interrupt (swi). if this bit is set but the bdm is not enabled by the enbdm bit in the bdm module, then breakpoints default to swi. 0 breakpoint to software interrupt if bdm inactive. otherwise no breakpoint. 1 breakpoint to bdm, if bdm enabled. otherwise breakpoint to swi
s12x debug (s12xdbgv3) module s12xs family reference manual, rev. 1.10 freescale semiconductor 199 6.3.2.2 debug status register (dbgsr) read: anytime write: never 3 dbgbrk s12xdbg breakpoint enable bit the dbgbrk bit controls whether the debugger will request a breakpoint to s12xcpu upon reaching the state sequencer final state. if tracing is enabled, the breakpoint is generated on completion of the tracing session. if tracing is not enabled, the breakpoint is generated immediately. please refer to section 6.4.7 for further details. 0 no breakpoint on trigger. 1 breakpoint on trigger 1? comrv comparator register visibility bits these bits determine which bank of comparator register is visible in the 8-byte window of the s12xdbg module address map, located between 0x0028 to 0x002f. furthermore these bits determine which register is visible at the address 0x0027. see table 6-5 . table 6-5. comrv encoding comrv visible comparator visible register at 0x0027 00 comparator a dbgscr1 01 comparator b dbgscr2 10 comparator c dbgscr3 11 comparator d dbgmfr address: 0x0021 76543210 r tbf 0 0 0 0 ssf2 ssf1 ssf0 w reset por 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 = unimplemented or reserved figure 6-4. debug status register (dbgsr) table 6-6. dbgsr field descriptions field description 7 tbf trace buffer full the tbf bit indicates that the trace buffer has stored 64 or more lines of data since it was last armed. if this bit is set, then all 64 lines will be valid data, regardless of the value of dbgcnt bits cnt[6:0]. the tbf bit is cleared when arm in dbgc1 is written to a one. the tbf is cleared by the power on reset initialization. other system generated resets have no affect on this bit 2? ssf[2:0] state sequencer flag bits the ssf bits indicate in which state the state sequencer is currently in. during a debug session on each transition to a new state these bits are updated. if the debug session is ended by software clearing the arm bit, then these bits retain their value to re?ct the last state of the state sequencer before disarming. if a debug session is ended by an internal trigger, then the state sequencer returns to state0 and these bits are cleared to indicate that state0 was entered during the session. on arming the module the state sequencer enters state1 and these bits are forced to ssf[2:0] = 001. see table 6-7 . table 6-4. dbgc1 field descriptions (continued) field description
s12x debug (s12xdbgv3) module s12xs family reference manual, rev. 1.10 200 freescale semiconductor 6.3.2.3 debug trace control register (dbgtcr) read: anytime write: bits 7:6 only when s12xdbg is neither secure nor armed. bits 5:0 anytime the module is disarmed. warning dbgtcr[7] is reserved. setting this bit maps the tracing to an unimplemented bus, thus preventing proper operation. table 6-7. ssf[2:0] ?state sequence flag bit encoding ssf[2:0] current state 000 state0 (disarmed) 001 state1 010 state2 011 state3 100 final state 101,110,111 reserved address: 0x0022 76543210 r reserved tsource trange trcmod talign w reset 00000000 figure 6-5. debug trace control register (dbgtcr) table 6-8. dbgtcr field descriptions field description 6 tsource trace source control bits the tsource enables the tracing session. if the mcu system is secured, this bit cannot be set and tracing is inhibited. 0 no tracing selected 1 tracing selected 5? trange trace range bits the trange bits allow ?tering of trace information from a selected address range when tracing from the cpu12x in detail mode. to use a comparator for range ?tering, the corresponding compe bits must remain cleared. if the compe bit is not clear then the comparator will also be used to generate state sequence triggers. see table 6-9 . 3? trcmod trace mode bits see section 6.4.5.2 for detailed trace mode descriptions. in normal mode, change of ?w information is stored. in loop1 mode, change of ?w information is stored but redundant entries into trace memory are inhibited. in detail mode, address and data for all memory and register accesses is stored. see table 6-10 . 1? talign trigger align bits ?these bits control whether the trigger is aligned to the beginning, end or the middle of a tracing session. see table 6-11 .
s12x debug (s12xdbgv3) module s12xs family reference manual, rev. 1.10 freescale semiconductor 201 6.3.2.4 debug control register2 (dbgc2) read: anytime write: anytime the module is disarmed. this register con?ures the comparators for range matching. table 6-9. trange trace range encoding trange tracing range 00 trace from all addresses (no ?ter) 01 trace only in address range from $00000 to comparator d 10 trace only in address range from comparator c to $7fffff 11 trace only in range from comparator c to comparator d table 6-10. trcmod trace mode bit encoding trcmod description 00 normal 01 loop1 10 detail 11 pure pc table 6-11. talign trace alignment encoding talign description 00 trigger at end of stored data 01 trigger before storing data 10 trace buffer entries before and after trigger 11 reserved address: 0x0023 76543210 r0000 cdcm abcm w reset 00000000 = unimplemented or reserved figure 6-6. debug control register2 (dbgc2) table 6-12. dbgc2 field descriptions field description 3? cdcm[1:0] c and d comparator match control ?these bits determine the c and d comparator match mapping as described in table 6-13 . 1? abcm[1:0] a and b comparator match control ?these bits determine the a and b comparator match mapping as described in table 6-14 .
s12x debug (s12xdbgv3) module s12xs family reference manual, rev. 1.10 202 freescale semiconductor 6.3.2.5 debug trace buffer register (dbgtbh:dbgtbl) read: only when unlocked and not secured and not armed and with the tsource bit set. write: aligned word writes when disarmed unlock the trace buffer for reading but do not affect trace buffer contents. table 6-13. cdcm encoding cdcm description 00 match2 mapped to comparator c match....... match3 mapped to comparator d match. 01 match2 mapped to comparator c/d inside range....... match3 disabled. 10 match2 mapped to comparator c/d outside range....... match3 disabled. 11 reserved 1 1 currently defaults to match2 mapped to comparator c : match3 mapped to comparator d table 6-14. abcm encoding abcm description 00 match0 mapped to comparator a match....... match1 mapped to comparator b match. 01 match 0 mapped to comparator a/b inside range....... match1 disabled. 10 match 0 mapped to comparator a/b outside range....... match1 disabled. 11 reserved 1 1 currently defaults to match0 mapped to comparator a : match1 mapped to comparator b address: 0x0024, 0x0025 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 w porxxxxxxxxxxxxxxxx other resets figure 6-7. debug trace buffer register (dbgtb) table 6-15. dbgtb field descriptions field description 15? bit[15:0] trace buffer data bits the trace buffer register is a window through which the 64-bit wide data lines of the trace buffer may be read 16 bits at a time. each valid read of dbgtb increments an internal trace buffer pointer which points to the next address to be read. when the arm bit is written to 1 the trace buffer is locked to prevent reading. the trace buffer can only be unlocked for reading by writing to dbgtb with an aligned word write when the module is disarmed. the dbgtb register can be read only as an aligned word, any byte reads or misaligned access of these registers will return 0 and will not cause the trace buffer pointer to increment to the next trace buffer address. the same is true for word reads while the debugger is armed. the por state is unde?ed other resets do not affect the trace buffer contents. .
s12x debug (s12xdbgv3) module s12xs family reference manual, rev. 1.10 freescale semiconductor 203 6.3.2.6 debug count register (dbgcnt) read: anytime write: never 6.3.2.7 debug state control registers there is a dedicated control register for each of the state sequencer states 1 to 3 that determines if transitions from that state are allowed, depending upon comparator matches or tag hits, and de?es the address: 0x0026 76543210 r 0 cnt w reset por 0 0 0 0 0 0 0 0 0 = unimplemented or reserved figure 6-8. debug count register (dbgcnt) table 6-16. dbgcnt field descriptions field description 6? cnt[6:0] count value the cnt bits [6:0] indicate the number of valid data 64-bit data lines stored in the trace buffer. table 6-17 shows the correlation between the cnt bits and the number of valid data lines in the trace buffer. when the cnt rolls over to zero, the tbf bit in dbgsr is set and incrementing of cnt will continue in end- trigger or mid-trigger mode. the dbgcnt register is cleared when arm in dbgc1 is written to a one. the dbgcnt register is cleared by power-on-reset initialization but is not cleared by other system resets. thus should a reset occur during a debug session, the dbgcnt register still indicates after the reset, the number of valid trace buffer entries stored before the reset occurred. the dbgcnt register is not decremented when reading from the trace buffer. table 6-17. cnt decoding table tbf (dbgsr) cnt[6:0] description 0 0000000 no data valid 0 0000001 32 bits of one line valid 0 0000010 0000100 0000110 .. 1111100 1 line valid 2 lines valid 3 lines valid .. 62 lines valid 0 1111110 63 lines valid 1 0000000 64 lines valid; if using begin trigger alignment, arm bit will be cleared and the tracing session ends. 1 0000010 .. .. 1111110 64 lines valid, oldest data has been overwritten by most recent data
s12x debug (s12xdbgv3) module s12xs family reference manual, rev. 1.10 204 freescale semiconductor next state for the state sequencer following a match. the three debug state control registers are located at the same address in the register address map (0x0027). each register can be accessed using the comrv bits in dbgc1 to blend in the required register. the comrv = 11 value blends in the match ?g register (dbgmfr). 6.3.2.7.1 debug state control register 1 (dbgscr1) read: if comrv[1:0] = 00 write: if comrv[1:0] = 00 and s12xdbg is not armed. this register is visible at 0x0027 only with comrv[1:0] = 00. the state control register 1 selects the targeted next state whilst in state1. the matches refer to the match channels of the comparator match control logic as depicted in figure 6-1 and described in section 6.3.2.8.1 . comparators must be enabled by setting the comparator enable bit in the associated dbgxctl control register. table 6-18. state control register access encoding comrv visible state control register 00 dbgscr1 01 dbgscr2 10 dbgscr3 11 dbgmfr address: 0x0027 76543210 r0000 sc3 sc2 sc1 sc0 w reset 00000000 = unimplemented or reserved figure 6-9. debug state control register 1 (dbgscr1) table 6-19. dbgscr1 field descriptions field description 3? sc[3:0] these bits select the targeted next state whilst in state1, based upon the match event. table 6-20. state1 sequencer next state selection sc[3:0] description 0000 any match triggers to state2 0001 any match triggers to state3 0010 any match triggers to final state 0011 match2 triggers to state2....... other matches have no effect 0100 match2 triggers to state3....... other matches have no effect 0101 match2 triggers to final state....... other matches have no effect 0110 match0 triggers to state2....... match1 triggers to state3....... other matches have no effect
s12x debug (s12xdbgv3) module s12xs family reference manual, rev. 1.10 freescale semiconductor 205 the trigger priorities described in table 6-39 dictate that in the case of simultaneous matches, the match on the lower channel number (0,1,2,3) has priority. the sc[3:0] encoding ensures that a match leading to ?al state has priority over all other matches. 6.3.2.7.2 debug state control register 2 (dbgscr2) read: if comrv[1:0] = 01 write: if comrv[1:0] = 01 and s12xdbg is not armed. this register is visible at 0x0027 only with comrv[1:0] = 01. the state control register 2 selects the targeted next state whilst in state2. the matches refer to the match channels of the comparator match control logic as depicted in figure 6-1 and described in section 6.3.2.8.1 . comparators must be enabled by setting the comparator enable bit in the associated dbgxctl control register. 0111 match1 triggers to state3....... match0 triggers final state....... other matches have no effect 1000 match0 triggers to state2....... match2 triggers to state3....... other matches have no effect 1001 match2 triggers to state3....... match0 triggers final state....... other matches have no effect 1010 match1 triggers to state2....... match3 triggers to state3....... other matches have no effect 1011 match3 triggers to state3....... match1 triggers to final state....... other matches have no effect 1100 match3 has no effect....... all other matches (m0,m1,m2) trigger to state2 1101 reserved. (no match triggers state sequencer transition) 1110 reserved. (no match triggers state sequencer transition) 1111 reserved. (no match triggers state sequencer transition) address: 0x0027 76543210 r0000 sc3 sc2 sc1 sc0 w reset 00000000 = unimplemented or reserved figure 6-10. debug state control register 2 (dbgscr2) table 6-21. dbgscr2 field descriptions field description 3? sc[3:0] these bits select the targeted next state whilst in state2, based upon the match event. table 6-22. state2 ?equencer next state selection sc[3:0] description 0000 any match triggers to state1 0001 any match triggers to state3 0010 any match triggers to final state 0011 match3 triggers to state1....... other matches have no effect 0100 match3 triggers to state3....... other matches have no effect table 6-20. state1 sequencer next state selection (continued) sc[3:0] description
s12x debug (s12xdbgv3) module s12xs family reference manual, rev. 1.10 206 freescale semiconductor the trigger priorities described in table 6-39 dictate that in the case of simultaneous matches, the match on the lower channel number (0,1,2,3) has priority. the sc[3:0] encoding ensures that a match leading to ?al state has priority over all other matches. 6.3.2.7.3 debug state control register 3 (dbgscr3) read: if comrv[1:0] = 10 write: if comrv[1:0] = 10 and s12xdbg is not armed. this register is visible at 0x0027 only with comrv[1:0] = 10. the state control register three selects the targeted next state whilst in state3. the matches refer to the match channels of the comparator match control logic as depicted in figure 6-1 and described in section 6.3.2.8.1 . comparators must be enabled by setting the comparator enable bit in the associated dbgxctl control register. 0101 match3 triggers to final state....... other matches have no effect 0110 match0 triggers to state1....... match1 triggers to state3....... other matches have no effect 0111 match1 triggers to state3....... match0 triggers final state....... other matches have no effect 1000 match0 triggers to state1....... match2 triggers to state3....... other matches have no effect 1001 match2 triggers to state3....... match0 triggers final state....... other matches have no effect 1010 match1 triggers to state1....... match3 triggers to state3....... other matches have no effect 1011 match3 triggers to state3....... match1 triggers final state....... other matches have no effect 1100 match2 triggers to state1..... match3 trigger to final state 1101 match2 has no affect, all other matches (m0,m1,m3) trigger to final state 1110 reserved. (no match triggers state sequencer transition) 1111 reserved. (no match triggers state sequencer transition) address: 0x0027 76543210 r0000 sc3 sc2 sc1 sc0 w reset 00000000 = unimplemented or reserved figure 6-11. debug state control register 3 (dbgscr3) table 6-23. dbgscr3 field descriptions field description 3? sc[3:0] these bits select the targeted next state whilst in state3, based upon the match event. table 6-24. state3 ?sequencer next state selection sc[3:0] description 0000 any match triggers to state1 0001 any match triggers to state2 table 6-22. state2 ?equencer next state selection (continued) sc[3:0] description
s12x debug (s12xdbgv3) module s12xs family reference manual, rev. 1.10 freescale semiconductor 207 the trigger priorities described in table 6-39 dictate that in the case of simultaneous matches, the match on the lower channel number (0,1,2,3) has priority. the sc[3:0] encoding ensures that a match leading to final state has priority over all other matches. 6.3.2.7.4 debug match flag register (dbgmfr) read: if comrv[1:0] = 11 write: never dbgmfr is visible at 0x0027 only with comrv[1:0] = 11. it features four ?g bits each mapped directly to a channel. should a match occur on the channel during the debug session, then the corresponding ?g is set and remains set until the next time the module is armed by writing to the arm bit. thus the contents are retained after a debug session for evaluation purposes. these ?gs cannot be cleared by software, they are cleared only when arming the module. a set ?g does not inhibit the setting of other ?gs. once a ?g is set, further triggers on the same channel have no affect. 6.3.2.8 comparator register descriptions each comparator has a bank of registers that are visible through an 8-byte window in the s12xdbg module register address map. comparators a and c consist of 8 register bytes (3 address bus compare registers, two data bus compare registers, two data bus mask registers and a control register). 0010 any match triggers to final state 0011 match0 triggers to state1....... other matches have no effect 0100 match0 triggers to state2....... other matches have no effect 0101 match0 triggers to final state.......match1 triggers to state1...other matches have no effect 0110 match1 triggers to state1....... other matches have no effect 0111 match1 triggers to state2....... other matches have no effect 1000 match1 triggers to final state....... other matches have no effect 1001 match2 triggers to state2....... match0 triggers to final state....... other matches have no effect 1010 match1 triggers to state1....... match3 triggers to state2....... other matches have no effect 1011 match3 triggers to state2....... match1 triggers to final state....... other matches have no effect 1100 match2 triggers to final state....... other matches have no effect 1101 match3 triggers to final state....... other matches have no effect 1110 reserved. (no match triggers state sequencer transition) 1111 reserved. (no match triggers state sequencer transition) address: 0x0027 76543210 r0000mc3mc2mc1mc0 w reset 00000000 = unimplemented or reserved figure 6-12. debug match flag register (dbgmfr) table 6-24. state3 ?sequencer next state selection sc[3:0] description
s12x debug (s12xdbgv3) module s12xs family reference manual, rev. 1.10 208 freescale semiconductor comparators b and d consist of four register bytes (three address bus compare registers and a control register). each set of comparator registers is accessible in the same 8-byte window of the register address map and can be accessed using the comrv bits in the dbgc1 register. if the comparators b or d are accessed through the 8-byte window, then only the address and control bytes are visible, the 4 bytes associated with data bus and data bus masking read as zero and cannot be written. furthermore the control registers for comparators b and d differ from those of comparators a and c. 6.3.2.8.1 debug comparator control register (dbgxctl) the contents of this register bits 7 and 6 differ depending upon which comparator registers are visible in the 8-byte window of the dbg module register address map. read: anytime. see table 6-26 for visible register encoding. write: if dbg not armed. see table 6-26 for visible register encoding. warning dbgxctl[1] is reserved. setting this bit maps the corresponding comparator to an table 6-25. comparator register layout 0x0028 control read/write comparators a,b,c,d 0x0029 address high read/write comparators a,b,c,d 0x002a address medium read/write comparators a,b,c,d 0x002b address low read/write comparators a,b,c,d 0x002c data high comparator read/write comparator a and c only 0x002d data low comparator read/write comparator a and c only 0x002e data high mask read/write comparator a and c only 0x002f data low mask read/write comparator a and c only address: 0x0028 76543210 r0 ndb tag brk rw rwe reserved compe w reset 00000000 = unimplemented or reserved figure 6-13. debug comparator control register (comparators a and c) address: 0x0028 76543210 r sze sz tag brk rw rwe reserved compe w reset 00000000 figure 6-14. debug comparator control register (comparators b and d)
s12x debug (s12xdbgv3) module s12xs family reference manual, rev. 1.10 freescale semiconductor 209 unimplemented bus, thus preventing proper operation. the dbgc1_comrv bits determine which comparator control, address, data and datamask registers are visible in the 8-byte window from 0x0028 to 0x002f as shown in section table 6-26. table 6-26. comparator address register visibility comrv visible comparator 00 dbgactl, dbgaah ,dbgaam, dbgaal, dbgadh, dbgadl, dbgadhm, dbgadlm 01 dbgbctl, dbgbah, dbgbam, dbgbal 10 dbgcctl, dbgcah, dbgcam, dbgcal, dbgcdh, dbgcdl, dbgcdhm, dbgcdlm 11 dbgdctl, dbgdah, dbgdam, dbgdal table 6-27. dbgxctl field descriptions field description 7 sze (comparators b and d) size comparator enable bit ?the sze bit controls whether access size comparison is enabled for the associated comparator. this bit is ignored if the tag bit in the same register is set. 0 word/byte access size is not used in comparison 1 word/byte access size is used in comparison 6 ndb (comparators a and c not data bus the ndb bit controls whether the match occurs when the data bus matches the comparator register value or when the data bus differs from the register value. furthermore data bus bits can be individually masked using the comparator data mask registers. this bit is only available for comparators a and c. this bit is ignored if the tag bit in the same register is set. this bit position has an sz functionality for comparators b and d. 0 match on data bus equivalence to comparator register contents 1 match on data bus difference to comparator register contents 6 sz (comparators b and d) size comparator value bit ?the sz bit selects either word or byte access size in comparison for the associated comparator. this bit is ignored if the sze bit is cleared or if the tag bit in the same register is set. this bit position has ndb functionality for comparators a and c 0 word access size will be compared 1 byte access size will be compared 5 tag tag select ?this bit controls whether the comparator match will cause a trigger or tag the opcode at the matched address. tagged opcodes trigger only if they reach the execution stage of the instruction queue. 0 trigger immediately on match 1 on match, tag the opcode. if the opcode is about to be executed a trigger is generated 4 brk break ?this bit controls whether a channel match terminates a debug session immediately, independent of state sequencer state. to generate an immediate breakpoint the module breakpoints must be enabled using dbgbrk. 0 the debug session termination is dependent upon the state sequencer and trigger conditions. 1 a match on this channel terminates the debug session immediately; breakpoints if active are generated, tracing, if active, is terminated and the module disarmed. 3 rw read/write comparator value bit the rw bit controls whether read or write is used in compare for the associated comparator . the rw bit is not used if rwe = 0. 0 write cycle will be matched 1 read cycle will be matched 2 rwe read/write enable bit ?the rwe bit controls whether read or write comparison is enabled for the associated comparator. this bit is not used for tagged operations. 0 read/write is not used in comparison 1 read/write is used in comparison
s12x debug (s12xdbgv3) module s12xs family reference manual, rev. 1.10 210 freescale semiconductor table 6-28 shows the effect for rwe and rw on the comparison conditions. these bits are not useful for tagged operations since the trigger occurs based on the tagged opcode reaching the execution stage of the instruction queue. thus these bits are ignored if tagged triggering is selected. 6.3.2.8.2 debug comparator address high register (dbgxah) read: anytime. see table 6-26 for visible register encoding. write: if dbg not armed. see table 6-26 for visible register encoding. 0 compe determines if comparator is enabled 0 the comparator is not enabled 1 the comparator is enabled for state sequence triggers or tag generation table 6-28. read or write comparison logic table rwe bit rw bit rw signal comment 0 x 0 rw not used in comparison 0 x 1 rw not used in comparison 1 0 0 write 1 0 1 no match 1 1 0 no match 1 1 1 read address: 0x0029 76543210 r0 bit 22 bit 21 bit 20 bit 19 bit 18 bit 17 bit 16 w reset 00000000 = unimplemented or reserved figure 6-15. debug comparator address high register (dbgxah) table 6-29. dbgxah field descriptions field description 6? bit[22:16] comparator address high compare bits the comparator address high compare bits control whether the selected comparator will compare the address bus bits [22:16] to a logic one or logic zero. . 0 compare corresponding address bit to a logic zero 1 compare corresponding address bit to a logic one table 6-27. dbgxctl field descriptions (continued) field description
s12x debug (s12xdbgv3) module s12xs family reference manual, rev. 1.10 freescale semiconductor 211 6.3.2.8.3 debug comparator address mid register (dbgxam) read: anytime. see table 6-26 for visible register encoding. write: if dbg not armed. see table 6-26 for visible register encoding. 6.3.2.8.4 debug comparator address low register (dbgxal) read: anytime. see table 6-26 for visible register encoding. write: if dbg not armed. see table 6-26 for visible register encoding. address: 0x002a 76543210 r bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 w reset 00000000 figure 6-16. debug comparator address mid register (dbgxam) table 6-30. dbgxam field descriptions field description 7? bit[15:8] comparator address mid compare bits ?the comparator address mid compare bits control whether the selected comparator will compare the address bus bits [15:8] to a logic one or logic zero. 0 compare corresponding address bit to a logic zero 1 compare corresponding address bit to a logic one address: 0x002b 76543210 r bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 w reset 00000000 figure 6-17. debug comparator address low register (dbgxal) table 6-31. dbgxal field descriptions field description 7? bits[7:0] comparator address low compare bits ?the comparator address low compare bits control whether the selected comparator will compare the address bus bits [7:0] to a logic one or logic zero. 0 compare corresponding address bit to a logic zero 1 compare corresponding address bit to a logic one
s12x debug (s12xdbgv3) module s12xs family reference manual, rev. 1.10 212 freescale semiconductor 6.3.2.8.5 debug comparator data high register (dbgxdh) read: anytime. see table 6-26 for visible register encoding. write: if dbg not armed. see table 6-26 for visible register encoding. 6.3.2.8.6 debug comparator data low register (dbgxdl) read: anytime. see table 6-26 for visible register encoding. write: if dbg not armed. see table 6-26 for visible register encoding. address: 0x002c 76543210 r bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 w reset 00000000 figure 6-18. debug comparator data high register (dbgxdh) table 6-32. dbgxah field descriptions field description 7? bits[15:8] comparator data high compare bits the comparator data high compare bits control whether the selected comparator compares the data bus bits [15:8] to a logic one or logic zero. the comparator data compare bits are only used in comparison if the corresponding data mask bit is logic 1. this register is available only for comparators a and c. 0 compare corresponding data bit to a logic zero 1 compare corresponding data bit to a logic one address: 0x002d 76543210 r bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 w reset 00000000 figure 6-19. debug comparator data low register (dbgxdl) table 6-33. dbgxdl field descriptions field description 7? bits[7:0] comparator data low compare bits the comparator data low compare bits control whether the selected comparator compares the data bus bits [7:0] to a logic one or logic zero. the comparator data compare bits are only used in comparison if the corresponding data mask bit is logic 1. this register is available only for comparators a and c. 0 compare corresponding data bit to a logic zero 1 compare corresponding data bit to a logic one
s12x debug (s12xdbgv3) module s12xs family reference manual, rev. 1.10 freescale semiconductor 213 6.3.2.8.7 debug comparator data high mask register (dbgxdhm) read: anytime. see table 6-26 for visible register encoding. write: if dbg not armed. see table 6-26 for visible register encoding. 6.3.2.8.8 debug comparator data low mask register (dbgxdlm) read: anytime. see table 6-26 for visible register encoding. write: if dbg not armed. see table 6-26 for visible register encoding. 6.4 functional description this section provides a complete functional description of the s12xdbg module. if the part is in secure mode, the s12xdbg module can generate breakpoints but tracing is not possible. address: 0x002e 76543210 r bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 w reset 00000000 figure 6-20. debug comparator data high mask register (dbgxdhm) table 6-34. dbgxdhm field descriptions field description 7? bits[15:8] comparator data high mask bits ?the comparator data high mask bits control whether the selected comparator compares the data bus bits [15:8] to the corresponding comparator data compare bits. this register is available only for comparators a and c. 0 do not compare corresponding data bit 1 compare corresponding data bit address: 0x002f 76543210 r bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 w reset 00000000 figure 6-21. debug comparator data low mask register (dbgxdlm) table 6-35. dbgxdlm field descriptions field description 7? bits[7:0] comparator data low mask bits ?the comparator data low mask bits control whether the selected comparator compares the data bus bits [7:0] to the corresponding comparator data compare bits. this register is available only for comparators a and c. 0 do not compare corresponding data bit 1 compare corresponding data bit
s12x debug (s12xdbgv3) module s12xs family reference manual, rev. 1.10 214 freescale semiconductor 6.4.1 s12xdbg operation arming the s12xdbg module by setting arm in dbgc1 allows triggering, and storing of data in the trace buffer and can be used to cause breakpoints to the cpu12x . the dbg module is made up of four main blocks, the comparators, control logic, the state sequencer, and the trace buffer. the comparators monitor the bus activity of the cpu12x . comparators can be con?ured to monitor address and databus. comparators can also be con?ured to mask out individual data bus bits during a compare and to use r/w and word/byte access quali?ation in the comparison. when a match with a comparator register value occurs the associated control logic can trigger the state sequencer to another state (see figure 6-22 ). either forced or tagged triggers are possible. using a forced trigger, the trigger is generated immediately on a comparator match. using a tagged trigger, at a comparator match, the instruction opcode is tagged and only if the instruction reaches the execution stage of the instruction queue is a trigger generated. in the case of a transition to final state, bus tracing is triggered and/or a breakpoint can be generated. independent of the state sequencer, a breakpoint can be triggered by writing to the trig bit in the dbgc1 control register. the trace buffer is visible through a 2-byte window in the register address map and can be read out using standard 16-bit word reads. 6.4.2 comparator modes the s12xdbg contains four comparators, a, b, c, and d. each comparator compares the selected address bus with the address stored in dbgxah, dbgxam, and dbgxal. furthermore, comparators a and c also compare the data buses to the data stored in dbgxdh, dbgxdl and allow masking of individual data bus bits. s12x comparator matches are disabled in bdm and during bdm accesses. the comparator match control logic con?ures comparators to monitor the buses for an exact address or an address range. the comparator con?uration is controlled by the control register contents and the range control by the dbgc2 contents. on a match a trigger can initiate a transition to another state sequencer state (see section 6.4.3 ). the comparator control register also allows the type of access to be included in the comparison through the use of the rwe, rw, sze, and sz bits. the rwe bit controls whether read or write comparison is enabled for the associated comparator and the rw bit selects either a read or write access for a valid match. similarly the sze and sz bits allows the size of access (word or byte) to be considered in the compare. only comparators b and d feature sze and sz. the tag bit in each comparator control register is used to determine the triggering condition. by setting tag, the comparator will qualify a match with the output of opcode tracking logic and a trigger occurs before the tagged instruction executes (tagged-type trigger). whilst tagging, the rw, rwe, sze, and sz bits are ignored and the comparator register must be loaded with the exact opcode address. if the tag bit is clear (forced type trigger) a comparator match is generated when the selected address appears on the system address bus. if the selected address is an opcode address, the match is generated
s12x debug (s12xdbgv3) module s12xs family reference manual, rev. 1.10 freescale semiconductor 215 when the opcode is fetched from the memory. this precedes the instruction execution by an inde?ite number of cycles due to instruction pipe lining. for a comparator match of an opcode at an odd address when tag = 0, the corresponding even address must be contained in the comparator register. thus for an opcode at odd address (n), the comparator register must contain address (n?). once a successful comparator match has occurred, the condition that caused the original match is not veri?d again on subsequent matches. thus if a particular data value is veri?d at a given address, this address may not still contain that data value when a subsequent match occurs. comparators c and d can also be used to select an address range to trace from. this is determined by the trange bits in the dbgtcr register. the trange encoding is shown in table 6-9 . if the trange bits select a range de?ition using comparator d, then comparator d is con?ured for trace range de?ition and cannot be used for address bus comparisons. similarly if the trange bits select a range de?ition using comparator c, then comparator c is con?ured for trace range de?ition and cannot be used for address bus comparisons. match[0, 1, 2, 3] map directly to comparators[a, b, c, d] respectively, except in range modes (see section 6.3.2.4 ). comparator priority rules are described in the trigger priority section ( section 6.4.3.4? . 6.4.2.1 exact address comparator match (comparators a and c) with range comparisons disabled, the match condition is an exact equivalence of address/data bus with the value stored in the comparator address/data registers. further quali?ation of the type of access (r/w, word/byte) is possible. comparators a and c do not feature sze or sz control bits, thus the access size is not compared. table 6- 37 lists access considerations without data bus compare. table 6-36 lists access considerations with data bus comparison. to compare byte accesses dbgxdh must be loaded with the data byte, the low byte must be masked out using the dbgxdlm mask register. on word accesses the data byte of the lower address is mapped to dbgxdh. code may contain various access forms of the same address, i.e. a word access of addr[n] or byte access of addr[n+1] both access n+1. at a word access of addr[n], address addr[n+1] does not appear on the address bus and so cannot cause a comparator match if the comparator contains addr[n]. thus it is not possible to monitor all data accesses of addr[n+1] with one comparator. to detect an access of addr[n+1] through a word access of addr[n] the comparator can be configured to addr[n], dbgxdl is loaded with the data pattern and dbgxdhm is cleared so only the data[n+1] is compared on accesses of addr[n]. table 6-36. comparator a and c data bus considerations access address dbgxdh dbgxdl dbgxdhm dbgxdlm example valid match word addr[n] data[n] data[n+1] $ff $ff movw #$word addr[n] con?1 byte addr[n] data[n] x $ff $00 movb #$byte addr[n] con?2 word addr[n] data[n] x $ff $00 movw #$word addr[n] con?2 word addr[n] x data[n+1] $00 $ff movw #$word addr[n] con?3
s12x debug (s12xdbgv3) module s12xs family reference manual, rev. 1.10 216 freescale semiconductor note using this configuration, a byte access of addr[n] can cause a comparator match if the databus low byte by chance contains the same value as addr[n+1] because the databus comparator does not feature access size comparison and uses the mask as a ?on? care?function. thus masked bits do not prevent a match. comparators a and c feature an ndb control bit to determine if a match occurs when the data bus differs to comparator register contents or when the data bus is equivalent to the comparator register contents. 6.4.2.2 exact address comparator match (comparators b and d) comparators b and d feature sz and sze control bits. if sze is clear, then the comparator address match quali?ation functions the same as for comparators a and c. if the sze bit is set the access size (word or byte) is compared with the sz bit value such that only the speci?d type of access causes a match. thus if con?ured for a byte access of a particular address, a word access covering the same address does not lead to match. 6.4.2.3 data bus comparison ndb dependency comparators a and c each feature an ndb control bit, which allows data bus comparators to be con?ured to either trigger on equivalence or trigger on difference. this allows monitoring of a difference in the contents of an address location from an expected value. when matching on an equivalence (ndb=0), each individual data bus bit position can be masked out by clearing the corresponding mask bit (dbgxdhm/dbgxdlm), so that it is ignored in the comparison. a match occurs when all data bus bits with corresponding mask bits set are equivalent. if all mask register bits are clear, then a match is based on the address bus only, the data bus is ignored. when matching on a difference, mask bits can be cleared to ignore bit positions. a match occurs when any data bus bit with corresponding mask bit set is different. clearing all mask bits, causes all bits to be ignored and prevents a match because no difference can be detected. in this case address bus equivalence does not cause a match. table 6-37. comparator access size considerations comparator address sze sz8 condition for valid match comparators a and c addr[n] word and byte accesses of addr[n] 1 movb #$byte addr[n] movw #$word addr[n] 1 a word access of addr[n-1] also accesses addr[n] but does not generate a match. the comparator address register must contain the exact address used in the code. comparators b and d addr[n] 0 x word and byte accesses of addr[n] 1 movb #$byte addr[n] movw #$word addr[n] comparators b and d addr[n] 1 0 word accesses of addr[n] 1 movw #$word addr[n] comparators b and d addr[n] 1 1 byte accesses of addr[n] movb #$byte addr[n]
s12x debug (s12xdbgv3) module s12xs family reference manual, rev. 1.10 freescale semiconductor 217 6.4.2.4 range comparisons when using the ab comparator pair for a range comparison, the data bus can also be used for quali?ation by using the comparator a data and data mask registers. furthermore the dbgactl rw and rwe bits can be used to qualify the range comparison on either a read or a write access. the corresponding dbgbctl bits are ignored. similarly when using the cd comparator pair for a range comparison, the data bus can also be used for quali?ation by using the comparator c data and data mask registers. furthermore the dbgcctl rw and rwe bits can be used to qualify the range comparison on either a read or a write access if tagging is not selected. the corresponding dbgdctl bits are ignored. the sze and sz control bits are ignored in range mode. the comparator a and c tag bits are used to tag range comparisons for the ab and cd ranges respectively. the comparator b and d tag bits are ignored in range modes. in order for a range comparison using comparators a and b, both compea and compeb must be set; to disable range comparisons both must be cleared. similarly for a range cd comparison, both compec and comped must be set. the comparator a and c brk bits are used for the ab and cd ranges respectively, the comparator b and d brk bits are ignored in range mode. when con?ured for range comparisons and tagging, the ranges are accurate only to word boundaries. 6.4.2.4.1 inside range (compac_addr address compbd_addr) in the inside range comparator mode, either comparator pair a and b or comparator pair c and d can be con?ured for range comparisons by the control register (dbgc2). the match condition requires that a valid match for both comparators happens on the same bus cycle. a match condition on only one comparator is not valid. an aligned word access which straddles the range boundary will cause a trigger only if the aligned address is inside the range. 6.4.2.4.2 outside range (address < compac_addr or address > compbd_addr) in the outside range comparator mode, either comparator pair a and b or comparator pair c and d can be con?ured for range comparisons. a single match condition on either of the comparators is recognized as valid. an aligned word access which straddles the range boundary will cause a trigger only if the aligned address is outside the range. outside range mode in combination with tagged triggers can be used to detect if the opcode fetches are from an unexpected range. in forced trigger modes the outside range trigger would typically be activated at any interrupt vector fetch or register access. this can be avoided by setting the upper or lower range limit to $7fffff or $000000 respectively. interrupt vector fetches do not cause taghits table 6-38. ndb and mask bit dependency ndb dbgxdhm[n] / dbgxdlm[n] comment 0 0 do not compare data bus bit. 0 1 compare data bus bit. match on equivalence. 1 0 do not compare data bus bit. 1 1 compare data bus bit. match on difference.
s12x debug (s12xdbgv3) module s12xs family reference manual, rev. 1.10 218 freescale semiconductor 6.4.3 trigger modes trigger modes are used as quali?rs for a state sequencer change of state. the control logic determines the trigger mode and provides a trigger to the state sequencer. the individual trigger modes are described in the following sections. 6.4.3.1 forced trigger on comparator match if a forced trigger comparator match occurs, the trigger immediately initiates a transition to the next state sequencer state whereby the corresponding ?gs in dbgsr are set. the state control register for the current state determines the next state for each trigger. forced triggers are generated as soon as the matching address appears on the address bus, which in the case of opcode fetches occurs several cycles before the opcode execution. for this reason a forced trigger at an opcode address precedes a tagged trigger at the same address by several cycles. 6.4.3.2 trigger on comparator related taghit if a cpu12x taghit occurs, a transition to another state sequencer state is initiated and the corresponding dbgsr ?gs are set. for a comparator related taghit to occur, the s12xdbg must ?st generate tags based on comparator matches. when the tagged instruction reaches the execution stage of the instruction queue a taghit is generated by the cpu12x. the state control register for the current state determines the next state for each trigger. 6.4.3.3 trig immediate trigger independent of comparator matches it is possible to initiate a tracing session and/or breakpoint by writing the trig bit in dbgc1 to a logic ?? if con?ured for begin or mid aligned tracing, this triggers the state sequencer into the final state, if con?ured for end alignment, setting the trig bit disarms the module, ending the session. if breakpoints are enabled, a forced breakpoint request is issued immediately (end alignment) or when tracing has completed (begin or mid alignment). 6.4.3.4 trigger priorities in case of simultaneous triggers, the priority is resolved according to table 6-39 . the lower priority trigger is suppressed. it is thus possible to miss a lower priority trigger if it occurs simultaneously with a trigger of a higher priority. the trigger priorities described in table 6-39 dictate that in the case of simultaneous matches, the match on the lower channel number (0,1,2,3) has priority. the sc[3:0] encoding ensures that a match leading to ?al state has priority over all other matches in each state sequencer state. when con?ured for range modes a simultaneous match of comparators a and c generates an active match0 whilst match2 is suppressed. if a write access to dbgc1 with the arm bit position set occurs simultaneously to a hardware disarm from an internal trigger event, then the arm bit is cleared due to the hardware disarm. table 6-39. trigger priorities priority source action
s12x debug (s12xdbgv3) module s12xs family reference manual, rev. 1.10 freescale semiconductor 219 6.4.4 state sequence control figure 6-22. state sequencer diagram the state sequencer allows a de?ed sequence of events to provide a trigger point for tracing of data in the trace buffer. once the s12xdbg module has been armed by setting the arm bit in the dbgc1 register, then state1 of the state sequencer is entered. further transitions between the states are then controlled by the state control registers and depend upon a selected trigger mode condition being met. from final state the only permitted transition is back to the disarmed state0. transition between any of the states 1 to 3 is not restricted. each transition updates the ssf[2:0] ?gs in dbgsr accordingly to indicate the current state. alternatively by setting the trig bit in dbgsc1, the state machine can be triggered to state0 or final state depending on tracing alignment. independent of the state sequencer, each comparator channel can be individually con?ured to generate an immediate breakpoint when a match occurs through the use of the brk bits in the dbgxctl registers. thus it is possible to generate an immediate breakpoint on selected channels, whilst a state sequencer transition can be initiated by a match on other channels. if a debug session is ended by a trigger on a channel with brk = 1, the state sequencer transitions through final state for a clock cycle to state0. this is independent of tracing and breakpoint activity, thus with tracing and breakpoints disabled, the state sequencer enters state0 and the debug module is disarmed. highest trig trigger immediately to ?al state (begin or mid aligned tracing enabled) trigger immediately to state 0 (end aligned or no tracing enabled) match0 (force or tag hit) trigger to next state as de?ed by state control registers match1 (force or tag hit) trigger to next state as de?ed by state control registers match2 (force or tag hit) trigger to next state as de?ed by state control registers lowest match3 (force or tag hit) trigger to next state as de?ed by state control registers table 6-39. trigger priorities state1 final state state3 arm = 1 session complete (disarm) state2 state 0 (disarmed) arm = 0 arm = 0 arm = 0
s12x debug (s12xdbgv3) module s12xs family reference manual, rev. 1.10 220 freescale semiconductor 6.4.4.1 final state on entering final state a trigger may be issued to the trace buffer according to the trace position control as de?ed by the talign ?ld (see section 6.3.2.3 ). if tsource in the trace control register dbgtcr is cleared then the trace buffer is disabled and the transition to final state can only generate a breakpoint request. in this case or upon completion of a tracing session when tracing is enabled, the arm bit in the dbgc1 register is cleared, returning the module to the disarmed state0. if tracing is enabled, a breakpoint request can occur at the end of the tracing session. if neither tracing nor breakpoints are enabled then when the ?al state is reached it returns automatically to state0 and the debug module is disarmed. 6.4.5 trace buffer operation the trace buffer is a 64 lines deep by 64-bits wide ram array. the s12xdbg module stores trace information in the ram array in a circular buffer format. the ram array can be accessed through a register window (dbgtbh:dbgtbl) using 16-bit wide word accesses. after each complete 64-bit trace buffer line is read, an internal pointer into the ram is incremented so that the next read will receive fresh information. data is stored in the format shown in table 6-40 . after each store the counter register bits dbgcnt[6:0] are incremented. tracing of cpu12x activity is disabled when the bdm is active. reading the trace buffer whilst the dbg is armed returns invalid data and the trace buffer pointer is not incremented. 6.4.5.1 trace trigger alignment using the talign bits (see section 6.3.2.3 ) it is possible to align the trigger with the end, the middle, or the beginning of a tracing session. if end or mid tracing is selected, tracing begins when the arm bit in dbgc1 is set and state1 is entered. the transition to final state if end is selected signals the end of the tracing session. the transition to final state if mid is selected signals that another 32 lines will be traced before ending the tracing session. tracing with begin-trigger starts at the opcode of the trigger. 6.4.5.1.1 storing with begin-trigger storing with begin-trigger, data is not stored in the trace buffer until the final state is entered. once the trigger condition is met the s12xdbg module will remain armed until 64 lines are stored in the trace buffer. if the trigger is at the address of the change-of-?w instruction the change of ?w associated with the trigger will be stored in the trace buffer. using begin-trigger together with tagging, if the tagged instruction is about to be executed then the trace is started. upon completion of the tracing session the breakpoint is generated, thus the breakpoint does not occur at the tagged instruction boundary. 6.4.5.1.2 storing with mid-trigger storing with mid-trigger, data is stored in the trace buffer as soon as the s12xdbg module is armed. when the trigger condition is met, another 32 lines will be traced before ending the tracing session, irrespective of the number of lines stored before the trigger occurred, then the s12xdbg module is disarmed and no more data is stored. using mid-trigger with tagging, if the tagged instruction is about to
s12x debug (s12xdbgv3) module s12xs family reference manual, rev. 1.10 freescale semiconductor 221 be executed then the trace is continued for another 32 lines. upon tracing completion the breakpoint is generated, thus the breakpoint does not occur at the tagged instruction boundary. 6.4.5.1.3 storing with end-trigger storing with end-trigger, data is stored in the trace buffer until the final state is entered, at which point the s12xdbg module will become disarmed and no more data will be stored. if the trigger is at the address of a change of ?w instruction the trigger event will not be stored in the trace buffer. 6.4.5.2 trace modes the s12xdbg module can operate in four trace modes. the mode is selected using the trcmod bits in the dbgtcr register. the modes are described in the following subsections. the trace buffer organization is shown in table 6-40 . 6.4.5.2.1 normal mode in normal mode, change of ?w (cof) program counter (pc) addresses will be stored. cof addresses are de?ed as follows : source address of taken conditional branches (long, short, bit-conditional, and loop primitives) destination address of indexed jmp, jsr, and call instruction destination address of rti, rts, and rtc instructions. vector address of interrupts, except for swi and bdm vectors lbra, bra, bsr, bgnd as well as non-indexed jmp, jsr, and call instructions are not classi?d as change of ?w and are not stored in the trace buffer. change-of-?w addresses stored include the full 23-bit address bus of cpu12x and an information byte, which contains a source/destination bit to indicate whether the stored address was a source address or destination address. note when an cpu12x cof instruction with destination address is executed, the destination address is stored to the trace buffer on instruction completion, indicating the cof has taken place. if an interrupt occurs simultaneously then the next instruction carried out is actually from the interrupt service routine. the instruction at the destination address of the original program ?w gets exectuted after the interrupt service routine. in the following example an irq interrupt occurs during execution of the indexed jmp at address mark1. the brn at the destination (sub_1) is not executed until after the irq service routine but the destination address is entered into the trace buffer to indicate that the indexed jmp cof has taken place. ldx #sub_1 mark1 jmp 0,x ; irq interrupt occurs during execution of this mark2 nop ;
s12x debug (s12xdbgv3) module s12xs family reference manual, rev. 1.10 222 freescale semiconductor sub_1 brn * ; jmp destination address trace buffer entry 1 ; rti destination address trace buffer entry 3 nop ; addr1 dbne a,part5 ; source address trace buffer entry 4 irq_isr ldab #$f0 ; irq vector $fff2 = trace buffer entry 2 stab var_c1 rti ; the execution ?w taking into account the irq is as follows ldx #sub_1 mark1 jmp 0,x ; irq_isr ldab #$f0 ; stab var_c1 rti ; sub_1 brn * nop ; addr1 dbne a,part5 ; 6.4.5.2.2 loop1 mode loop1 mode, similarly to normal mode also stores only cof address information to the trace buffer, it however allows the ?tering out of redundant information. the intent of loop1 mode is to prevent the trace buffer from being ?led entirely with duplicate information from a looping construct such as delays using the dbne instruction or polling loops using brset/brclr instructions. immediately after address information is placed in the trace buffer, the s12xdbg module writes this value into a background register. this prevents consecutive duplicate address entries in the trace buffer resulting from repeated branches. loop1 mode only inhibits consecutive duplicate source address entries that would typically be stored in most tight looping constructs. it does not inhibit repeated entries of destination addresses or vector addresses, since repeated entries of these would most likely indicate a bug in the users code that the s12xdbg module is designed to help ?d. 6.4.5.2.3 detail mode in detail mode, address and data for all memory and register accesses is stored in the trace buffer. this mode also features information byte entries to the trace buffer, for each address byte entry. the information byte indicates the size of access (word or byte) and the type of access (read or write). when tracing cpu12x activity in detail mode, all cycles are traced except those when the cpu12x is either in a free or opcode fetch cycle, the address range can be limited to a range speci?d by the trange bits in dbgtcr. this function uses comparators c and d to de?e an address range inside which cpu12x activity should be traced (see table 6-40 ). thus the traced cpu12x activity can be restricted to particular register range accesses. 6.4.5.2.4 pure pc mode in pure pc mode, tracing from the cpu the pc addresses of all executed opcodes, including illegal opcodes, are stored.
s12x debug (s12xdbgv3) module s12xs family reference manual, rev. 1.10 freescale semiconductor 223 6.4.5.3 trace buffer organization referring to table 6-40 . adrh, adrm, adrl denote address high, middle and low byte respectively. inf bytes contain control information (r/w, s/d etc.). the numerical suf? indicates which tracing step. the information format for loop1 mode and purepc mode is the same as that of normal mode. whilst tracing in normal or loop1 modes each array line contains 2 data entries, thus in this case the dbgcnt[0] is incremented after each separate entry. in detail mode dbgcnt[0] remains cleared whilst the other dbgcnt bits are incremented on each trace buffer entry. when a cof occurs a trace buffer entry is made and the corresponding cdv bit is set. single byte data accesses in detail mode are always stored to the low byte of the trace buffer (cdatal ) and the high byte is cleared. when tracing word accesses, the byte at the lower address is always stored to trace buffer byte3 and the byte at the higher address is stored to byte2 table 6-40. trace buffer organization mode 8-byte wide word buffer 76543210 s12xcpu detail cxinf1 cadrh1 cadrm1 cadrl1 cdatah1 cdatal1 cxinf2 cadrh2 cadrm2 cadrl2 cdatah2 cdatal2 cpu12x other modes cinf1 cpch1 cpcm1 cpcl1 cinf0 cpch0 cpcm0 cpcl0 cinf3 cpch3 cpcm3 cpcl3 cinf2 cpch2 cpcm2 cpcl2
s12x debug (s12xdbgv3) module s12xs family reference manual, rev. 1.10 224 freescale semiconductor 6.4.5.3.1 information byte organization the format of the control information byte is dependent upon the active trace mode as described below. in normal, loop1, or pure pc modes tracing of cpu12x activity, cinf is used to store control information. in detail mode, cxinf contains the control information cpu12x information byte cxinf information byte this describes the format of the information byte used only when tracing in detail mode. when tracing from the cpu12x in detail mode, information is stored to the trace buffer on all cycles except opcode fetch and free cycles. in this case the csz and crw bits indicate the type of access being made by the cpu12x. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 csd cva 0 cdv 0 0 0 0 figure 6-23. cpu12x information byte cinf table 6-41. cinf field descriptions field description 7 csd source destination indicator this bit indicates if the corresponding stored address is a source or destination address. this is only used in normal and loop1 mode tracing. 0 source address 1 destination address 6 cva vector indicator this bit indicates if the corresponding stored address is a vector address.. vector addresses are destination addresses, thus if cva is set, then the corresponding csd is also set. this is only used in normal and loop1 mode tracing. this bit has no meaning in pure pc mode. 0 indexed jump destination address 1 vector destination address 4 cdv data invalid indicator ?this bit indicates if the trace buffer entry is invalid. it is only used when tracing from both sources in normal, loop1 and pure pc modes, to indicate that the cpu12x trace buffer entry is valid. 0 trace buffer entry is invalid 1 trace buffer entry is valid bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 csz crw figure 6-24. information byte cxinf table 6-42. cxinf field descriptions field description 6 csz access type indicator this bit indicates if the access was a byte or word size access.this bit only contains valid information when tracing cpu12x activity in detail mode. 0 word access 1 byte access
s12x debug (s12xdbgv3) module s12xs family reference manual, rev. 1.10 freescale semiconductor 225 6.4.5.4 reading data from trace buffer the data stored in the trace buffer can be read using either the background debug module (bdm) module or the cpu12x provided the s12xdbg module is not armed, is con?ured for tracing and the system not secured. when the arm bit is written to 1 the trace buffer is locked to prevent reading. the trace buffer can only be unlocked for reading by an aligned word write to dbgtb when the module is disarmed. the trace buffer can only be read through the dbgtb register using aligned word reads, any byte or misaligned reads return 0 and do not cause the trace buffer pointer to increment to the next trace buffer address. the trace buffer data is read out ?st-in ?st-out. by reading cnt in dbgcnt the number of valid 64-bit lines can be determined. dbgcnt will not decrement as data is read. whilst reading an internal pointer is used to determine the next line to be read. after a tracing session, the pointer points to the oldest data entry, thus if no over?w has occurred, the pointer points to line0, otherwise it points to the line with the oldest entry. the pointer is initialized by each aligned write to dbgtbh to point to the oldest data again. this enables an interrupted trace buffer read sequence to be easily restarted from the oldest data entry. the least signi?ant word of each 64-bit wide array line is read out ?st. this corresponds to the bytes 1 and 0 of table 6-40 . the bytes containing invalid information (shaded in table 6-40 ) are also read out. reading the trace buffer while the s12xdbg module is armed will return invalid data and no shifting of the ram pointer will occur. 6.4.5.5 trace buffer reset state the trace buffer contents are not initialized by a system reset. thus should a system reset occur, the trace session information from immediately before the reset occurred can be read out. the dbgcnt bits are not cleared by a system reset. thus should a reset occur, the number of valid lines in the trace buffer is indicated by dbgcnt. the internal pointer to the current trace buffer address is initialized by unlocking the trace buffer thus points to the oldest valid data even if a reset occurred during the tracing session. generally debugging occurrences of system resets is best handled using mid or end trigger alignment since the reset may occur before the trace trigger, which in the begin trigger alignment case means no information would be stored in the trace buffer. note an external pin reset that occurs simultaneous to a trace buffer entry can, in very seldom cases, lead to either that entry being corrupted or the ?st entry of the session being corrupted. in such cases the other contents of the trace buffer still contain valid tracing information. the case occurs when the reset assertion coincides with the trace buffer entry clock edge. 5 crw read write indicator ?this bit indicates if the corresponding stored address corresponds to a read or write access. this bit only contains valid information when tracing cpu12x activity in detail mode. 0 write access 1 read access table 6-42. cxinf field descriptions (continued) field description
s12x debug (s12xdbgv3) module s12xs family reference manual, rev. 1.10 226 freescale semiconductor 6.4.6 tagging a tag follows program information as it advances through the instruction queue. when a tagged instruction reaches the head of the queue a tag hit occurs and triggers the state sequencer. each comparator control register features a tag bit, which controls whether the comparator match will cause a trigger immediately or tag the opcode at the matched address. if a comparator is enabled for tagged comparisons, the address stored in the comparator match address registers must be an opcode address for the trigger to occur. using begin trigger together with tagging, if the tagged instruction is about to be executed then the transition to the next state sequencer state occurs. if the transition is to the final state, tracing is started. only upon completion of the tracing session can a breakpoint be generated. similarly using mid trigger with tagging, if the tagged instruction is about to be executed then the trace is continued for another 32 lines. upon tracing completion the breakpoint is generated. using end trigger, when the tagged instruction is about to be executed and the next transition is to final state then a breakpoint is generated immediately, before the tagged instruction is carried out. read/write (r/w), access size (sz) monitoring and data bus monitoring is not useful if tagged triggering is selected, since the tag is attached to the opcode at the matched address and is not dependent on the data bus nor on the type of access. thus these bits are ignored if tagged triggering is selected. when con?ured for range comparisons and tagging, the ranges are accurate only to word boundaries. s12x tagging is disabled when the bdm becomes active. 6.4.7 breakpoints breakpoints can be generated as follows. from comparator channel triggers to ?al state. using software to write to the trig bit in the dbgc1 register. breakpoints generated via the bdm background command have no affect on the cpu12x in stop or wait mode. 6.4.7.1 breakpoints from internal comparator channel final state triggers breakpoints can be generated when internal comparator channels trigger the state sequencer to the final state. if con?ured for tagging, then the breakpoint is generated when the tagged opcode reaches the execution stage of the instruction queue. if a tracing session is selected by tsource, breakpoints are requested when the tracing session has completed, thus if begin or mid aligned triggering is selected, the breakpoint is requested only on completion of the subsequent trace (see table 6-43 ). if no tracing session is selected, breakpoints are requested immediately. if the brk bit is set on the triggering channel, then the breakpoint is generated immediately independent of tracing trigger alignment.
s12x debug (s12xdbgv3) module s12xs family reference manual, rev. 1.10 freescale semiconductor 227 6.4.7.2 breakpoints generated via the trig bit if a trig triggers occur, the final state is entered. if a tracing session is selected by tsource, breakpoints are requested when the tracing session has completed, thus if begin or mid aligned triggering is selected, the breakpoint is requested only on completion of the subsequent trace (see table 6-43 ). if no tracing session is selected, breakpoints are requested immediately. trig breakpoints are possible even if the s12xdbg module is disarmed. 6.4.7.3 s12xdbg breakpoint priorities if a trig trigger occurs after begin or mid aligned tracing has already been triggered by a comparator instigated transition to final state, then trig no longer has an effect. when the associated tracing session is complete, the breakpoint occurs. similarly if a trig is followed by a subsequent trigger from a comparator channel, it has no effect, since tracing has already started. 6.4.7.3.1 s12xdbg breakpoint priorities and bdm interfacing breakpoint operation is dependent on the state of the s12xbdm module. if the s12xbdm module is active, the cpu12x is executing out of bdm ?mware and s12x breakpoints are disabled. in addition, while executing a bdm trace command, tagging into bdm is disabled. if bdm is not active, the breakpoint will give priority to bdm requests over swi requests if the breakpoint coincides with a swi instruction in the users code. on returning from bdm, the swi from user code gets executed. table 6-43. breakpoint setup brk talign dbgbrk breakpoint alignment 0 00 0 fill trace buffer until trigger (no breakpoints ?keep running) 0 00 1 fill trace buffer until trigger, then breakpoint request occurs 0 01 0 start trace buffer at trigger (no breakpoints ?keep running) 0 01 1 start trace buffer at trigger a breakpoint request occurs when trace buffer is full 0 10 0 store a further 32 trace buffer line entries after trigger (no breakpoints ?keep running) 0 10 1 store a further 32 trace buffer line entries after trigger request breakpoint after the 32 further trace buffer entries 1 00,01,10 1 terminate tracing and generate breakpoint immediately on trigger 1 00,01,10 0 terminate tracing immediately on trigger x 11 x reserved table 6-44. breakpoint mapping summary dbgbrk (dbgc1[3]) bdm bit (dbgc1[4]) bdm enabled bdm active s12x breakpoint mapping 0 x x x no breakpoint 1 0 x 0 breakpoint to swi 1 0 x 1 no breakpoint
s12x debug (s12xdbgv3) module s12xs family reference manual, rev. 1.10 228 freescale semiconductor bdm cannot be entered from a breakpoint unless the enable bit is set in the bdm. if entry to bdm via a bgnd instruction is attempted and the enable bit in the bdm is cleared, the cpu12x actually executes the bdm ?mware code. it checks the enable and returns if enable is not set. if not serviced by the monitor then the breakpoint is re-asserted when the bdm returns to normal cpu12x ?w. if the comparator register contents coincide with the swi/bdm vector address then an swi in user code and dbg breakpoint could occur simultaneously. the cpu12x ensures that bdm requests have a higher priority than swi requests. returning from the bdm/swi service routine care must be taken to avoid re triggering a breakpoint. note when program control returns from a tagged breakpoint using an rti or bdm go command without program counter modi?ation it will return to the instruction whose tag generated the breakpoint. to avoid re triggering a breakpoint at the same location recon?ure the s12xdbg module in the swi routine, if con?ured for an swi breakpoint, or over the bdm interface by executing a trace command before the go to increment the program ?w past the tagged instruction. 1 1 0 x breakpoint to swi 1 1 1 0 breakpoint to bdm 1 1 1 1 no breakpoint table 6-44. breakpoint mapping summary
s12xs family reference manual, rev. 1.10 freescale semiconductor 229 chapter 7 security (s12xs9secv2) 7.1 introduction this speci?ation describes the function of the security mechanism in the s12xs chip family (9sec). note no security feature is absolutely secure. however, freescales strategy is to make reading or copying the flash and/or eeprom dif?ult for unauthorized users. 7.1.1 features the user must be reminded that part of the security must lie with the application code. an extreme example would be application code that dumps the contents of the internal memory. this would defeat the purpose of security. at the same time, the user may also wish to put a backdoor in the application program. an example of this is the user downloads a security key through the sci, which allows access to a programming routine that updates parameters stored in another section of the flash memory. the security features of the s12xs chip family (in secure mode) are: protect the content of non-volatile memories (flash, eeprom) execution of nvm commands is restricted disable access to internal memory via background debug module (bdm) table 7-2 gives an overview over availability of security relevant features in unsecure and secure modes. table 7-1. revision history version number revision date effective date author description of changes 02.00 27 aug 2004 08 sep 2004 reviewed and updated for s12xd architecture 02.01 21 feb 2007 21 feb 2007 added s12xe, s12xf and s12xs architectures 02.02 19 apr 2007 19 apr 2007 corrected statement about backdoor key access via bdm on xe, xf, xs table 7-2. feature availability in unsecure and secure modes on s12xs unsecure mode secure mode ns ss nx es ex st ns ss nx es ex st flash array access ?? ??
security (s12xs9secv2) s12xs family reference manual, rev. 1.10 230 freescale semiconductor 7.1.2 modes of operation 7.1.3 securing the microcontroller once the user has programmed the flash and eeprom, the chip can be secured by programming the security bits located in the options/security byte in the flash memory array. these non-volatile bits will keep the device secured through reset and power-down. the options/security byte is located at address 0xff0f (= global address 0x7f_ff0f) in the flash memory array. this byte can be erased and programmed like any other flash location. two bits of this byte are used for security (sec[1:0]). on devices which have a memory page window, the flash options/security byte is also available at address 0xbf0f by selecting page 0x3f with the ppage register. the contents of this byte are copied into the flash security register (fsec) during a reset sequence. the meaning of the bits keyen[1:0] is shown in table 7-3 . please refer to section 7.1.5.1, ?nsecuring the mcu using the backdoor key access for more information. the meaning of the security bits sec[1:0] is shown in table 7-4 . for security reasons, the state of device security is controlled by two bits. to put the device in unsecured mode, these bits must be programmed to eeprom array access ?? ?? nvm commands ? 1 ? ? 1 ? 1 bdm ?? ? 2 dbg module trace ?? 1 restricted nvm command set only. please refer to the nvm wrapper block guides for detailed information. 2 bdm hardware commands restricted to peripheral registers only. 76543210 0xff0f keyen1 keyen0 nv5 nv4 nv3 nv2 sec1 sec0 figure 7-1. flash options/security byte table 7-3. backdoor key access enable bits keyen[1:0] backdoor key access enabled 00 0 (disabled) 01 0 (disabled) 10 1 (enabled) 11 0 (disabled) table 7-2. feature availability in unsecure and secure modes on s12xs unsecure mode secure mode ns ss nx es ex st ns ss nx es ex st
security (s12xs9secv2) s12xs family reference manual, rev. 1.10 freescale semiconductor 231 sec[1:0] = ?0? all other combinations put the device in a secured mode. the recommended value to put the device in secured state is the inverse of the unsecured state, i.e. sec[1:0] = ?1? note please refer to the flash block guide for actual security con?uration (in section ?lash module security?. 7.1.4 operation of the secured microcontroller by securing the device, unauthorized access to the eeprom and flash memory contents can be prevented. however, it must be understood that the security of the eeprom and flash memory contents also depends on the design of the application program. for example, if the application has the capability of downloading code through a serial port and then executing that code (e.g. an application containing bootloader code), then this capability could potentially be used to read the eeprom and flash memory contents even when the microcontroller is in the secure state. in this example, the security of the application could be enhanced by requiring a challenge/response authentication before any code can be downloaded. secured operation has the following effects on the microcontroller: table 7-4. security bits sec[1:0] security state 00 1 (secured) 01 1 (secured) 10 0 (unsecured) 11 1 (secured)
security (s12xs9secv2) s12xs family reference manual, rev. 1.10 232 freescale semiconductor 7.1.4.1 normal single chip mode (ns) background debug module (bdm) operation is completely disabled. execution of flash and eeprom commands is restricted. please refer to the nvm block guide for details. tracing code execution using the dbg module is disabled. 7.1.4.2 special single chip mode (ss) bdm ?mware commands are disabled. bdm hardware commands are restricted to the register space. execution of flash and eeprom commands is restricted. please refer to the nvm block guide for details. tracing code execution using the dbg module is disabled. special single chip mode means bdm is active after reset. the availability of bdm ?mware commands depends on the security state of the device. the bdm secure ?mware ?st performs a blank check of both the flash memory and the eeprom. if the blank check succeeds, security will be temporarily turned off and the state of the security bits in the appropriate flash memory location can be changed if the blank check fails, security will remain active, only the bdm hardware commands will be enabled, and the accessible memory space is restricted to the peripheral register area. this will allow the bdm to be used to erase the eeprom and flash memory without giving access to their contents. after erasing both flash memory and eeprom, another reset into special single chip mode will cause the blank check to succeed and the options/security byte can be programmed to ?nsecured?state via bdm. while the bdm is executing the blank check, the bdm interface is completely blocked, which means that all bdm commands are temporarily blocked.
security (s12xs9secv2) s12xs family reference manual, rev. 1.10 freescale semiconductor 233 7.1.5 unsecuring the microcontroller unsecuring the microcontroller can be done by three different methods: 1. backdoor key access 2. reprogramming the security bits 3. complete memory erase (special modes) 7.1.5.1 unsecuring the mcu using the backdoor key access in normal modes (single chip and expanded), security can be temporarily disabled using the backdoor key access method. this method requires that: the backdoor key at 0xff00?xff07 (= global addresses 0x7f_ff00?x7f_ff07) has been programmed to a valid value. the keyen[1:0] bits within the flash options/security byte select ?nabled? in single chip mode, the application program programmed into the microcontroller must be designed to have the capability to write to the backdoor key locations. the backdoor key values themselves would not normally be stored within the application data, which means the application program would have to be designed to receive the backdoor key values from an external source (e.g. through a serial port). the backdoor key access method allows debugging of a secured microcontroller without having to erase the flash. this is particularly useful for failure analysis. note no word of the backdoor key is allowed to have the value 0x0000 or 0xffff. 7.1.6 reprogramming the security bits in normal single chip mode (ns), security can also be disabled by erasing and reprogramming the security bits within flash options/security byte to the unsecured value. because the erase operation will erase the entire sector from 0xfe00?xffff (0x7f_fe00?x7f_ffff), the backdoor key and the interrupt vectors will also be erased; this method is not recommended for normal single chip mode. the application software can only erase and program the flash options/security byte if the flash sector containing the flash options/security byte is not protected (see flash protection). thus flash protection is a useful means of preventing this method. the microcontroller will enter the unsecured state after the next reset following the programming of the security bits to the unsecured value. this method requires that: the application software previously programmed into the microcontroller has been designed to have the capability to erase and program the flash options/security byte, or security is ?st disabled using the backdoor key method, allowing bdm to be used to issue commands to erase and program the flash options/security byte. the flash sector containing the flash options/security byte is not protected.
security (s12xs9secv2) s12xs family reference manual, rev. 1.10 234 freescale semiconductor 7.1.7 complete memory erase (special modes) the microcontroller can be unsecured in special modes by erasing the entire eeprom and flash memory contents. when a secure microcontroller is reset into special single chip mode (ss), the bdm ?mware veri?s whether the eeprom and flash memory are erased. if any eeprom or flash memory address is not erased, only bdm hardware commands are enabled. bdm hardware commands can then be used to write to the eeprom and flash registers to mass erase the eeprom and all flash memory blocks. when next reset into special single chip mode, the bdm ?mware will again verify whether all eeprom and flash memory are erased, and this being the case, will enable all bdm commands, allowing the flash options/security byte to be programmed to the unsecured value. the security bits sec[1:0] in the flash security register will indicate the unsecure state following the next reset.
s12xs family reference manual, rev. 1.10 freescale semiconductor 235 chapter 8 s12xe clocks and reset generator (s12xecrgv1) 8.1 introduction this specification describes the function of the clocks and reset generator (s12xecrg). 8.1.1 features the main features of this block are: phase locked loop (ipll) frequency multiplier with internal ?ter reference divider post divider con?urable internal ?ter (no external pin) optional frequency modulation for de?ed jitter and reduced emission automatic frequency lock detector interrupt request on entry or exit from locked condition self clock mode in absence of reference clock system clock generator clock quality check user selectable fast wake-up from stop in self-clock mode for power saving and immediate program execution clock switch for either oscillator or pll based system clocks computer operating properly (cop) watchdog timer with time-out clear window. system reset generation from the following possible sources: power on reset table 8-1. revision history revision number revision date sections affected description of changes v01.00 26 oct. 2005 initial release v01.01 02 nov 2006 8.4.1.1/8-252 table ?xamples of ipll divider settings? corrected $32 to $31 v01.02 4 mar. 2008 8.4.1.4/8-255 8.4.3.3/8-259 corrected details v01.03 1 sep. 2008 table 8-14 added 100mhz example for pll v01.04 20 nov. 2008 8.3.2.4/8-241 s12xecrg flags register: corrected address to module base + 0x0003 v01.05 19. sep 2009 8.5.1/8-261 modi?d note below table 8-17./8-261
s12xe clocks and reset generator (s12xecrgv1) s12xs family reference manual, rev. 1.10 236 freescale semiconductor low voltage reset illegal address reset cop reset loss of clock reset external pin reset real-time interrupt (rti) 8.1.2 modes of operation this subsection lists and briefly describes all operating modes supported by the s12xecrg. run mode all functional parts of the s12xecrg are running during normal run mode. if rti or cop functionality is required the individual bits of the associated rate select registers (copctl, rtictl) have to be set to a non zero value. wait mode in this mode the ipll can be disabled automatically depending on the pllwai bit. stop mode depending on the setting of the pstp bit stop mode can be differentiated between full stop mode (pstp = 0) and pseudo stop mode (pstp = 1). full stop mode the oscillator is disabled and thus all system and core clocks are stopped. the cop and the rti remain frozen. pseudo stop mode the oscillator continues to run and most of the system and core clocks are stopped. if the respective enable bits are set the cop and rti will continue to run, else they remain frozen. self clock mode self clock mode will be entered if the clock monitor enable bit (cme) and the self clock mode enable bit (scme) are both asserted and the clock monitor in the oscillator block detects a loss of clock. as soon as self clock mode is entered the s12xecrg starts to perform a clock quality check. self clock mode remains active until the clock quality check indicates that the required quality of the incoming clock signal is met (frequency and amplitude). self clock mode should be used for safety purposes only. it provides reduced functionality to the mcu in case a loss of clock is causing severe system conditions. 8.1.3 block diagram figure 8-1 shows a block diagram of the s12xecrg.
s12xe clocks and reset generator (s12xecrgv1) s12xs family reference manual rev. 1.10 freescale semiconductor 237 figure 8-1. block diagram of s12xecrg 8.2 signal description this section lists and describes the signals that connect off chip. 8.2.1 v ddpll , v sspll these pins provides operating voltage (v ddpll ) and ground (v sspll ) for the ipll circuitry. this allows the supply voltage to the ipll to be independently bypassed. even if ipll usage is not required v ddpll and v sspll must be connected to properly. 8.2.2 reset reset is an active low bidirectional reset pin. as an input it initializes the mcu asynchronously to a known start-up state. as an open-drain output it indicates that an system reset (internal to mcu) has been triggered. icrg registers cop reset rti ipll v ddpll v sspll extal xtal bus clock system reset oscillator clock pllclk oscclk core clock cm fail xclks power on reset low voltage reset cop timeout real time interrupt pll lock interrupt self clock mode interrupt s12x_mmc illegal address reset reset generator clock quality checker clock and reset control voltage regulator clock monitor oscillator
s12xe clocks and reset generator (s12xecrgv1) s12xs family reference manual, rev. 1.10 238 freescale semiconductor 8.3 memory map and registers this section provides a detailed description of all registers accessible in the s12xecrg. 8.3.1 module memory map figure 8-2 gives an overview on all s12xecrg registers. note register address = base address + address offset, where the base address is de?ed at the mcu level and the address offset is de?ed at the module level. address name bit 7 6 5 4 3 2 1 bit 0 0x0000 synr r vcofrq[1:0] syndiv[5:0] w 0x0001 refdv r reffrq[1:0] refdiv[5:0] w 0x0002 postdiv r0 0 0 postdiv[4:0] w 0x0003 crgflg r rtif porf lvrf lockif lock ilaf scmif scm w 0x0004 crgint r rtie 00 lockie 00 scmie 0 w 0x0005 clksel r pllsel pstp xclks 0 pllwai 0 rtiwai copwai w 0x0006 pllctl r cme pllon fm1 fm0 fstwkp pre pce scme w 0x0007 rtictl r rtdec rtr6 rtr5 rtr4 rtr3 rtr2 rtr1 rtr0 w 0x0008 copctl r wcop rsbck 000 cr2 cr1 cr0 w wrtmask 0x0009 forbyp 2 r0 0 0 000 0 0 w 0x000a ctctl 2 r0 0 0 000 0 0 w 0x000b armcop r0 0 0 000 0 0 w bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 2. forbyp and ctctl are intended for factory test purposes only. = unimplemented or reserved figure 8-2. crg register summary
s12xe clocks and reset generator (s12xecrgv1) s12xs family reference manual rev. 1.10 freescale semiconductor 239 8.3.2 register descriptions this section describes in address order all the s12xecrg registers and their individual bits. 8.3.2.1 s12xecrg synthesizer register (synr) the synr register controls the multiplication factor of the ipll and selects the vco frequency range. read: anytime write: anytime except if pllsel = 1 note write to this register initializes the lock detector bit. note f vco must be within the speci?d vco frequency lock range. f. bus (bus clock) must not exceed the speci?d maximum. if postdiv = $00 then f pll is same as f vco (divide by one). the vcofrq[1:0] bit are used to configure the vco gain for optimal stability and lock time. for correct ipll operation the vcofrq[1:0] bits have to be selected according to the actual target vcoclk frequency as shown in table 8-2 . setting the vcofrq[1:0] bits wrong can result in a non functional ipll (no locking and/or insufficient stability). module base + 0x0000 76543210 r vcofrq[1:0] syndiv[5:0] w reset 0 0 0 00000 figure 8-3. s12xecrg synthesizer register (synr) table 8-2. vco clock frequency selection vcoclk frequency ranges vcofrq[1:0] 32mhz <= f vco <= 48mhz 00 48mhz < f vco <= 80mhz 01 reserved 10 80mhz < f vco <= 120mhz 11 f vco 2f osc syndiv 1 + () refdiv 1 + () ------------------------------------- = f pll f vco 2 postdiv ----------------------------------- - = f bus f pll 2 ------------ - =
s12xe clocks and reset generator (s12xecrgv1) s12xs family reference manual, rev. 1.10 240 freescale semiconductor 8.3.2.2 s12xecrg reference divider register (refdv) the refdv register provides a finer granularity for the ipll multiplier steps. read: anytime write: anytime except when pllsel = 1 note write to this register initializes the lock detector bit. the reffrq[1:0] bit are used to configure the internal pll filter for optimal stability and lock time. for correct ipll operation the reffrq[1:0] bits have to be selected according to the actual refclk frequency as shown in figure 8-3 . setting the reffrq[1:0] bits wrong can result in a non functional ipll (no locking and/or insufficient stability). 8.3.2.3 s12xecrg post divider register (postdiv) the postdiv register controls the frequency ratio between the vcoclk and pllclk. the count in the final divider divides vcoclk frequency by 1 or 2*postdiv. note that if postdiv = $00 f pll = f vco (divide by one). module base + 0x0001 76543210 r reffrq[1:0] refdiv[5:0] w reset 0 0 0 00000 figure 8-4. s12xecrg reference divider register (refdv) table 8-3. reference clock frequency selection refclk frequency ranges reffrq[1:0] 1mhz <= f ref <= 2mhz 00 2mhz < f ref <= 6mhz 01 6mhz < f ref <= 12mhz 10 f ref >12mhz 11 f ref f osc refdiv 1 + () ------------------------------------ =
s12xe clocks and reset generator (s12xecrgv1) s12xs family reference manual rev. 1.10 freescale semiconductor 241 read: anytime write: anytime except if pllsel = 1 note if postdiv = $00 then f pll is identical to f vco (divide by one). 8.3.2.4 s12xecrg flags register (crgflg) this register provides s12xecrg status bits and flags. read: anytime write: refer to each bit for individual write conditions module base + 0x0002 76543210 r000 postdiv[4:0] w reset 0 0 0 00000 = unimplemented or reserved figure 8-5. s12xecrg post divider register (postdiv) module base + 0x0003 76543210 r rtif porf lvrf lockif lock ilaf scmif scm w reset 0 note 1 note 2 note 3 0000 1. porf is set to 1 when a power on reset occurs. unaffected by system reset. 2. lvrf is set to 1 when a low voltage reset occurs. unaffected by system reset. 3. ilaf is set to 1 when an illegal address reset occurs. unaffected by system reset. cleared by power on or low voltage reset. = unimplemented or reserved figure 8-6. s12xecrg flags register (crgflg) f pll f vco 2xpostdiv () -------------------------------------- =
s12xe clocks and reset generator (s12xecrgv1) s12xs family reference manual, rev. 1.10 242 freescale semiconductor 8.3.2.5 s12xecrg interrupt enable register (crgint) this register enables s12xecrg interrupt requests. table 8-4. crgflg field descriptions field description 7 rtif real time interrupt flag rtif is set to 1 at the end of the rti period. this ?g can only be cleared by writing a 1. writing a 0 has no effect. if enabled (rtie=1), rtif causes an interrupt request. 0 rti time-out has not yet occurred. 1 rti time-out has occurred. 6 porf power on reset flag porf is set to 1 when a power on reset occurs. this ?g can only be cleared by writing a 1. writing a 0 has no effect. 0 power on reset has not occurred. 1 power on reset has occurred. 5 lvrf low voltage reset flag lvrf is set to 1 when a low voltage reset occurs. this ?g can only be cleared by writing a 1. writing a 0 has no effect. 0 low voltage reset has not occurred. 1 low voltage reset has occurred. 4 lockif ipll lock interrupt flag lockif is set to 1 when lock status bit changes. this ?g can only be cleared by writing a 1. writing a 0 has no effect.if enabled (lockie=1), lockif causes an interrupt request. 0 no change in lock bit. 1 lock bit has changed. 3 lock lock status bit lock re?cts the current state of ipll lock condition. this bit is cleared in self clock mode. writes have no effect. 0 vcoclk is not within the desired tolerance of the target frequency. 1 vcoclk is within the desired tolerance of the target frequency. 2 ilaf illegal address reset flag ilaf is set to 1 when an illegal address reset occurs. refer to s12xmmc block guide for details. this ?g can only be cleared by writing a 1. writing a 0 has no effect. 0 illegal address reset has not occurred. 1 illegal address reset has occurred. 1 scmif self clock mode interrupt flag ?scmif is set to 1 when scm status bit changes. this ?g can only be cleared by writing a 1. writing a 0 has no effect. if enabled (scmie=1), scmif causes an interrupt request. 0 no change in scm bit. 1 scm bit has changed. 0 scm self clock mode status bit ?scm re?cts the current clocking mode. writes have no effect. 0 mcu is operating normally with oscclk available. 1 mcu is operating in self clock mode with oscclk in an unknown state. all clocks are derived from pllclk running at its minimum frequency f scm . module base + 0x0004 76543210 r rtie 00 lockie 00 scmie 0 w reset 0 0 0 00000 = unimplemented or reserved figure 8-7. s12xecrg interrupt enable register (crgint)
s12xe clocks and reset generator (s12xecrgv1) s12xs family reference manual rev. 1.10 freescale semiconductor 243 read: anytime write: anytime 8.3.2.6 s12xecrg clock select register (clksel) this register controls s12xecrg clock selection. refer to figure 8-16 for more details on the effect of each bit. read: anytime write: refer to each bit for individual write conditions table 8-5. crgint field descriptions field description 7 rtie real time interrupt enable bit 0 interrupt requests from rti are disabled. 1 interrupt will be requested whenever rtif is set. 4 lockie lock interrupt enable bit 0 lock interrupt requests are disabled. 1 interrupt will be requested whenever lockif is set. 1 scmie self clock mode interrupt enable bit 0 scm interrupt requests are disabled. 1 interrupt will be requested whenever scmif is set. module base + 0x0005 76543210 r pllsel pstp xclks 0 pllwai 0 rtiwai copwai w reset 0 0 0 00000 = unimplemented or reserved figure 8-8. s12xecrg clock select register (clksel)
s12xe clocks and reset generator (s12xecrgv1) s12xs family reference manual, rev. 1.10 244 freescale semiconductor 8.3.2.7 s12xecrg ipll control register (pllctl) this register controls the ipll functionality. table 8-6. clksel field descriptions field description 7 pllsel pll select bit write: anytime. writing a one when lock=0 has no effect. this prevents the selection of an unstable pllclk as sysclk. pllsel bit is cleared when the mcu enters self clock mode, stop mode or wait mode with pllwai bit set. it is recommended to read back the pllsel bit to make sure pllclk has really been selected as sysclk, as lock status bit could theoretically change at the very moment writing the pllsel bit. 0 system clocks are derived from oscclk (f bus = f osc / 2). 1 system clocks are derived from pllclk (f bus = f pll / 2). 6 pstp pseudo stop bit write: anytime this bit controls the functionality of the oscillator during stop mode. 0 oscillator is disabled in stop mode. 1 oscillator continues to run in stop mode (pseudo stop). note: pseudo stop mode allows for faster stop recovery and reduces the mechanical stress and aging of the resonator in case of frequent stop conditions at the expense of a slightly increased power consumption. 5 xclks oscillator con?uration status bit ?this read-only bit shows the oscillator con?uration status. 0 loop controlled pierce oscillator is selected. 1 external clock / full swing pierce oscillator is selected. 3 pllwai pll stops in wait mode bit write: anytime if pllwai is set, the s12xecrg will clear the pllsel bit before entering wait mode. the pllon bit remains set during wait mode but the ipll is powered down. upon exiting wait mode, the pllsel bit has to be set manually if pll clock is required. 0 ipll keeps running in wait mode. 1 ipll stops in wait mode. 1 rtiwai rti stops in wait mode bit write: anytime 0 rti keeps running in wait mode. 1 rti stops and initializes the rti dividers whenever the part goes into wait mode. 0 copwai cop stops in wait mode bit normal modes: write once special modes: write anytime 0 cop keeps running in wait mode. 1 cop stops and initializes the cop counter whenever the part goes into wait mode. module base + 0x0006 76543210 r cme pllon fm1 fm0 fstwkp pre pce scme w reset 1 1 0 00001 figure 8-9. s12xecrg ipll control register (pllctl)
s12xe clocks and reset generator (s12xecrgv1) s12xs family reference manual rev. 1.10 freescale semiconductor 245 read: anytime write: refer to each bit for individual write conditions table 8-7. pllctl field descriptions field description 7 cme clock monitor enable bit ?cme enables the clock monitor. write anytime except when scm = 1. 0 clock monitor is disabled. 1 clock monitor is enabled. slow or stopped clocks will cause a clock monitor reset sequence or self clock mode. note: operating with cme=0 will not detect any loss of clock. in case of poor clock quality this could cause unpredictable operation of the mcu! in stop mode (pstp=0) the clock monitor is disabled independently of the cme bit setting and any loss of external clock will not be detected. also after wake-up from stop mode (pstp = 0) with fast wake-up enabled (fstwkp = 1) the clock monitor is disabled independently of the cme bit setting and any loss of external clock will not be detected. 6 pllon phase lock loop on bit pllon turns on the ipll circuitry. in self clock mode, the ipll is turned on, but the pllon bit reads the last written value. write anytime except when pllsel = 1. 0 ipll is turned off. 1 ipll is turned on. 5, 4 fm1, fm0 ipll frequency modulation enable bit ?fm1 and fm0 enable additional frequency modulation on the vcoclk. this is to reduce noise emission. the modulation frequency is f ref divided by 16. write anytime except when pllsel = 1. see table 8-8 for coding. 3 fstwkp fast wake-up from full stop bit fstwkp enables fast wake-up from full stop mode. write anytime. if self- clock mode is disabled (scme = 0) this bit has no effect. 0 fast wake-up from full stop mode is disabled. 1 fast wake-up from full stop mode is enabled. when waking up from full stop mode the system will immediately resume operation in self-clock mode (see section 8.4.1.4, ?lock quality checker ). the scmif ?g will not be set. the system will remain in self-clock mode with oscillator and clock monitor disabled until fstwkp bit is cleared. the clearing of fstwkp will start the oscillator, the clock monitor and the clock quality check. if the clock quality check is successful, the s12xecrg will switch all system clocks to oscclk. the scmif ?g will be set. see application examples in figure 8-19 and figure 8-20 . 2 pre rti enable during pseudo stop bit ?pre enables the rti during pseudo stop mode. write anytime. 0 rti stops running during pseudo stop mode. 1 rti continues running during pseudo stop mode. note: if the pre bit is cleared the rti dividers will go static while pseudo stop mode is active. the rti dividers will not initialize like in wait mode with rtiwai bit set. 1 pce cop enable during pseudo stop bit ?pce enables the cop during pseudo stop mode. write anytime. 0 cop stops running during pseudo stop mode 1 cop continues running during pseudo stop mode note: if the pce bit is cleared the cop dividers will go static while pseudo stop mode is active. the cop dividers will not initialize like in wait mode with copwai bit set. 0 scme self clock mode enable bit normal modes: write once special modes: write anytime scme can not be cleared while operating in self clock mode (scm = 1). 0 detection of crystal clock failure causes clock monitor reset (see section 8.5.1.1, ?lock monitor reset ). 1 detection of crystal clock failure forces the mcu in self clock mode (see section 8.4.2.2, ?elf clock mode ).
s12xe clocks and reset generator (s12xecrgv1) s12xs family reference manual, rev. 1.10 246 freescale semiconductor 8.3.2.8 s12xecrg rti control register (rtictl) this register selects the timeout period for the real time interrupt. read: anytime write: anytime note a write to this register initializes the rti counter. table 8-8. fm amplitude selection fm1 fm0 fm amplitude / f vco variation 0 0 fm off 01 1% 10 2% 11 4% module base + 0x0007 76543210 r rtdec rtr6 rtr5 rtr4 rtr3 rtr2 rtr1 rtr0 w reset 0 0 0 00000 figure 8-10. s12xecrg rti control register (rtictl) table 8-9. rtictl field descriptions field description 7 rtdec decimal or binary divider select bit ?rtdec selects decimal or binary based prescaler values. 0 binary based divider value. see table 8-10 1 decimal based divider value. see table 8-11 6? rtr[6:4] real time interrupt prescale rate select bits these bits select the prescale rate for the rti. see ta bl e 8 - 10 and table 8-11 . 3? rtr[3:0] real time interrupt modulus counter select bits ?these bits select the modulus counter target value to provide additional granularity. table 8-10 and table 8-11 show all possible divide values selectable by the rtictl register. the source clock for the rti is oscclk. table 8-10. rti frequency divide rates for rtdec = 0 rtr[3:0] rtr[6:4] = 000 (off) 001 (2 10 ) 010 (2 11 ) 011 (2 12 ) 100 (2 13 ) 101 (2 14 ) 110 (2 15 ) 111 (2 16 ) 0000 ( 1) off 1 2 10 2 11 2 12 2 13 2 14 2 15 2 16
s12xe clocks and reset generator (s12xecrgv1) s12xs family reference manual rev. 1.10 freescale semiconductor 247 0001 ( 2) off 2x2 10 2x2 11 2x2 12 2x2 13 2x2 14 2x2 15 2x2 16 0010 ( 3) off 3x2 10 3x2 11 3x2 12 3x2 13 3x2 14 3x2 15 3x2 16 0011 ( 4) off 4x2 10 4x2 11 4x2 12 4x2 13 4x2 14 4x2 15 4x2 16 0100 ( 5) off 5x2 10 5x2 11 5x2 12 5x2 13 5x2 14 5x2 15 5x2 16 0101 ( 6) off 6x2 10 6x2 11 6x2 12 6x2 13 6x2 14 6x2 15 6x2 16 0110 ( 7) off 7x2 10 7x2 11 7x2 12 7x2 13 7x2 14 7x2 15 7x2 16 0111 ( 8) off 8x2 10 8x2 11 8x2 12 8x2 13 8x2 14 8x2 15 8x2 16 1000 ( 9) off 9x2 10 9x2 11 9x2 12 9x2 13 9x2 14 9x2 15 9x2 16 1001 ( 10) off 10x2 10 10x2 11 10x2 12 10x2 13 10x2 14 10x2 15 10x2 16 1010 ( 11) off 11x2 10 11x2 11 11x2 12 11x2 13 11x2 14 11x2 15 11x2 16 1011 ( 12) off 12x2 10 12x2 11 12x2 12 12x2 13 12x2 14 12x2 15 12x2 16 1100 ( 13) off 13x2 10 13x2 11 13x2 12 13x2 13 13x2 14 13x2 15 13x2 16 1101 ( 14) off 14x2 10 14x2 11 14x2 12 14x2 13 14x2 14 14x2 15 14x2 16 1110 ( 15) off 15x2 10 15x2 11 15x2 12 15x2 13 15x2 14 15x2 15 15x2 16 1111 ( 16) off 16x2 10 16x2 11 16x2 12 16x2 13 16x2 14 16x2 15 16x2 16 1 denotes the default value out of reset.this value should be used to disable the rti to ensure future backwards compatibility. table 8-11. rti frequency divide rates for rtdec=1 rtr[3:0] rtr[6:4] = 000 (1x10 3 ) 001 (2x10 3 ) 010 (5x10 3 ) 011 (10x10 3 ) 100 (20x10 3 ) 101 (50x10 3 ) 110 (100x10 3 ) 111 (200x10 3 ) 0000 ( 1) 1x10 3 2x10 3 5x10 3 10x10 3 20x10 3 50x10 3 100x10 3 200x10 3 0001 ( 2) 2x10 3 4x10 3 10x10 3 20x10 3 40x10 3 100x10 3 200x10 3 400x10 3 0010 ( 3) 3x10 3 6x10 3 15x10 3 30x10 3 60x10 3 150x10 3 300x10 3 600x10 3 0011 ( 4) 4x10 3 8x10 3 20x10 3 40x10 3 80x10 3 200x10 3 400x10 3 800x10 3 0100 ( 5) 5x10 3 10x10 3 25x10 3 50x10 3 100x10 3 250x10 3 500x10 3 1x10 6 0101 ( 6) 6x10 3 12x10 3 30x10 3 60x10 3 120x10 3 300x10 3 600x10 3 1.2x10 6 table 8-10. rti frequency divide rates for rtdec = 0 rtr[3:0] rtr[6:4] = 000 (off) 001 (2 10 ) 010 (2 11 ) 011 (2 12 ) 100 (2 13 ) 101 (2 14 ) 110 (2 15 ) 111 (2 16 )
s12xe clocks and reset generator (s12xecrgv1) s12xs family reference manual, rev. 1.10 248 freescale semiconductor 8.3.2.9 s12xecrg cop control register (copctl) this register controls the cop (computer operating properly) watchdog. read: anytime write: 1. rsbck: anytime in special modes; write to ??but not to ??in all other modes 2. wcop, cr2, cr1, cr0: anytime in special modes write once in all other modes writing cr[2:0] to ?00?has no effect, but counts for the ?rite once?condition. writing wcop to ??has no effect, but counts for the ?rite once?condition. 0110 ( 7) 7x10 3 14x10 3 35x10 3 70x10 3 140x10 3 350x10 3 700x10 3 1.4x10 6 0111 ( 8) 8x10 3 16x10 3 40x10 3 80x10 3 160x10 3 400x10 3 800x10 3 1.6x10 6 1000 ( 9) 9x10 3 18x10 3 45x10 3 90x10 3 180x10 3 450x10 3 900x10 3 1.8x10 6 1001 ( 10) 10 x10 3 20x10 3 50x10 3 100x10 3 200x10 3 500x10 3 1x10 6 2x10 6 1010 ( 11) 11 x10 3 22x10 3 55x10 3 110x10 3 220x10 3 550x10 3 1.1x10 6 2.2x10 6 1011 ( 12) 12x10 3 24x10 3 60x10 3 120x10 3 240x10 3 600x10 3 1.2x10 6 2.4x10 6 1100 ( 13) 13x10 3 26x10 3 65x10 3 130x10 3 260x10 3 650x10 3 1.3x10 6 2.6x10 6 1101 ( 14) 14x10 3 28x10 3 70x10 3 140x10 3 280x10 3 700x10 3 1.4x10 6 2.8x10 6 1110 ( 15) 15x10 3 30x10 3 75x10 3 150x10 3 300x10 3 750x10 3 1.5x10 6 3x10 6 1111 ( 16) 16x10 3 32x10 3 80x10 3 160x10 3 320x10 3 800x10 3 1.6x10 6 3.2x10 6 module base + 0x0008 76543210 r wcop rsbck 000 cr2 cr1 cr0 w wrtmask reset 1 00000000 1. refer to device user guide (section: s12xecrg) for reset values of wcop, cr2, cr1 and cr0. = unimplemented or reserved figure 8-11. s12xecrg cop control register (copctl) table 8-11. rti frequency divide rates for rtdec=1 rtr[3:0] rtr[6:4] = 000 (1x10 3 ) 001 (2x10 3 ) 010 (5x10 3 ) 011 (10x10 3 ) 100 (20x10 3 ) 101 (50x10 3 ) 110 (100x10 3 ) 111 (200x10 3 )
s12xe clocks and reset generator (s12xecrgv1) s12xs family reference manual rev. 1.10 freescale semiconductor 249 the cop time-out period is restarted if one these two conditions is true: 1. writing a non zero value to cr[2:0] (anytime in special modes, once in all other modes) with wrtmask = 0. or 2. changing rsbck bit from ??to ?? table 8-12. copctl field descriptions field description 7 wcop window cop mode bit when set, a write to the armcop register must occur in the last 25% of the selected period. a write during the ?st 75% of the selected period will reset the part. as long as all writes occur during this window, $55 can be written as often as desired. once $aa is written after the $55, the time-out logic restarts and the user must wait until the next window before writing to armcop. table 8-13 shows the duration of this window for the seven available cop rates. 0 normal cop operation 1 window cop operation 6 rsbck cop and rti stop in active bdm mode bit 0 allows the cop and rti to keep running in active bdm mode. 1 stops the cop and rti counters whenever the part is in active bdm mode. 5 wrtmask write mask for wcop and cr[2:0] bit this write-only bit serves as a mask for the wcop and cr[2:0] bits while writing the copctl register. it is intended for bdm writing the rsbck without touching the contents of wcop and cr[2:0]. 0 write of wcop and cr[2:0] has an effect with this write of copctl 1 write of wcop and cr[2:0] has no effect with this write of copctl. (does not count for ?rite once?) 2? cr[2:0] cop watchdog timer rate select ?these bits select the cop time-out rate (see table 8-13 ). writing a nonzero value to cr[2:0] enables the cop counter and starts the time-out period. a cop counter time-out causes a system reset. this can be avoided by periodically (before time-out) reinitialize the cop counter via the armcop register. while all of the following four conditions are true the cr[2:0], wcop bits are ignored and the cop operates at highest time-out period ( 2 24 cycles) in normal cop mode (window cop mode disabled): 1) cop is enabled (cr[2:0] is not 000) 2) bdm mode active 3) rsbck = 0 4) operation in emulation or special modes table 8-13. cop watchdog rates 1 cr2 cr1 cr0 oscclk cycles to timeout 0 0 0 cop disabled 001 2 14 010 2 16 011 2 18 100 2 20 101 2 22 110 2 23
s12xe clocks and reset generator (s12xecrgv1) s12xs family reference manual, rev. 1.10 250 freescale semiconductor 8.3.2.10 reserved register (forbyp) note this reserved register is designed for factory test purposes only, and is not intended for general user access. writing to this register when in special modes can alter the s12xecrgs functionality. read: always read $00 except in special modes write: only in special modes 8.3.2.11 reserved register (ctctl) note this reserved register is designed for factory test purposes only, and is not intended for general user access. writing to this register when in special test modes can alter the s12xecrgs functionality. read: always read $00 except in special modes 111 2 24 1 oscclk cycles are referenced from the previous cop time-out reset (writing $55/$aa to the armcop register) module base + 0x0009 76543210 r00000000 w reset 0 0 0 00000 = unimplemented or reserved figure 8-12. reserved register (forbyp) module base + 0x000a 76543210 r00000000 w reset 0 0 0 00000 = unimplemented or reserved figure 8-13. reserved register (ctctl) table 8-13. cop watchdog rates 1 cr2 cr1 cr0 oscclk cycles to timeout
s12xe clocks and reset generator (s12xecrgv1) s12xs family reference manual rev. 1.10 freescale semiconductor 251 write: only in special modes 8.3.2.12 s12xecrg cop timer arm/reset register (armcop) this register is used to restart the cop time-out period. read: always reads $00 write: anytime when the cop is disabled (cr[2:0] = ?00? writing to this register has no effect. when the cop is enabled by setting cr[2:0] nonzero, the following applies: writing any value other than $55 or $aa causes a cop reset. to restart the cop time-out period you must write $55 followed by a write of $aa. other instructions may be executed between these writes but the sequence ($55, $aa) must be completed prior to cop end of time-out period to avoid a cop reset. sequences of $55 writes or sequences of $aa writes are allowed. when the wcop bit is set, $55 and $aa writes must be done in the last 25% of the selected time-out period; writing any value in the ?st 75% of the selected period will cause a cop reset. module base + 0x000b 76543210 r00000000 w bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset 0 0 0 00000 figure 8-14. s12xecrg armcop register diagram
s12xe clocks and reset generator (s12xecrgv1) s12xs family reference manual, rev. 1.10 252 freescale semiconductor 8.4 functional description 8.4.1 functional blocks 8.4.1.1 phase locked loop with internal filter (ipll) the ipll is used to run the mcu from a different time base than the incoming oscclk. figure 8-15 shows a block diagram of the ipll. figure 8-15. ipll functional diagram for increased flexibility, oscclk can be divided in a range of 1 to 64 to generate the reference frequency refclk using the refdiv[5:0] bits. this offers a finer multiplication granularity. based on the syndiv[5:0] bits the ipll generates the vcoclk by multiplying the reference clock by a multiple of 2, 4, 6,... 126, 128. based on the postdiv[4:0] bits the vcoclk can be divided in a range of 1,2,4,6,8,... to 62 to generate the pllclk. . note although it is possible to set the dividers to command a very high clock frequency, do not exceed the speci?d bus frequency limit for the mcu. if (pllsel = 1) then f bus = f pll / 2. if postdiv = $00 the f pll is identical to f vco (divide by one) several examples of ipll divider settings are shown in table 8-14 . shaded rows indicated that these settings are not recommended. the following rules help to achieve optimum stability and shortest lock time: use lowest possible f vco / f ref ratio (syndiv value). use highest possible refclk frequency f ref . reduced consumption oscillator extal xtal oscclk pllclk reference programmable divider pdet phase detector refdiv[5:0] loop programmable divider syndiv[5:0] vco lock up down lock detector refclk fbclk v ddpll /v sspll clock monitor v ddpll /v sspll v dd /v ss supplied by: cpump and filter post programmable divider postdiv[4:0] vcoclk f pll 2f osc syndiv 1 + refdiv 1 + [] 2 postdiv [] ------------------------------------------------------------------------------ =
s12xe clocks and reset generator (s12xecrgv1) s12xs family reference manual rev. 1.10 freescale semiconductor 253 8.4.1.1.1 ipll operation the oscillator output clock signal (oscclk) is fed through the reference programmable divider and is divided in a range of 1 to 64 (refdiv+1) to output the refclk. the vco output clock, (vcoclk) is fed back through the programmable loop divider and is divided in a range of 2 to 128 in increments of [2 x (syndiv +1)] to output the fbclk. the vcoclk is fed to the final programmable divider and is divided in a range of 1,2,4,6,8,... to 62 (2*postdiv) to output the pllclk. see figure 8-15 . the phase detector then compares the fbclk, with the refclk. correction pulses are generated based on the phase difference between the two signals. the loop filter then slightly alters the dc voltage on the internal filter capacitor, based on the width and direction of the correction pulse. the user must select the range of the refclk frequency and the range of the vcoclk frequency to ensure that the correct ipll loop bandwidth is set. the lock detector compares the frequencies of the fbclk, and the refclk. therefore, the speed of the lock detector is directly proportional to the reference clock frequency. the circuit determines the lock condition based on this comparison. if ipll lock interrupt requests are enabled, the software can wait for an interrupt request and then check the lock bit. if interrupt requests are disabled, software can poll the lock bit continuously (during ipll start-up, usually) or at periodic intervals. in either case, only when the lock bit is set, the pllclk can be selected as the source for the system and core clocks. if the ipll is selected as the source for the system and core clocks and the lock bit is clear, the ipll has suffered a severe noise hit and the software must take appropriate action, depending on the application. the lock bit is a read-only indicator of the locked state of the ipll. the lock bit is set when the vco frequency is within a certain tolerance, ? lock , and is cleared when the vco frequency is out of a certain tolerance, ? unl . interrupt requests can occur if enabled (lockie = 1) when the lock condition changes, toggling the lock bit. table 8-14. examples of ipll divider settings f osc refdiv[5:0] f ref reffrq[1:0] syndiv[5:0] f vco vcofrq[1:0] postdiv[4:0] f pll f bus 4mhz $01 2mhz 01 $18 100mhz 11 $00 100mhz 50 mhz 8mhz $03 2mhz 01 $18 100mhz 11 $00 100mhz 50 mhz 4mhz $00 4mhz 01 $09 80mhz 01 $00 80mhz 40mhz 8mhz $00 8mhz 10 $04 80mhz 01 $00 80mhz 40mhz 4mhz $00 4mhz 01 $03 32mhz 00 $01 16mhz 8mhz 4mhz $01 2mhz 01 $18 100mhz 11 $01 50mhz 25mhz 4mhz $03 1mhz 00 $18 50mhz 01 $00 50mhz 25mhz 4mhz $03 1mhz 00 $31 100mhz 11 $01 50mhz 25mhz
s12xe clocks and reset generator (s12xecrgv1) s12xs family reference manual, rev. 1.10 254 freescale semiconductor 8.4.1.2 system clocks generator figure 8-16. system clocks generator the clock generator creates the clocks used in the mcu (see figure 8-16 ). the gating condition placed on top of the individual clock gates indicates the dependencies of different modes (stop, wait) and the setting of the respective configuration bits. the peripheral modules use the bus clock. some peripheral modules also use the oscillator clock. if the mcu enters self clock mode (see section 8.4.2.2, ?elf clock mode ) oscillator clock source is switched to pllclk running at its minimum frequency f scm . the bus clock is used to generate the clock visible at the eclk pin. the core clock signal is the clock for the cpu. the core clock is twice the bus clock. but note that a cpu cycle corresponds to one bus clock. ipll clock mode is selected with pllsel bit in the clksel register. when selected, the ipll output clock drives sysclk for the main system including the cpu and peripherals. the ipll cannot be turned off by clearing the pllon bit, if the ipll clock is selected. when pllsel is changed, it takes a maximum of 4 oscclk plus 4 pllclk cycles to make the transition. during the transition, all clocks freeze and cpu activity ceases. oscillator phase lock loop (iipll) extal xtal sysclk rti oscclk pllclk clock phase generator bus clock clock monitor 1 0 pllsel or scm 2 core clock cop oscillator = clock gate gating condition wait(rtiwai), stop( pstp, pre), rti enable wait(copwai), stop( pstp, pce), cop enable stop 1 0 scm clock stop
s12xe clocks and reset generator (s12xecrgv1) s12xs family reference manual rev. 1.10 freescale semiconductor 255 8.4.1.3 clock monitor (cm) if no oscclk edges are detected within a certain time, the clock monitor within the oscillator block generates a clock monitor fail event. the s12xecrg then asserts self clock mode or generates a system reset depending on the state of scme bit. if the clock monitor is disabled or the presence of clocks is detected no failure is indicated by the oscillator block.the clock monitor function is enabled/disabled by the cme control bit. 8.4.1.4 clock quality checker the clock monitor performs a coarse check on the incoming clock signal. the clock quality checker provides a more accurate check in addition to the clock monitor. a clock quality check is triggered by any of the following events: power on reset ( por ) low voltage reset ( lvr ) wake-up from full stop mode ( exit full stop ) clock monitor fail indication ( cm fail ) a time window of 50000 pllclk cycles 1 is called check window . a number greater equal than 4096 rising oscclk edges within a check window is called osc ok . note that osc ok immediately terminates the current check window . see figure 8-17 as an example. figure 8-17. check window example 1. ipll is running at self clock mode frequency f scm . 12 49999 50000 pllclk check window 12345 4095 4096 3 oscclk osc ok
s12xe clocks and reset generator (s12xecrgv1) s12xs family reference manual, rev. 1.10 256 freescale semiconductor the sequence for clock quality check is shown in figure 8-18 . figure 8-18. sequence for clock quality check note remember that in parallel to additional actions caused by self clock mode or clock monitor reset 1 handling the clock quality checker continues to check the oscclk signal. note the clock quality checker enables the ipll and the voltage regulator (vreg) anytime a clock check has to be performed. an ongoing clock quality check could also cause a running ipll (f scm ) and an active vreg during pseudo stop mode. 1. a clock monitor reset will always set the scme bit to logical?? check window osc ok ? scm active? switch to oscclk exit scm clock ok num = 50 num > 0 ? num = num-1 yes no yes scme = 1 ? no enter scm scm active? yes clock monitor reset no yes no num = 0 yes no por exit full stop cm fail lvr scme=1 & ? fstwkp=1 yes no ? fstwkp = 0 no num = 0 enter scm yes
s12xe clocks and reset generator (s12xecrgv1) s12xs family reference manual rev. 1.10 freescale semiconductor 257 8.4.1.5 computer operating properly watchdog (cop) the cop (free running watchdog timer) enables the user to check that a program is running and sequencing properly. when the cop is being used, software is responsible for keeping the cop from timing out. if the cop times out it is an indication that the software is no longer being executed in the intended sequence; thus a system reset is initiated (see section 8.4.1.5, ?omputer operating properly watchdog (cop) ). the cop runs with a gated oscclk. three control bits in the copctl register allow selection of seven cop time-out periods. when cop is enabled, the program must write $55 and $aa (in this order) to the armcop register during the selected time-out period. once this is done, the cop time-out period is restarted. if the program fails to do this and the cop times out, the part will reset. also, if any value other than $55 or $aa is written, the part is immediately reset. windowed cop operation is enabled by setting wcop in the copctl register. in this mode, writes to the armcop register to clear the cop timer must occur in the last 25% of the selected time-out period. a premature write will immediately reset the part. if pce bit is set, the cop will continue to run in pseudo stop mode. 8.4.1.6 real time interrupt (rti) the rti can be used to generate a hardware interrupt at a fixed periodic rate. if enabled (by setting rtie=1), this interrupt will occur at the rate selected by the rtictl register. the rti runs with a gated oscclk. at the end of the rti time-out period the rtif flag is set to one and a new rti time-out period starts immediately. a write to the rtictl register restarts the rti time-out period. if the pre bit is set, the rti will continue to run in pseudo stop mode. 8.4.2 operation modes 8.4.2.1 normal mode the s12xecrg block behaves as described within this specification in all normal modes. 8.4.2.2 self clock mode if the external clock frequency is not available due to a failure or due to long crystal start-up time, the bus clock and the core clock are derived from the pllclk running at self clock mode frequency f scm ; this mode of operation is called self clock mode. this requires cme = 1 and scme = 1, which is the default after reset. if the mcu was clocked by the pllclk prior to entering self clock mode, the pllsel bit will be cleared. if the external clock signal has stabilized again, the s12xecrg will automatically select oscclk to be the system clock and return to normal mode. see section 8.4.1.4, ?lock quality checker for more information on entering and leaving self clock mode.
s12xe clocks and reset generator (s12xecrgv1) s12xs family reference manual, rev. 1.10 258 freescale semiconductor note in order to detect a potential clock loss the cme bit should always be enabled (cme = 1). if cme bit is disabled and the mcu is con?ured to run on pllclk, a loss of external clock (oscclk) will not be detected and will cause the system clock to drift towards lower frequencies. as soon as the external clock is available again the system clock ramps up to its ipll target frequency. if the mcu is running on external clock any loss of clock will cause the system to go static. 8.4.3 low power options this section summarizes the low power options available in the s12xecrg. 8.4.3.1 run mode this is the default mode after reset. the rti can be stopped by setting the associated rate select bits to zero. the cop can be stopped by setting the associated rate select bits to zero. 8.4.3.2 wait mode the wai instruction puts the mcu in a low power consumption stand-by mode depending on setting of the individual bits in the clksel register. all individual wait mode configuration bits can be superposed. this provides enhanced granularity in reducing the level of power consumption during wait mode. table 8-15 lists the individual configuration bits and the parts of the mcu that are affected in wait mode. after executing the wai instruction the core requests the s12xecrg to switch mcu into wait mode. the s12xecrg then checks whether the pllwai bit is asserted. depending on the configuration the s12xecrg switches the system and core clocks to oscclk by clearing the pllsel bit and disables the ipll. there are two ways to restart the mcu from wait mode: 1. any reset 2. any interrupt table 8-15. mcu con?uration during wait mode pllwai rtiwai copwai ipll stopped rti stopped cop stopped
s12xe clocks and reset generator (s12xecrgv1) s12xs family reference manual rev. 1.10 freescale semiconductor 259 8.4.3.3 stop mode all clocks are stopped in stop mode, dependent of the setting of the pce, pre and pstp bit. the oscillator is disabled in stop mode unless the pstp bit is set. if the pre or pce bits are set, the rti or cop continues to run in pseudo stop mode. in addition to disabling system and core clocks the s12xecrg requests other functional units of the mcu (e.g. voltage-regulator) to enter their individual power saving modes (if available). if the pllsel bit is still set when entering stop mode, the s12xecrg will switch the system and core clocks to oscclk by clearing the pllsel bit. then the s12xecrg disables the ipll, disables the core clock and finally disables the remaining system clocks. if pseudo stop mode is entered from self-clock mode the s12xecrg will continue to check the clock quality until clock check is successful. in this case the ipll and the voltage regulator (vreg) will remain enabled. if full stop mode (pstp = 0) is entered from self-clock mode the ongoing clock quality check will be stopped. a complete timeout window check will be started when stop mode is left again. there are two ways to restart the mcu from stop mode: 1. any reset 2. any interrupt if the mcu is woken-up from full stop mode by an interrupt and the fast wake-up feature is enabled (fstwkp=1 and scme=1), the system will immediately (no clock quality check) resume operation in self-clock mode (see section 8.4.1.4, ?lock quality checker ). the scmif flag will not be set for this special case. the system will remain in self-clock mode with oscillator disabled until fstwkp bit is cleared. the clearing of fstwkp will start the oscillator and the clock quality check. if the clock quality check is successful, the s12xecrg will switch all system clocks to oscillator clock. the scmif flag will be set. see application examples in figure 8-19 and figure 8-20 . because the ipll has been powered-down during stop mode the pllsel bit is cleared and the mcu runs on oscclk after leaving stop-mode. the software must manually set the pllsel bit again, in order to switch system and core clocks to the pllclk. note in full stop mode or self-clock mode caused by the fast wake-up feature the clock monitor and the oscillator are disabled.
s12xe clocks and reset generator (s12xecrgv1) s12xs family reference manual, rev. 1.10 260 freescale semiconductor figure 8-19. fast wake-up from full stop mode: example 1 . figure 8-20. fast wake-up from full stop mode: example 2 8.5 resets all reset sources are listed in table 8-16 . refer to mcu specification for related vector addresses and priorities. table 8-16. reset summary reset source local enable power on reset none low voltage reset none external reset none illegal address reset none clock monitor reset pllctl (cme=1, scme=0) oscillator clock pll clock core clock instruction stop irq service fstwkp=1 irq service stop stop irq service oscillator disabled power saving self-clock mode scme=1 cpu resumes program execution immediately interrupt interrupt interrupt oscillator clock pll clock core clock instruction clock quality check stop irq service fstwkp=1 irq interrupt fstwkp=0 scmie=1 osc startup oscillator disabled cpu resumes program execution immediately self-clock mode scme=1 frequent uncritical instructions frequent critical instructions possible scm interrupt
s12xe clocks and reset generator (s12xecrgv1) s12xs family reference manual rev. 1.10 freescale semiconductor 261 8.5.1 description of reset operation the reset sequence is initiated by any of the following events: low level is detected at the reset pin (external reset). power on is detected. low voltage is detected. illegal address reset is detected (see s12xmmc block guide for details). cop watchdog times out. clock monitor failure is detected and self-clock mode was disabled (scme=0). upon detection of any reset event, an internal circuit drives the reset pin low for 128 sysclk cycles (see figure 8-21 ). since entry into reset is asynchronous it does not require a running sysclk. however, the internal reset circuit of the s12xecrg cannot sequence out of current reset condition without a running sysclk. the number of 128 sysclk cycles might be increased by n = 3 to 6 additional sysclk cycles depending on the internal synchronization latency. after 128+n sysclk cycles the reset pin is released. the reset generator of the s12xecrg waits for additional 64 sysclk cycles and then samples the reset pin to determine the originating source. table 8-17 shows which vector will be fetched. note external circuitry connected to the reset pin should be able to raise the signal to a valid logic one within 64 sysclk cycles after the low drive is released by the mcu. if this requirement is not adhered to the reset source will always be recognized as ?xternal reset even if the reset was initially caused by an other reset source. cop watchdog reset copctl (cr[2:0] nonzero) table 8-17. reset vector selection sampled reset pin (64 cycles after release) clock monitor reset pending cop reset pending vector fetch 1 0 0 por / lvr / illegal address reset/ external reset 1 1 x clock monitor reset 1 0 1 cop reset 0 x x por / lvr / illegal address reset/ external reset with rise of reset pin table 8-16. reset summary reset source local enable
s12xe clocks and reset generator (s12xecrgv1) s12xs family reference manual, rev. 1.10 262 freescale semiconductor the internal reset of the mcu remains asserted while the reset generator completes the 192 sysclk long reset sequence. in case the reset pin is externally driven low for more than these 192 sysclk cycles (external reset), the internal reset remains asserted longer. figure 8-21. reset timing 8.5.1.1 clock monitor reset the s12xecrg generates a clock monitor reset in case all of the following conditions are true: clock monitor is enabled (cme = 1) loss of clock is detected self-clock mode is disabled (scme = 0). the reset event asynchronously forces the configuration registers to their default settings. in detail the cme and the scme are reset to logical ? (which changes the state of the scme bit. as a consequence the s12xecrg immediately enters self clock mode and starts its internal reset sequence. in parallel the clock quality check starts. as soon as clock quality check indicates a valid oscillator clock the s12xecrg switches to oscclk and leaves self clock mode. since the clock quality checker is running in parallel to the reset generator, the s12xecrg may leave self clock mode while still completing the internal reset sequence. 8.5.1.2 computer operating properly watchdog (cop) reset when cop is enabled, the s12xecrg expects sequential write of $55 and $aa (in this order) to the armcop register during the selected time-out period. once this is done, the cop time-out period restarts. if the program fails to do this the s12xecrg will generate a reset. 8.5.1.3 power on reset, low voltage reset the on-chip voltage regulator detects when v dd to the mcu has reached a certain level and asserts power on reset or low voltage reset or both. as soon as a power on reset or low voltage reset is triggered the ) ( ) ( ) ( ) sysclk 128+ n cycles 64 cycles with n being min 3 / max 6 cycles depending on internal synchronization delay icrg drives reset pin low possibly sysclk not running possibly reset driven low externally ) ( ( reset reset pin released
s12xe clocks and reset generator (s12xecrgv1) s12xs family reference manual rev. 1.10 freescale semiconductor 263 s12xecrg performs a quality check on the incoming clock signal. as soon as clock quality check indicates a valid oscillator clock signal the reset sequence starts using the oscillator clock. if after 50 check windows the clock quality check indicated a non-valid oscillator clock the reset sequence starts using self-clock mode. figure 8-22 and figure 8-23 show the power-up sequence for cases when the reset pin is tied to v dd and when the reset pin is held low. figure 8-22. reset pin tied to v dd (by a pull-up resistor) figure 8-23. reset pin held low externally 8.6 interrupts the interrupts/reset vectors requested by the s12xecrg are listed in table 8-18 . refer to mcu specification for related vector addresses and priorities. table 8-18. s12xecrg interrupt vectors interrupt source ccr mask local enable real time interrupt i bit crgint (rtie) lock interrupt i bit crgint (lockie) scm interrupt i bit crgint (scmie) reset internal por 128 sysclk 64 sysclk internal reset clock quality check (no self-clock mode) ) ( ) ( ) ( clock quality check reset internal por internal reset 128 sysclk 64 sysclk (no self clock mode) ) ( ) ( ) (
s12xe clocks and reset generator (s12xecrgv1) s12xs family reference manual, rev. 1.10 264 freescale semiconductor 8.6.1 description of interrupt operation 8.6.1.1 real time interrupt the s12xecrg generates a real time interrupt when the selected interrupt time period elapses. rti interrupts are locally disabled by setting the rtie bit to zero. the real time interrupt flag (rtif) is set to1 when a timeout occurs, and is cleared to 0 by writing a 1 to the rtif bit. the rti continues to run during pseudo stop mode if the pre bit is set to 1. this feature can be used for periodic wakeup from pseudo stop if the rti interrupt is enabled. 8.6.1.2 ipll lock interrupt the s12xecrg generates a ipll lock interrupt when the lock condition of the ipll has changed, either from a locked state to an unlocked state or vice versa. lock interrupts are locally disabled by setting the lockie bit to zero. the ipll lock interrupt flag (lockif) is set to1 when the lock condition has changed, and is cleared to 0 by writing a 1 to the lockif bit. 8.6.1.3 self clock mode interrupt the s12xecrg generates a self clock mode interrupt when the scm condition of the system has changed, either entered or exited self clock mode. scm conditions are caused by a failing clock quality check after power on reset (por) or low voltage reset (lvr) or recovery from full stop mode (pstp = 0) or clock monitor failure. for details on the clock quality check refer to section 8.4.1.4, ?lock quality checker . if the clock monitor is enabled (cme = 1) a loss of external clock will also cause a scm condition (scme = 1). scm interrupts are locally disabled by setting the scmie bit to zero. the scm interrupt flag (scmif) is set to1 when the scm condition has changed, and is cleared to 0 by writing a 1 to the scmif bit.
s12xs family reference manual, rev. 1.10 freescale semiconductor 265 chapter 9 pierce oscillator (s12xosclcpv2) 9.1 introduction the pierce oscillator (xosc) module provides a robust, low-noise and low-power clock source. the module will be operated from the v ddpll supply rail (1.8 v nominal) and require the minimum number of external components. it is designed for optimal start-up margin with typical crystal oscillators. 9.1.1 features the xosc will contain circuitry to dynamically control current gain in the output amplitude. this ensures a signal with low harmonic distortion, low power and good noise immunity. high noise immunity due to input hysteresis low rf emissions with peak-to-peak swing limited dynamically transconductance (gm) sized for optimum start-up margin for typical oscillators dynamic gain control eliminates the need for external current limiting resistor integrated resistor eliminates the need for external bias resistor in loop controlled pierce mode. low power consumption: operates from 1.8 v (nominal) supply amplitude control limits power clock monitor 9.1.2 modes of operation two modes of operation exist: 1. loop controlled pierce (lcp) oscillator 2. external square wave mode featuring also full swing pierce (fsp) without internal bias resistor the oscillator mode selection is described in the device overview section, subsection oscillator con?uration. table 9-1. revision history revision number revision date sections affected description of changes v01.05 19 jul 2006 - all xclks info was removed v02.00 04 aug 2006 - incremented revision to match the design system spec revision
pierce oscillator (s12xosclcpv2) s12xs family reference manual, rev. 1.10 266 freescale semiconductor 9.1.3 block diagram figure 9-1 shows a block diagram of the xosc. figure 9-1. xosc block diagram 9.2 external signal description this section lists and describes the signals that connect off chip 9.2.1 vddpll and vsspll ?operating and ground voltage pins theses pins provides operating voltage (v ddpll ) and ground (v sspll ) for the xosc circuitry. this allows the supply voltage to the xosc to use an independent bypass capacitor. 9.2.2 extal and xtal ?input and output pins these pins provide the interface for either a crystal or a 1.8v cmos compatible clock to control the internal clock generator circuitry. extal is the external clock input or the input to the crystal oscillator ampli?r. xtal is the output of the crystal oscillator ampli?r. the mcu internal system clock is derived extal xtal gain control v ddpll = 1.8 v rf oscclk monitor_failure clock monitor peak detector
pierce oscillator (s12xosclcpv2) s12xs family reference manual rev. 1.10 freescale semiconductor 267 from the extal input frequency. in full stop mode (pstp = 0), the extal pin is pulled down by an internal resistor of typical 200 k ? . note freescale recommends an evaluation of the application board and chosen resonator or crystal by the resonator or crystal supplier. loop controlled circuit is not suited for overtone resonators and crystals. figure 9-2. loop controlled pierce oscillator connections (lcp mode selected) note full swing pierce circuit is not suited for overtone resonators and crystals without a careful component selection. figure 9-3. full swing pierce oscillator connections (fsp mode selected) figure 9-4. external clock connections (fsp mode selected) mcu extal xtal v sspll crystal or ceramic resonator c2 c1 * r s can be zero (shorted) when use with higher frequency crystals. refer to manufacturer? data. mcu extal xtal rs* rb v sspll crystal or ceramic resonator c2 c1 mcu extal xtal not connected cmos compatible external oscillator (v ddpll level)
pierce oscillator (s12xosclcpv2) s12xs family reference manual, rev. 1.10 268 freescale semiconductor 9.3 memory map and register de?ition the crg contains the registers and associated bits for controlling and monitoring the oscillator module. 9.4 functional description the xosc module has control circuitry to maintain the crystal oscillator circuit voltage level to an optimal level which is determined by the amount of hysteresis being used and the maximum oscillation range. the oscillator block has two external pins, extal and xtal. the oscillator input pin, extal, is intended to be connected to either a crystal or an external clock source. the xtal pin is an output signal that provides crystal circuit feedback. a buffered extal signal becomes the internal clock. to improve noise immunity, the oscillator is powered by the vddpll and vsspll power supply pins. 9.4.1 gain control in lcp mode a closed loop control system will be utilized whereby the ampli?r is modulated to keep the output waveform sinusoidal and to limit the oscillation amplitude. the output peak to peak voltage will be kept above twice the maximum hysteresis level of the input buffer. electrical speci?ation details are provided in the electrical characteristics appendix. 9.4.2 clock monitor the clock monitor circuit is based on an internal rc time delay so that it can operate without any mcu clocks. if no oscclk edges are detected within this rc time delay, the clock monitor indicates failure which asserts self-clock mode or generates a system reset depending on the state of scme bit. if the clock monitor is disabled or the presence of clocks is detected no failure is indicated.the clock monitor function is enabled/disabled by the cme control bit, described in the crg block description chapter. 9.4.3 wait mode operation during wait mode, xosc is not impacted. 9.4.4 stop mode operation xosc is placed in a static state when the part is in stop mode except when pseudo-stop mode is enabled. during pseudo-stop mode, xosc is not impacted.
s12xs family reference manual, rev. 1.10 freescale semiconductor 269 chapter 10 analog-to-digital converter (adc12b16cv1) revision history 10.1 introduction the adc12b16c is a 16-channel, 12-bit, multiplexed input successive approximation analog-to-digital converter. refer to device electrical speci?ations for atd accuracy. 10.1.1 features 8-, 10-, or 12-bit resolution. conversion in stop mode using internally generated clock automatic return to low power after conversion sequence automatic compare with interrupt for higher than or less/equal than programmable value programmable sample time. left/right justi?d result data. external trigger control. sequence complete interrupt. analog input multiplexer for 16 analog input channels. special conversions for v rh , v rl , (v rl +v rh )/2. 1-to-16 conversion sequence lengths. continuous conversion mode. multiple channel scans. con?urable external trigger functionality on any ad channel or any of four additional trigger inputs. the four additional trigger inputs can be chip external or internal. refer to device speci?ation for availability and connectivity. version number revision date effective date author description of changes v01.00 13 oct. 2005 13 oct. 2005 initial version v01.01 4 mar. 2008 4 mar. 2008 correchted reference that djm bit is in atdctl3
analog-to-digital converter (adc12b16cv1) s12xs family reference manual, rev. 1.10 270 freescale semiconductor con?urable location for channel wrap around (when converting multiple channels in a sequence).
analog-to-digital converter (adc12b16cv1) s12xs family reference manual, rev. 1.10 freescale semiconductor 271 10.1.2 modes of operation 10.1.2.1 conversion modes there is software programmable selection between performing single or continuous conversion on a single channel or multiple channels . 10.1.2.2 mcu operating modes stop mode iclkstp=0 (in atdctl2 register) entering stop mode aborts any conversion sequence in progress and if a sequence was aborted restarts it after exiting stop mode. this has the same effect/consequences as starting a conversion sequence with write to atdctl5. so after exiting from stop mode with a previously aborted sequence all ?gs are cleared etc. iclkstp=1 (in atdctl2 register) a/d conversion sequence seamless continues in stop mode based on the internally generated clock iclk as atd clock. for conversions during transition from run to stop mode or vice versa the result is not written to the results register, no ccf ?g is set and no compare is done. when converting in stop mode (iclkstp=1) an atd stop recovery time t atdstprcv is required to switch back to bus clock based atdclk when leaving stop mode. do not access atd registers during this time . wait mode adc12b16c behaves same in run and wait mode. for reduced power consumption continuos conversions should be aborted before entering wait mode. freeze mode in freeze mode the adc12b16c will either continue or ?ish or stop converting according to the frz1 and frz0 bits. this is useful for debugging and emulation.
analog-to-digital converter (adc12b16cv1) s12xs family reference manual, rev. 1.10 272 freescale semiconductor 10.1.3 block diagram figure 10-1. adc12b16c block diagram v ssa an8 atd_12b16c analog mux mode and successive approximation register (sar) results atd 0 atd 1 atd 2 atd 3 atd 4 atd 5 atd 6 atd 7 and dac sample & hold v dda v rl v rh sequence complete + - comparator clock prescaler bus clock atd clock atd 8 atd 9 atd 10 atd 11 atd 12 atd 13 atd 14 atd 15 an7 an6 an5 an4 an3 an2 an1 an0 an9 an10 an11 an12 an13 an14 an15 etrig0 (see device speci? cation for availability etrig1 etrig2 etrig3 and connectivity) timing control atddien atdctl1 trigger mux internal clock interrupt compare interrupt iclk
analog-to-digital converter (adc12b16cv1) s12xs family reference manual, rev. 1.10 freescale semiconductor 273 10.2 signal description this section lists all inputs to the adc12b16c block. 10.2.1 detailed signal descriptions 10.2.1.1 an x ( x = 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0) this pin serves as the analog input channel x . it can also be con?ured as digital port or external trigger for the atd conversion. 10.2.1.2 etrig3, etrig2, etrig1, etrig0 these inputs can be con?ured to serve as an external trigger for the atd conversion. refer to device speci?ation for availability and connection of these inputs! 10.2.1.3 v rh , v rl v rh is the high reference voltage, v rl is the low reference voltage for atd conversion. 10.2.1.4 v dda , v ssa these pins are the power supplies for the analog circuitry of the adc12b16c block. 10.3 memory map and register de?ition this section provides a detailed description of all registers accessible in the adc12b16c. 10.3.1 module memory map figure 10-2 gives an overview on all adc12b16c registers. note register address = base address + address offset, where the base address is de?ed at the mcu level and the address offset is de?ed at the module level. address name bit 7 6 5 4 3 2 1 bit 0 0x0000 atdctl0 r reserved 000 wrap3 wrap2 wrap1 wrap0 w 0x0001 atdctl1 r etrigsel sres1 sres0 smp_dis etrigch3 etrigch2 etrigch1 etrigch0 w 0x0002 atdctl2 r0 affc iclkstp etrigle etrigp etrige ascie acmpie w = unimplemented or reserved figure 10-2. adc12b16c register summary (sheet 1 of 3)
analog-to-digital converter (adc12b16cv1) s12xs family reference manual, rev. 1.10 274 freescale semiconductor 0x0003 atdctl3 r djm s8c s4c s2c s1c fifo frz1 frz0 w 0x0004 atdctl4 r smp2 smp1 smp0 prs[4:0] w 0x0005 atdctl5 r0 sc scan mult cd cc cb ca w 0x0006 atdstat0 r scf 0 etorf fifor cc3 cc2 cc1 cc0 w 0x0007 unimple- mented r0 000 0 0 0 0 w 0x0008 atdcmpeh r cmpe[15:8] w 0x0009 atdcmpel r cmpe[7:0] w 0x000a atdstat2h r ccf[15:8] w 0x000b atdstat2l r ccf[7:0] w 0x000c atddienh r ien[15:8] w 0x000d atddienl r ien[7:0] w 0x000e atdcmphth r cmpht[15:8] w 0x000f atdcmphtl r cmpht[7:0] w 0x0010 atddr0 r see section 10.3.2.12.1, ?eft justi?d result data (djm=0) and section 10.3.2.12.2, ?ight justi?d result data (djm=1) w 0x0012 atddr1 r see section 10.3.2.12.1, ?eft justi?d result data (djm=0) and section 10.3.2.12.2, ?ight justi?d result data (djm=1) w 0x0014 atddr2 r see section 10.3.2.12.1, ?eft justi?d result data (djm=0) and section 10.3.2.12.2, ?ight justi?d result data (djm=1) w 0x0016 atddr3 r see section 10.3.2.12.1, ?eft justi?d result data (djm=0) and section 10.3.2.12.2, ?ight justi?d result data (djm=1) w 0x0018 atddr4 r see section 10.3.2.12.1, ?eft justi?d result data (djm=0) and section 10.3.2.12.2, ?ight justi?d result data (djm=1) w 0x001a atddr5 r see section 10.3.2.12.1, ?eft justi?d result data (djm=0) and section 10.3.2.12.2, ?ight justi?d result data (djm=1) w 0x001c atddr6 r see section 10.3.2.12.1, ?eft justi?d result data (djm=0) and section 10.3.2.12.2, ?ight justi?d result data (djm=1) w 0x001e atddr7 r see section 10.3.2.12.1, ?eft justi?d result data (djm=0) and section 10.3.2.12.2, ?ight justi?d result data (djm=1) w 0x0020 atddr8 r see section 10.3.2.12.1, ?eft justi?d result data (djm=0) and section 10.3.2.12.2, ?ight justi?d result data (djm=1) w 0x0022 atddr9 r see section 10.3.2.12.1, ?eft justi?d result data (djm=0) and section 10.3.2.12.2, ?ight justi?d result data (djm=1) w address name bit 7 6 5 4 3 2 1 bit 0 = unimplemented or reserved figure 10-2. adc12b16c register summary (sheet 2 of 3)
analog-to-digital converter (adc12b16cv1) s12xs family reference manual, rev. 1.10 freescale semiconductor 275 0x0024 atddr10 r see section 10.3.2.12.1, ?eft justi?d result data (djm=0) and section 10.3.2.12.2, ?ight justi?d result data (djm=1) w 0x0026 atddr11 r see section 10.3.2.12.1, ?eft justi?d result data (djm=0) and section 10.3.2.12.2, ?ight justi?d result data (djm=1) w 0x0028 atddr12 r see section 10.3.2.12.1, ?eft justi?d result data (djm=0) and section 10.3.2.12.2, ?ight justi?d result data (djm=1) w 0x002a atddr13 r see section 10.3.2.12.1, ?eft justi?d result data (djm=0) and section 10.3.2.12.2, ?ight justi?d result data (djm=1) w 0x002c atddr14 r see section 10.3.2.12.1, ?eft justi?d result data (djm=0) and section 10.3.2.12.2, ?ight justi?d result data (djm=1) w 0x002e atddr15 r see section 10.3.2.12.1, ?eft justi?d result data (djm=0) and section 10.3.2.12.2, ?ight justi?d result data (djm=1) w address name bit 7 6 5 4 3 2 1 bit 0 = unimplemented or reserved figure 10-2. adc12b16c register summary (sheet 3 of 3)
analog-to-digital converter (adc12b16cv1) s12xs family reference manual, rev. 1.10 276 freescale semiconductor 10.3.2 register descriptions this section describes in address order all the adc12b16c registers and their individual bits. 10.3.2.1 atd control register 0 (atdctl0) writes to this register will abort current conversion sequence. read: anytime write: anytime, in special modes always write 0 to reserved bit 7. module base + 0x0000 76543210 r reserved 000 wrap3 wrap2 wrap1 wrap0 w reset 0 0 0 01111 = unimplemented or reserved figure 10-3. atd control register 0 (atdctl0) table 10-1. atdctl0 field descriptions field description 3-0 wrap[3-0] wrap around channel select bits ?these bits determine the channel for wrap around when doing multi- channel conversions. the coding is summarized in table 10-2 . table 10-2. multi-channel wrap around coding wrap3 wrap2 wrap1 wrap0 multiple channel conversions (mult = 1) wraparound to an0 after converting 0000 reserved 1 0001 an1 0010 an2 0011 an3 0100 an4 0101 an5 0110 an6 0111 an7 1000 an8 1001 an9 1010 an10 1011 an11 1100 an12 1101 an13 1110 an14 1111 an15
analog-to-digital converter (adc12b16cv1) s12xs family reference manual, rev. 1.10 freescale semiconductor 277 10.3.2.2 atd control register 1 (atdctl1) writes to this register will abort current conversion sequence. read: anytime write: anytime 1 if only an0 should be converted use mult=0. module base + 0x0001 76543210 r etrigsel sres1 sres0 smp_dis etrigch3 etrigch2 etrigch1 etrigch0 w reset 0 0 1 01111 figure 10-4. atd control register 1 (atdctl1) table 10-3. atdctl1 field descriptions field description 7 etrigsel external trigger source select ?this bit selects the external trigger source to be either one of the ad channels or one of the etrig3-0 inputs. see device speci?ation for availability and connectivity of etrig3- 0 inputs. if a particular etrig3-0 input option is not available, writing a 1 to etrisel only sets the bit but has not effect, this means that one of the ad channels (selected by etrigch3-0) is con?ured as the source for external trigger. the coding is summarized in table 10-5 . 6? sres[1:0] a/d resolution select ?these bits select the resolution of a/d conversion results. see table 10-4 for coding. 4 smp_dis discharge before sampling bit 0 no discharge before sampling. 1 the internal sample capacitor is discharged before sampling the channel. this adds 2 atd clock cycles to the sampling time. this can help to detect an open circuit instead of measuring the previous sampled channel. 3? etrigch[3:0] external trigger channel select these bits select one of the ad channels or one of the etrig3-0 inputs as source for the external trigger. the coding is summarized in table 10-5 . table 10-4. a/d resolution coding sres1 sres0 a/d resolution 0 0 8-bit data 0 1 10-bit data 1 0 12-bit data 1 1 reserved
analog-to-digital converter (adc12b16cv1) s12xs family reference manual, rev. 1.10 278 freescale semiconductor 10.3.2.3 atd control register 2 (atdctl2) writes to this register will abort current conversion sequence. read: anytime write: anytime table 10-5. external trigger channel select coding etrigsel etrigch3 etrigch2 etrigch1 etrigch0 external trigger source is 0 0 0 0 0 an0 0 0 0 0 1 an1 0 0 0 1 0 an2 0 0 0 1 1 an3 0 0 1 0 0 an4 0 0 1 0 1 an5 0 0 1 1 0 an6 0 0 1 1 1 an7 0 1 0 0 0 an8 0 1 0 0 1 an9 0 1 0 1 0 an10 0 1 0 1 1 an11 0 1 1 0 0 an12 0 1 1 0 1 an13 0 1 1 1 0 an14 0 1 1 1 1 an15 1 0 0 0 0 etrig0 1 1 only if etrig3-0 input option is available (see device speci?ation), else etrisel is ignored, that means external trigger source is still on one of the ad channels selected by etrigch3-0 1 0 0 0 1 etrig1 1 1 0 0 1 0 etrig2 1 1 0 0 1 1 etrig3 1 1 0 1 x x reserved 1 1 x x x reserved module base + 0x0002 76543210 r0 affc iclkstp etrigle etrigp etrige ascie acmpie w reset 0 0 0 00000 = unimplemented or reserved figure 10-5. atd control register 2 (atdctl2)
analog-to-digital converter (adc12b16cv1) s12xs family reference manual, rev. 1.10 freescale semiconductor 279 table 10-6. atdctl2 field descriptions field description 6 affc atd fast flag clear all 0 atd ?g clearing done by write 1 to respective ccf[ n ] ?g. 1 changes all atd conversion complete ?gs to a fast clear sequence. for compare disabled (cmpe[ n ]=0) a read access to the result register will cause the associated ccf[ n ] ?g to clear automatically. for compare enabled (cmpe[ n ]=1) a write access to the result register will cause the associated ccf[ n ] ?g to clear automatically. 5 iclkstp internal clock in stop mode bit this bit enables a/d conversions in stop mode. when going into stop mode and iclkstp=1 the atd conversion clock is automatically switched to the internally generated clock iclk. current conversion sequence will seamless continue. conversion speed will change from prescaled bus frequency to the iclk frequency (see atd electrical characteristics in device description). the prescaler bits prs4-0 in atdctl4 have no effect on the iclk frequency. for conversions during stop mode the automatic compare interrupt or the sequence complete interrupt can be used to inform software handler about changing a/d values. external trigger will not work while converting in stop mode. for conversions during transition from run to stop mode or vice versa the result is not written to the results register, no ccf ?g is set and no compare is done. when converting in stop mode (iclkstp=1) an atd stop recovery time t atdstprcv is required to switch back to bus clock based atdclk when leaving stop mode. do not access atd registers during this time. 0 if a/d conversion sequence is ongoing when going into stop mode, the actual conversion sequence will be aborted and automatically restarted when exiting stop mode. 1 a/d continues to convert in stop mode using internally generated clock (iclk) 4 etrigle external trigger level/edge control ?this bit controls the sensitivity of the external trigger signal. see table 10-7 for details. 3 etrigp external trigger polarity this bit controls the polarity of the external trigger signal. see table 10-7 for details. 2 etrige external trigger mode enable this bit enables the external trigger on one of the ad channels or one of the etrig3-0 inputs as described in table 10-5 . if external trigger source is one of the ad channels, the digital input buffer of this channel is enabled. the external trigger allows to synchronize the start of conversion with external events. external trigger will not work while converting in stop mode. 0 disable external trigger 1 enable external trigger 1 ascie atd sequence complete interrupt enable 0 atd sequence complete interrupt requests are disabled. 1 atd sequence complete interrupt will be requested whenever scf=1 is set. 0 acmpie atd compare interrupt enable if automatic compare is enabled for conversion n (cmpe[ n ]=1 in atdcmpe register) this bit enables the compare interrupt. if the ccf[ n ] ?g is set (showing a successful compare for conversion n ), the compare interrupt is triggered. 0 atd compare interrupt requests are disabled. 1 for the conversions in a sequence for which automatic compare is enabled (cmpe[ n ]=1), atd compare interrupt will be requested whenever any of the respective ccf ?gs is set. table 10-7. external trigger con?urations etrigle etrigp external trigger sensitivity 0 0 falling edge 0 1 rising edge 1 0 low level 1 1 high level
analog-to-digital converter (adc12b16cv1) s12xs family reference manual, rev. 1.10 280 freescale semiconductor 10.3.2.4 atd control register 3 (atdctl3) writes to this register will abort current conversion sequence. read: anytime write: anytime module base + 0x0003 76543210 r djm s8c s4c s2c s1c fifo frz1 frz0 w reset 0 0 1 00000 = unimplemented or reserved figure 10-6. atd control register 3 (atdctl3) table 10-8. atdctl3 field descriptions field description 7 djm result register data justi?ation ?result data format is always unsigned. this bit controls justi?ation of conversion data in the result registers. 0 left justi?d data in the result registers. 1 right justi?d data in the result registers. table 10-9 gives examples atd results for an input signal range between 0 and 5.12 volts. 6? s8c, s4c, s2c, s1c conversion sequence length ?these bits control the number of conversions per sequence. table 10-10 shows all combinations. at reset, s4c is set to 1 (sequence length is 4). this is to maintain software continuity to hc12 family. 2 fifo result register fifo mode if this bit is zero (non-fifo mode), the a/d conversion results map into the result registers based on the conversion sequence; the result of the ?st conversion appears in the ?st result register (atddr0), the second result in the second result register (atddr1), and so on. if this bit is one (fifo mode) the conversion counter is not reset at the beginning or ending of a conversion sequence; sequential conversion results are placed in consecutive result registers. in a continuously scanning conversion sequence, the result register counter will wrap around when it reaches the end of the result register ?e. the conversion counter value (cc3-0 in atdstat0) can be used to determine where in the result register ?e, the current conversion result will be placed. aborting a conversion or starting a new conversion clears the conversion counter even if fifo=1. so the ?st result of a new conversion sequence, started by writing to atdctl5, will always be place in the ?st result register (atdddr0). intended usage of fifo mode is continuos conversion (scan=1) or triggered conversion (etrig=1). which result registers hold valid data can be tracked using the conversion complete ?gs. fast ?g clear mode may or may not be useful in a particular application to track valid data. if this bit is one, automatic compare of result registers is always disabled, that is adc12b16c will behave as if acmpie and all cpme[ n ] were zero. 0 conversion results are placed in the corresponding result register up to the selected sequence length. 1 conversion results are placed in consecutive result registers (wrap around at end). 1? frz[1:0] background debug freeze enable ?when debugging an application, it is useful in many cases to have the atd pause when a breakpoint (freeze mode) is encountered. these 2 bits determine how the atd will respond to a breakpoint as shown in table 10-11 . leakage onto the storage node and comparator reference capacitors may compromise the accuracy of an immediately frozen conversion depending on the length of the freeze period.
analog-to-digital converter (adc12b16cv1) s12xs family reference manual, rev. 1.10 freescale semiconductor 281 table 10-9. examples of ideal decimal atd results input signal v rl = 0 volts v rh = 5.12 volts 8-bit codes (resolution=20mv) 10-bit codes (resolution=5mv) 12-bit codes (transfer curve has 1.25mv offset) (resolution=1.25mv) 5.120 volts ... 0.022 0.020 0.018 0.016 0.014 0.012 0.010 0.008 0.006 0.004 0.003 0.002 0.000 255 ... 1 1 1 1 1 1 1 0 0 0 0 0 0 1023 ... 4 4 4 3 3 2 2 2 1 1 0 0 0 4095 ... 17 16 14 12 11 9 8 6 4 3 2 1 0 table 10-10. conversion sequence length coding s8c s4c s2c s1c number of conversions per sequence 00 0 0 16 00 0 1 1 00 1 0 2 00 1 1 3 01 0 0 4 01 0 1 5 01 1 0 6 01 1 1 7 10 0 0 8 10 0 1 9 10 1 0 10 10 1 1 11 11 0 0 12 11 0 1 13 11 1 0 14 11 1 1 15
analog-to-digital converter (adc12b16cv1) s12xs family reference manual, rev. 1.10 282 freescale semiconductor 10.3.2.5 atd control register 4 (atdctl4) writes to this register will abort current conversion sequence. read: anytime write: anytime table 10-11. atd behavior in freeze mode (breakpoint) frz1 frz0 behavior in freeze mode 0 0 continue conversion 0 1 reserved 1 0 finish current conversion, then freeze 1 1 freeze immediately module base + 0x0004 76543210 r smp2 smp1 smp0 prs[4:0] w reset 0 0 0 00101 figure 10-7. atd control register 4 (atdctl4) table 10-12. atdctl4 field descriptions field description 7? smp[2:0] sample time select ?these three bits select the length of the sample time in units of atd conversion clock cycles. note that the atd conversion clock period is itself a function of the prescaler value (bits prs4-0). table 10-13 lists the available sample time lengths. 4? prs[4:0] atd clock prescaler these 5 bits are the binary prescaler value prs. the atd conversion clock frequency is calculated as follows: refer to device speci?ation for allowed frequency range of f atdclk . table 10-13. sample time select smp2 smp1 smp0 sample time in number of atd clock cycles 000 4 001 6 010 8 011 10 100 12 101 16 110 20 f atdclk f bus 2 prs 1 + () ------------------------------------- =
analog-to-digital converter (adc12b16cv1) s12xs family reference manual, rev. 1.10 freescale semiconductor 283 10.3.2.6 atd control register 5 (atdctl5) writes to this register will abort current conversion sequence and start a new conversion sequence. if external trigger is enabled (etrige=1) an initial write to atdctl5 is required to allow starting of a conversion sequence which will then occur on each trigger event. start of conversion means the beginning of the sampling phase. read: anytime write: anytime 111 24 module base + 0x0005 76543210 r0 sc scan mult cd cc cb ca w reset 0 0 0 00000 figure 10-8. atd control register 5 (atdctl5) table 10-14. atdctl5 field descriptions field description 6 sc special channel conversion bit if this bit is set, then special channel conversion can be selected using cd, cc, cb and ca of atdctl5. table 10-15 lists the coding. 0 special channel conversions disabled 1 special channel conversions enabled 5 scan continuous conversion sequence mode ?this bit selects whether conversion sequences are performed continuously or only once. if external trigger is enabled (etrige=1) setting this bit has no effect, that means external trigger always starts a single conversion sequence. 0 single conversion sequence 1 continuous conversion sequences (scan mode) table 10-13. sample time select smp2 smp1 smp0 sample time in number of atd clock cycles
analog-to-digital converter (adc12b16cv1) s12xs family reference manual, rev. 1.10 284 freescale semiconductor 4 mult multi-channel sample mode when mult is 0, the atd sequence controller samples only from the speci?d analog input channel for an entire conversion sequence. the analog channel is selected by channel selection code (control bits cd/cc/cb/ca located in atdctl5). when mult is 1, the atd sequence controller samples across channels. the number of channels sampled is determined by the sequence length value (s8c, s4c, s2c, s1c). the ?st analog channel examined is determined by channel selection code (cd, cc, cb, ca control bits); subsequent channels sampled in the sequence are determined by incrementing the channel selection code or wrapping around to an0 (channel 0). 0 sample only one channel 1 sample across several channels 3? cd, cc, cb, ca analog input channel select code ?these bits select the analog input channel(s) whose signals are sampled and converted to digital codes. table 10-15 lists the coding used to select the various analog input channels. in the case of single channel conversions (mult=0), this selection code speci?s the channel to be examined. in the case of multiple channel conversions (mult=1), this selection code speci?s the ?st channel to be examined in the conversion sequence. subsequent channels are determined by incrementing the channel selection code or wrapping around to an0 (after converting the channel de?ed by the wrap around channel select bits wrap3-0 in atdctl0). in case of starting with a channel number higher than the one de?ed by wrap3-0 the ?st wrap around will be an15 to an0. table 10-15. analog input channel select coding sc cd cc cb ca analog input channel 00000 an0 0001 an1 0010 an2 0011 an3 0100 an4 0101 an5 0110 an6 0111 an7 1000 an8 1001 an9 1 0 1 0 an10 1 0 1 1 an11 1 1 0 0 an12 1 1 0 1 an13 1 1 1 0 an14 1 1 1 1 an15 table 10-14. atdctl5 field descriptions (continued) field description
analog-to-digital converter (adc12b16cv1) s12xs family reference manual, rev. 1.10 freescale semiconductor 285 1 0 0 0 0 reserved 0 0 0 1 reserved 0 0 1 x reserved 0100 v rh 0101 v rl 0110 (v rh +v rl ) / 2 0 1 1 1 reserved 1 x x x reserved table 10-15. analog input channel select coding sc cd cc cb ca analog input channel
analog-to-digital converter (adc12b16cv1) s12xs family reference manual, rev. 1.10 286 freescale semiconductor 10.3.2.7 atd status register 0 (atdstat0) this register contains the sequence complete flag, overrun ?gs for external trigger and fifo mode, and the conversion counter. read: anytime write: anytime (no effect on (cc3, cc2, cc1, cc0)) module base + 0x0006 76543210 r scf 0 etorf fifor cc3 cc2 cc1 cc0 w reset 0 0 0 00000 = unimplemented or reserved figure 10-9. atd status register 0 (atdstat0) table 10-16. atdstat0 field descriptions field description 7 scf sequence complete flag ?this ?g is set upon completion of a conversion sequence. if conversion sequences are continuously performed (scan=1), the ?g is set after each one is completed. this ?g is cleared when one of the following occurs: a) write ??to scf b) write to atdctl5 (a new conversion sequence is started) c) if affc=1 and read of a result register 0 conversion sequence not completed 1 conversion sequence has completed 5 etorf external trigger overrun flag ?while in edge trigger mode (etrigle=0), if additional active edges are detected while a conversion sequence is in process the overrun ?g is set. this ?g is cleared when one of the following occurs: a) write ??to etorf b) write to atdctl0,1,2,3,4, atdcmpe or atdcmpht (a conversion sequence is aborted) c) write to atdctl5 (a new conversion sequence is started) 0 no external trigger over run error has occurred 1 external trigger over run error has occurred 4 fifor result register over run flag ?this bit indicates that a result register has been written to before its associated conversion complete ?g (ccf) has been cleared. this ?g is most useful when using the fifo mode because the ?g potentially indicates that result registers are out of sync with the input channels. however, it is also practical for non-fifo modes, and indicates that a result register has been over written before it has been read (i.e. the old data has been lost). this ?g is cleared when one of the following occurs: a) write ??to fifor b) write to atdctl0,1,2,3,4, atdcmpe or atdcmpht (a conversion sequence is aborted) c) write to atdctl5 (a new conversion sequence is started) 0 no over run has occurred 1 overrun condition exists (result register has been written while associated ccfx ?g was still set)
analog-to-digital converter (adc12b16cv1) s12xs family reference manual, rev. 1.10 freescale semiconductor 287 10.3.2.8 atd compare enable register (atdcmpe) writes to this register will abort current conversion sequence. read: anytime write: anytime 3? cc[3:0] conversion counter these 4 read-only bits are the binary value of the conversion counter. the conversion counter points to the result register that will receive the result of the current conversion. e.g. cc3=0, cc2=1, cc1=1, cc0=0 indicates that the result of the current conversion will be in atd result register 6. if in non-fifo mode (fifo=0) the conversion counter is initialized to zero at the begin and end of the conversion sequence. if in fifo mode (fifo=1) the register counter is not initialized. the conversion counters wraps around when its maximum value is reached. aborting a conversion or starting a new conversion clears the conversion counter even if fifo=1. module base + 0x0008 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r cmpe[15:0] w reset 0 0 0 0 0 0 0 0 0 0000000 figure 10-10. atd compare enable register (atdcmpe) table 10-17. atdcmpe field descriptions field description 15? cmpe[15:0] compare enable for conversion number n ( n = 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0) of a sequence ?these bits enable automatic compare of conversion results individually for conversions of a sequence. the sense of each comparison is determined by the cmpht[ n ] bit in the atdcmpht register. for each conversion number with cmpe[ n ]=1 do the following: 1) write compare value to atddr n result register 2) write compare operator with cmpht[ n ] in atdcpmht register ccf[ n ] in atdstat2 register will ?g individual success of any comparison. 0 no automatic compare 1 automatic compare of results for conversion n of a sequence is enabled. table 10-16. atdstat0 field descriptions (continued) field description
analog-to-digital converter (adc12b16cv1) s12xs family reference manual, rev. 1.10 288 freescale semiconductor 10.3.2.9 atd status register 2 (atdstat2) this read-only register contains the conversion complete flags ccf[15:0]. read: anytime write: anytime, no effect module base + 0x000a 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r ccf[15:0] w reset 0 0 0 0 0 0 0 0 0 0000000 = unimplemented or reserved figure 10-11. atd status register 2 (atdstat2) table 10-18. atdstat2 field descriptions field description 15? ccf[15:0] conversion complete flag n ( n = 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0) ?a conversion complete ?g is set at the end of each conversion in a sequence. the ?gs are associated with the conversion position in a sequence (and also the result register number). therefore in non-?o mode, ccf[8] is set when the ninth conversion in a sequence is complete and the result is available in result register atddr8; ccf[9] is set when the tenth conversion in a sequence is complete and the result is available in atddr9, and so forth. if automatic compare of conversion results is enabled (cmpe[ n ]=1 in atdcmpe), the conversion complete ?g is only set if comparison with atddr n is true and if acmpie=1 a compare interrupt will be requested. in this case, as the atddr n result register is used to hold the compare value, the result will not be stored there at the end of the conversion but is lost. a ?g ccf[ n ] is cleared when one of the following occurs: a) write to atdctl5 (a new conversion sequence is started) b) if affc=0, write ??to ccf[ n ] c) if affc=1 and cmpe[ n ]=0, read of result register atddr n d) if affc=1 and cmpe[ n ]=1, write to result register atddr n in case of a concurrent set and clear on ccf[ n ]: the clearing by method a) will overwrite the set. the clearing by methods b) or c) or d) will be overwritten by the set. 0 conversion number n not completed or successfully compared 1 if (cmpe[ n ]=0): conversion number n has completed. result is ready in atddr n . if (cmpe[ n ]=1): compare for conversion result number n with compare value in atddr n , using compare operator cmpgt[ n ] is true. (no result available in atddr n )
analog-to-digital converter (adc12b16cv1) s12xs family reference manual, rev. 1.10 freescale semiconductor 289 10.3.2.10 atd input enable register (atddien) read: anytime write: anytime 10.3.2.11 atd compare higher than register (atdcmpht) writes to this register will abort current conversion sequence. read: anytime write: anytime module base + 0x000c 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r ien[15:0] w reset 0 0 0 0 0 0 0 0 0 0000000 figure 10-12. atd input enable register (atddien) table 10-19. atddien field descriptions field description 15? ien[15:0] atd digital input enable on channel x ( x = 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0) this bit controls the digital input buffer from the analog input pin (an x ) to the digital data register. 0 disable digital input buffer to an x pin 1 enable digital input buffer on an x pin. note: setting this bit will enable the corresponding digital input buffer continuously. if this bit is set while simultaneously using it as an analog port, there is potentially increased power consumption because the digital input buffer maybe in the linear region. module base + 0x000e 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r cmpht[15:0] w reset 0 0 0 0 0 0 0 0 0 0000000 figure 10-13. atd compare higher than register (atdcmpht) table 10-20. atdcmpht field descriptions field description 15? cmpht[15:0] compare operation higher than enable for conversion number n ( n = 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0) of a sequence ?this bit selects the operator for comparison of conversion results. 0 if result of conversion n is lower or same than compare value in atddr n , this is ?gged in atdstat2 1 if result of conversion n is higher than compare value in atddr n , this is ?gged in atdstat2
analog-to-digital converter (adc12b16cv1) s12xs family reference manual, rev. 1.10 290 freescale semiconductor 10.3.2.12 atd conversion result registers (atddr n ) the a/d conversion results are stored in 16 result registers. results are always in unsigned data representation. left and right justi?ation is selected using the djm control bit in atdctl3. if automatic compare of conversions results is enabled (cmpe[ n ]=1 in atdcmpe), these registers must be written with the compare values in left or right justi?d format depending on the actual value of the djm bit. in this case, as the atddr n register is used to hold the compare value, the result will not be stored there at the end of the conversion but is lost. read: anytime write: anytime note for conversions not using automatic compare, results are stored in the result registers after each conversion. in this case avoid writing to atddrn except for initial values, because an a/d result might be overwritten. 10.3.2.12.1 left justi?d result data (djm=0) 10.3.2.12.2 right justi?d result data (djm=1) table 10-15 shows how depending on the a/d resolution the conversion result is transferred to the atd result registers. compare is always done using all 12 bits of both the conversion result and the compare value in atddrn. module base + 0x0010 = atddr0, 0x0012 = atddr1, 0x0014 = atddr2, 0x0016 = atddr3 0x0018 = atddr4, 0x001a = atddr5, 0x001c = atddr6, 0x001e = atddr7 0x0020 = atddr8, 0x0022 = atddr9, 0x0024 = atddr10, 0x0026 = atddr11 0x0028 = atddr12, 0x002a = atddr13, 0x002c = atddr14, 0x002e = atddr15 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0 000 w reset 0 0 0 0 0 0 0 0 0 0000000 figure 10-14. left justi?d atd conversion result register (atddr n ) module base + 0x0010 = atddr0, 0x0012 = atddr1, 0x0014 = atddr2, 0x0016 = atddr3 0x0018 = atddr4, 0x001a = atddr5, 0x001c = atddr6, 0x001e = atddr7 0x0020 = atddr8, 0x0022 = atddr9, 0x0024 = atddr10, 0x0026 = atddr11 0x0028 = atddr12, 0x002a = atddr13, 0x002c = atddr14, 0x002e = atddr15 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r 0 000 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bi1 1 bit 0 w reset 0 0 0 0 0 0 0 0 0 0000000 figure 10-15. right justi?d atd conversion result register (atddr n )
analog-to-digital converter (adc12b16cv1) s12xs family reference manual, rev. 1.10 freescale semiconductor 291 table 10-21. conversion result mapping to atddrn a/d resolution djm conversion result mapping to atddr n 8-bit data 0 bit[11:4] = result, bit[3:0]=0000 8-bit data 1 bit[7:0] = result, bit[11:8]=0000 10-bit data 0 bit[11:2] = result, bit[1:0]=00 10-bit data 1 bit[9:0] = result, bit[11:10]=00 12-bit data x bit[11:0] = result
analog-to-digital converter (adc12b16cv1) s12xs family reference manual, rev. 1.10 292 freescale semiconductor 10.4 functional description the adc12b16c is structured into an analog sub-block and a digital sub-block. 10.4.1 analog sub-block the analog sub-block contains all analog electronics required to perform a single conversion. separate power supplies v dda and v ssa allow to isolate noise of other mcu circuitry from the analog sub-block. 10.4.1.1 sample and hold machine the sample and hold (s/h) machine accepts analog signals from the external world and stores them as capacitor charge on a storage node. during the sample process the analog input connects directly to the storage node. the input analog signals are unipolar and must fall within the potential range of v ssa to v dda . during the hold process the analog input is disconnected from the storage node. 10.4.1.2 analog input multiplexer the analog input multiplexer connects one of the 16 external analog input channels to the sample and hold machine. 10.4.1.3 analog-to-digital (a/d) machine the a/d machine performs analog to digital conversions. the resolution is program selectable at either 8 or 10 or 12 bits. the a/d machine uses a successive approximation architecture. it functions by comparing the stored analog sample potential with a series of digitally generated analog potentials. by following a binary search algorithm, the a/d machine locates the approximating potential that is nearest to the sampled potential. when not converting the a/d machine is automatically powered down. only analog input signals within the potential range of v rl to v rh (a/d reference potentials) will result in a non-railed digital output code. 10.4.2 digital sub-block this subsection explains some of the digital features in more detail. see section 10.3.2, ?egister descriptions for all details. 10.4.2.1 external trigger input the external trigger feature allows the user to synchronize atd conversions to the external environment events rather than relying on software to signal the atd module when atd conversions are to take place. the external trigger signal (out of reset atd channel 15, con?urable in atdctl1) is programmable to
analog-to-digital converter (adc12b16cv1) s12xs family reference manual, rev. 1.10 freescale semiconductor 293 be edge or level sensitive with polarity control. table 10-22 gives a brief description of the different combinations of control bits and their effect on the external trigger function. during a conversion, if additional active edges are detected the overrun error ?g etorf is set. in either level or edge triggered modes, the ?st conversion begins when the trigger is received. once etrige is enabled, conversions cannot be started by a write to atdctl5, but rather must be triggered externally. if the level mode is active and the external trigger both de-asserts and re-asserts itself during a conversion sequence, this does not constitute an overrun. therefore, the ?g is not set. if the trigger is left asserted in level mode while a sequence is completing, another sequence will be triggered immediately. 10.4.2.2 general-purpose digital port operation the input channel pins can be multiplexed between analog and digital data. as analog inputs, they are multiplexed and sampled as analog channels to the a/d converter. the analog/digital multiplex operation is performed in the input pads. the input pad is always connected to the analog input channels of the adc12b16c. the input pad signal is buffered to the digital port registers. this buffer can be turned on or off with the atddien register. this is important so that the buffer does not draw excess current when analog potentials are presented at its input. 10.5 resets at reset the adc12b16c is in a power down state. the reset state of each individual bit is listed within the register description section (see section 10.3.2, ?egister descriptions ) which details the registers and their bit-?ld. table 10-22. external trigger control bits etrigle etrigp etrige scan description x x 0 0 ignores external trigger. performs one conversion sequence and stops. x x 0 1 ignores external trigger. performs continuous conversion sequences. 0 0 1 x falling edge triggered. performs one conversion sequence per trigger. 0 1 1 x rising edge triggered. performs one conversion sequence per trigger. 1 0 1 x trigger active low. performs continuous conversions while trigger is active. 1 1 1 x trigger active high. performs continuous conversions while trigger is active.
analog-to-digital converter (adc12b16cv1) s12xs family reference manual, rev. 1.10 294 freescale semiconductor 10.6 interrupts the interrupts requested by the adc12b16c are listed in table 10-23 . refer to mcu speci?ation for related vector address and priority. see section 10.3.2, ?egister descriptions for further details. table 10-23. atd interrupt vectors interrupt source ccr mask local enable sequence complete interrupt i bit ascie in atdctl2 compare interrupt i bit acmpie in atdctl2
s12xs family reference manual, rev. 1.10 freescale semiconductor 295 chapter 11 freescales scalable controller area network (s12mscanv3) 11.1 introduction freescales scalable controller area network (s12mscanv3) de?ition is based on the mscan12 de?ition, which is the speci? implementation of the mscan concept targeted for the m68hc12 microcontroller family. the module is a communication controller implementing the can 2.0a/b protocol as de?ed in the bosch speci?ation dated september 1991. for users to fully understand the mscan speci?ation, it is recommended that the bosch speci?ation be read ?st to familiarize the reader with the terms and concepts contained within this document. though not exclusively intended for automotive applications, can protocol is designed to meet the speci? requirements of a vehicle serial data bus: real-time processing, reliable operation in the emi environment of a vehicle, cost-effectiveness, and required bandwidth. mscan uses an advanced buffer arrangement resulting in predictable real-time behavior and simpli?d application software. table 11-1. revision history revision number revision date sections affected description of changes v03.09 04 may 2007 11.3.2.11/11- 313 - corrected mnemonics of code example in cantbsel register description v03.10 19 aug 2008 11.4.7.4/11-347 11.4.4.5/11-341 11.2/11-298 - corrected wake-up description - relocated initialization section - added note to external pin descriptions for use with integrated physical layer - minor corrections v03.11 31 mar 2009 - orthographic corrections
freescales scalable controller area network (s12mscanv3) s12xs family reference manual, rev. 1.10 296 freescale semiconductor 11.1.1 glossary 11.1.2 block diagram figure 11-1. mscan block diagram table 11-2. terminology ack acknowledge of can message can controller area network crc cyclic redundancy code eof end of frame fifo first-in-first-out memory ifs inter-frame sequence sof start of frame cpu bus cpu related read/write data bus can bus can protocol related serial bus oscillator clock direct clock from external oscillator bus clock cpu bus related clock can clock can protocol related clock rxcan txcan receive/ transmit engine message filtering and buffering control and status wake-up interrupt req. errors interrupt req. receive interrupt req. transmit interrupt req. canclk bus clock con?uration oscillator clock mux presc. tq clk mscan low pass filter wake-up registers
freescales scalable controller area network (s12mscanv3) s12xs family reference manual rev. 1.10 freescale semiconductor 297 11.1.3 features the basic features of the mscan are as follows: implementation of the can protocol ?version 2.0a/b standard and extended data frames zero to eight bytes data length programmable bit rate up to 1 mbps 1 support for remote frames five receive buffers with fifo storage scheme three transmit buffers with internal prioritization using a ?ocal priority?concept flexible maskable identi?r ?ter supports two full-size (32-bit) extended identi?r ?ters, or four 16-bit ?ters, or eight 8-bit ?ters programmable wake-up functionality with integrated low-pass ?ter programmable loopback mode supports self-test operation programmable listen-only mode for monitoring of can bus programmable bus-off recovery functionality separate signalling and interrupt capabilities for all can receiver and transmitter error states (warning, error passive, bus-off) programmable mscan clock source either bus clock or oscillator clock internal timer for time-stamping of received and transmitted messages three low-power modes: sleep, power down, and mscan enable global initialization of con?uration registers 11.1.4 modes of operation for a description of the speci? mscan modes and the module operation related to the system operating modes refer to section 11.4.4, ?odes of operation ? 1. depending on the actual bit timing and the clock jitter of the pll.
freescales scalable controller area network (s12mscanv3) s12xs family reference manual, rev. 1.10 298 freescale semiconductor 11.2 external signal description the mscan uses two external pins. note on mcus with an integrated can physical interface (transceiver) the mscan interface is connected internally to the transceiver interface. in these cases the external availability of signals txcan and rxcan is optional. 11.2.1 rxcan ?can receiver input pin rxcan is the mscan receiver input pin. 11.2.2 txcan ?can transmitter output pin txcan is the mscan transmitter output pin. the txcan output pin represents the logic level on the can bus: 0 = dominant state 1 = recessive state 11.2.3 can system a typical can system with mscan is shown in figure 11-2 . each can station is connected physically to the can bus lines through a transceiver device. the transceiver is capable of driving the large current needed for the can bus and has current protection against defective can or defective stations. figure 11-2. can system can bus can controller (mscan) transceiver can node 1 can node 2 can node n canl canh mcu txcan rxcan
freescales scalable controller area network (s12mscanv3) s12xs family reference manual rev. 1.10 freescale semiconductor 299 11.3 memory map and register de?ition this section provides a detailed description of all registers accessible in the mscan. 11.3.1 module memory map figure 11-3 gives an overview on all registers and their individual bits in the mscan memory map. the register address results from the addition of base address and address offset . the base address is determined at the mcu level and can be found in the mcu memory map description. the address offset is de?ed at the module level. the mscan occupies 64 bytes in the memory space. the base address of the mscan module is determined at the mcu level when the mcu is de?ed. the register decode map is ?ed and begins at the ?st address of the module address offset. the detailed register descriptions follow in the order they appear in the register map.
freescales scalable controller area network (s12mscanv3) s12xs family reference manual, rev. 1.10 300 freescale semiconductor register name bit 7 6 5 4 3 2 1 bit 0 0x0000 canctl0 r rxfrm rxact cswai synch time wupe slprq initrq w 0x0001 canctl1 r cane clksrc loopb listen borm wupm slpak initak w 0x0002 canbtr0 r sjw1 sjw0 brp5 brp4 brp3 brp2 brp1 brp0 w 0x0003 canbtr1 r samp tseg22 tseg21 tseg20 tseg13 tseg12 tseg11 tseg10 w 0x0004 canrflg r wupif cscif rstat1 rstat0 tstat1 tstat0 ovrif rxf w 0x0005 canrier r wupie cscie rstate1 rstate0 tstate1 tstate0 ovrie rxfie w 0x0006 cantflg r0 0 0 00 txe2 txe1 txe0 w 0x0007 cantier r00000 txeie2 txeie1 txeie0 w 0x0008 cantarq r00000 abtrq2 abtrq1 abtrq0 w 0x0009 cantaak r00000 abtak2 abtak1 abtak0 w 0x000a cantbsel r00000 tx2 tx1 tx0 w 0x000b canidac r0 0 idam1 idam0 0 idhit2 idhit1 idhit0 w 0x000c reserved r00000000 w 0x000d canmisc r0000000 bohold w 0x000e canrxerr r rxerr7 rxerr6 rxerr5 rxerr4 rxerr3 rxerr2 rxerr1 rxerr0 w = unimplemented or reserved figure 11-3. mscan register summary
freescales scalable controller area network (s12mscanv3) s12xs family reference manual rev. 1.10 freescale semiconductor 301 11.3.2 register descriptions this section describes in detail all the registers and register bits in the mscan module. each description includes a standard register diagram with an associated ?ure number. details of register bit and ?ld function follow the register diagrams, in bit order. all bits of all registers in this module are completely synchronous to internal clocks during a register read. 11.3.2.1 mscan control register 0 (canctl0) the canctl0 register provides various control bits of the mscan module as described below. 0x000f cantxerr r txerr7 txerr6 txerr5 txerr4 txerr3 txerr2 txerr1 txerr0 w 0x0010?x0013 canidar0? r ac7 ac6 ac5 ac4 ac3 ac2 ac1 ac0 w 0x0014?x0017 canidmrx r am7 am6 am5 am4 am3 am2 am1 am0 w 0x0018?x001b canidar4? r ac7 ac6 ac5 ac4 ac3 ac2 ac1 ac0 w 0x001c?x001f canidmr4? r am7 am6 am5 am4 am3 am2 am1 am0 w 0x0020?x002f canrxfg r see section 11.3.3, ?rogrammers model of message storage w 0x0030?x003f cantxfg r see section 11.3.3, ?rogrammers model of message storage w module base + 0x0000 access: user read/write (1) 76543210 r rxfrm rxact cswai synch time wupe slprq initrq w reset: 00000001 = unimplemented figure 11-4. mscan control register 0 (canctl0) register name bit 7 6 5 4 3 2 1 bit 0 = unimplemented or reserved figure 11-3. mscan register summary (continued)
freescales scalable controller area network (s12mscanv3) s12xs family reference manual, rev. 1.10 302 freescale semiconductor note the canctl0 register, except wupe, initrq, and slprq, is held in the reset state when the initialization mode is active (initrq = 1 and initak = 1). this register is writable again as soon as the initialization mode is exited (initrq = 0 and initak = 0). 1. read: anytime write: anytime when out of initialization mode; exceptions are read-only rxact and synch, rxfrm (which is set by the module only), and initrq (which is also writable in initialization mode) table 11-3. canctl0 register field descriptions field description 7 rxfrm (1) received frame flag this bit is read and clear only. it is set when a receiver has received a valid message correctly, independently of the ?ter con?uration. after it is set, it remains set until cleared by software or reset. clearing is done by writing a 1. writing a 0 is ignored. this bit is not valid in loopback mode. 0 no valid message was received since last clearing this ?g 1 a valid message was received since last clearing of this ?g 6 rxact receiver active status ?this read-only ?g indicates the mscan is receiving a message. the ?g is controlled by the receiver front end. this bit is not valid in loopback mode. 0 mscan is transmitting or idle 2 1 mscan is receiving a message (including when arbitration is lost) (2) 5 cswai (3) can stops in wait mode enabling this bit allows for lower power consumption in wait mode by disabling all the clocks at the cpu bus interface to the mscan module. 0 the module is not affected during wait mode 1 the module ceases to be clocked during wait mode 4 synch synchronized status this read-only ?g indicates whether the mscan is synchronized to the can bus and able to participate in the communication process. it is set and cleared by the mscan. 0 mscan is not synchronized to the can bus 1 mscan is synchronized to the can bus 3 time timer enable this bit activates an internal 16-bit wide free running timer which is clocked by the bit clock rate. if the timer is enabled, a 16-bit time stamp will be assigned to each transmitted/received message within the active tx/rx buffer. right after the eof of a valid message on the can bus, the time stamp is written to the highest bytes (0x000e, 0x000f) in the appropriate buffer (see section 11.3.3, ?rogrammers model of message storage ?. the internal timer is reset (all bits set to 0) when disabled. this bit is held low in initialization mode. 0 disable internal mscan timer 1 enable internal mscan timer 2 wupe (4) wake-up enable ?this con?uration bit allows the mscan to restart from sleep mode or from power down mode (entered from sleep) when traf? on can is detected (see section 11.4.5.5, ?scan sleep mode ?. this bit must be con?ured before sleep mode entry for the selected function to take effect. 0 wake-up disabled ?the mscan ignores traf? on can 1 wake-up enabled ?the mscan is able to restart
freescales scalable controller area network (s12mscanv3) s12xs family reference manual rev. 1.10 freescale semiconductor 303 11.3.2.2 mscan control register 1 (canctl1) the canctl1 register provides various control bits and handshake status information of the mscan module as described below. 1 slprq (5) sleep mode request ?this bit requests the mscan to enter sleep mode, which is an internal power saving mode (see section 11.4.5.5, ?scan sleep mode ?. the sleep mode request is serviced when the can bus is idle, i.e., the module is not receiving a message and all transmit buffers are empty. the module indicates entry to sleep mode by setting slpak = 1 (see section 11.3.2.2, ?scan control register 1 (canctl1) ?. slprq cannot be set while the wupif ?g is set (see section 11.3.2.5, ?scan receiver flag register (canrflg) ?. sleep mode will be active until slprq is cleared by the cpu or, depending on the setting of wupe, the mscan detects activity on the can bus and clears slprq itself. 0 running ?the mscan functions normally 1 sleep mode request ?the mscan enters sleep mode when can bus idle 0 initrq (6),(7) initialization mode request ?when this bit is set by the cpu, the mscan skips to initialization mode (see section 11.4.4.5, ?scan initialization mode ?. any ongoing transmission or reception is aborted and synchronization to the can bus is lost. the module indicates entry to initialization mode by setting initak = 1 ( section 11.3.2.2, ?scan control register 1 (canctl1) ?. the following registers enter their hard reset state and restore their default values: canctl0 (8) , canrflg (9) , canrier (10) , cantflg, cantier, cantarq, cantaak, and cantbsel. the registers canctl1, canbtr0, canbtr1, canidac, canidar0-7, and canidmr0-7 can only be written by the cpu when the mscan is in initialization mode (initrq = 1 and initak = 1). the values of the error counters are not affected by initialization mode. when this bit is cleared by the cpu, the mscan restarts and then tries to synchronize to the can bus. if the mscan is not in bus-off state, it synchronizes after 11 consecutive recessive bits on the can bus; if the mscan is in bus-off state, it continues to wait for 128 occurrences of 11 consecutive recessive bits. writing to other bits in canctl0, canrflg, canrier, cantflg, or cantier must be done only after initialization mode is exited, which is initrq = 0 and initak = 0. 0 normal operation 1 mscan in initialization mode 1. the mscan must be in normal mode for this bit to become set. 2. see the bosch can 2.0a/b speci?ation for a detailed de?ition of transmitter and receiver states. 3. in order to protect from accidentally violating the can protocol, txcan is immediately forced to a recessive state when the cpu enters wait (cswai = 1) or stop mode (see section 11.4.5.2, ?peration in wait mode and section 11.4.5.3, ?peration in stop mode ? . 4. the cpu has to make sure that the wupe register and the wupie wake-up interrupt enable register (see section 11.3.2.6, ?scan receiver interrupt enable register (canrier) ) is enabled, if the recovery mechanism from stop or wait is required. 5. the cpu cannot clear slprq before the mscan has entered sleep mode (slprq = 1 and slpak = 1). 6. the cpu cannot clear initrq before the mscan has entered initialization mode (initrq = 1 and initak = 1). 7. in order to protect from accidentally violating the can protocol, txcan is immediately forced to a recessive state when the initialization mode is requested by the cpu. thus, the recommended procedure is to bring the mscan into sleep mode (slprq = 1 and slpak = 1) before requesting initialization mode. 8. not including wupe, initrq, and slprq. 9. tstat1 and tstat0 are not affected by initialization mode. 10. rstat1 and rstat0 are not affected by initialization mode. table 11-3. canctl0 register field descriptions (continued) field description
freescales scalable controller area network (s12mscanv3) s12xs family reference manual, rev. 1.10 304 freescale semiconductor module base + 0x0001 access: user read/write (1) 1. read: anytime write: anytime in initialization mode (initrq = 1 and initak = 1); cane is write once 76543210 r cane clksrc loopb listen borm wupm slpak initak w reset: 00010001 = unimplemented figure 11-5. mscan control register 1 (canctl1) table 11-4. canctl1 register field descriptions field description 7 cane mscan enable 0 mscan module is disabled 1 mscan module is enabled 6 clksrc mscan clock source this bit de?es the clock source for the mscan module (only for systems with a clock generation module; section 11.4.3.2, ?lock system , and section figure 11-43., ?scan clocking scheme ,?. 0 mscan clock source is the oscillator clock 1 mscan clock source is the bus clock 5 loopb loopback self test mode when this bit is set, the mscan performs an internal loopback which can be used for self test operation. the bit stream output of the transmitter is fed back to the receiver internally. the rxcan input is ignored and the txcan output goes to the recessive state (logic 1). the mscan behaves as it does normally when transmitting and treats its own transmitted message as a message received from a remote node. in this state, the mscan ignores the bit sent during the ack slot in the can frame acknowledge ?ld to ensure proper reception of its own message. both transmit and receive interrupts are generated. 0 loopback self test disabled 1 loopback self test enabled 4 listen listen only mode this bit con?ures the mscan as a can bus monitor. when listen is set, all valid can messages with matching id are received, but no acknowledgement or error frames are sent out (see section 11.4.4.4, ?isten-only mode ?. in addition, the error counters are frozen. listen only mode supports applications which require ?ot plugging?or throughput analysis. the mscan is unable to transmit any messages when listen only mode is active. 0 normal operation 1 listen only mode activated 3 borm bus-off recovery mode ?this bit con?ures the bus-off state recovery mode of the mscan. refer to section 11.5.2, ?us-off recovery , for details. 0 automatic bus-off recovery (see bosch can 2.0a/b protocol speci?ation) 1 bus-off recovery upon user request 2 wupm wake-up mode ?if wupe in canctl0 is enabled, this bit de?es whether the integrated low-pass ?ter is applied to protect the mscan from spurious wake-up (see section 11.4.5.5, ?scan sleep mode ?. 0 mscan wakes up on any dominant level on the can bus 1 mscan wakes up only in case of a dominant pulse on the can bus that has a length of t wup
freescales scalable controller area network (s12mscanv3) s12xs family reference manual rev. 1.10 freescale semiconductor 305 11.3.2.3 mscan bus timing register 0 (canbtr0) the canbtr0 register con?ures various can bus timing parameters of the mscan module. 1 slpak sleep mode acknowledge ?this ?g indicates whether the mscan module has entered sleep mode (see section 11.4.5.5, ?scan sleep mode ?. it is used as a handshake ?g for the slprq sleep mode request. sleep mode is active when slprq = 1 and slpak = 1. depending on the setting of wupe, the mscan will clear the ?g if it detects activity on the can bus while in sleep mode. 0 running ?the mscan operates normally 1 sleep mode active ?the mscan has entered sleep mode 0 initak initialization mode acknowledge ?this ?g indicates whether the mscan module is in initialization mode (see section 11.4.4.5, ?scan initialization mode ?. it is used as a handshake ?g for the initrq initialization mode request. initialization mode is active when initrq = 1 and initak = 1. the registers canctl1, canbtr0, canbtr1, canidac, canidar0?anidar7, and canidmr0?anidmr7 can be written only by the cpu when the mscan is in initialization mode. 0 running ?the mscan operates normally 1 initialization mode active ?the mscan has entered initialization mode module base + 0x0002 access: user read/write (1) 1. read: anytime write: anytime in initialization mode (initrq = 1 and initak = 1) 76543210 r sjw1 sjw0 brp5 brp4 brp3 brp2 brp1 brp0 w reset: 00000000 figure 11-6. mscan bus timing register 0 (canbtr 0 ) table 11-5. canbtr 0 register field descriptions field description 7-6 sjw[1:0] synchronization jump width the synchronization jump width de?es the maximum number of time quanta (tq) clock cycles a bit can be shortened or lengthened to achieve resynchronization to data transitions on the can bus (see table 11-6 ). 5-0 brp[5:0] baud rate prescaler these bits determine the time quanta (tq) clock which is used to build up the bit timing (see table 11-7 ). table 11-6. synchronization jump width sjw1 sjw0 synchronization jump width 0 0 1 tq clock cycle 0 1 2 tq clock cycles 1 0 3 tq clock cycles 1 1 4 tq clock cycles table 11-4. canctl1 register field descriptions (continued) field description
freescales scalable controller area network (s12mscanv3) s12xs family reference manual, rev. 1.10 306 freescale semiconductor 11.3.2.4 mscan bus timing register 1 (canbtr1) the canbtr1 register con?ures various can bus timing parameters of the mscan module. table 11-7. baud rate prescaler brp5 brp4 brp3 brp2 brp1 brp0 prescaler value (p) 000000 1 000001 2 000010 3 000011 4 :::::: : 111111 64 module base + 0x0003 access: user read/write (1) 1. read: anytime write: anytime in initialization mode (initrq = 1 and initak = 1) 76543210 r samp tseg22 tseg21 tseg20 tseg13 tseg12 tseg11 tseg10 w reset: 00000000 figure 11-7. mscan bus timing register 1 (canbtr1) table 11-8. canbtr1 register field descriptions field description 7 samp sampling ?this bit determines the number of can bus samples taken per bit time. 0 one sample per bit. 1 three samples per bit (1) . if samp = 0, the resulting bit value is equal to the value of the single bit positioned at the sample point. if samp = 1, the resulting bit value is determined by using majority rule on the three total samples. for higher bit rates, it is recommended that only one sample is taken per bit time (samp = 0). 1. in this case, phase_seg1 must be at least 2 time quanta (tq). 6-4 tseg2[2:0] time segment 2 time segments within the bit time ? the number of clock cycles per bit time and the location of the sample point (see figure 11-44 ). time segment 2 (tseg2) values are programmable as shown in table 11-9 . 3-0 tseg1[3:0] time segment 1 time segments within the bit time ? the number of clock cycles per bit time and the location of the sample point (see figure 11-44 ). time segment 1 (tseg1) values are programmable as shown in table 11-10 .
freescales scalable controller area network (s12mscanv3) s12xs family reference manual rev. 1.10 freescale semiconductor 307 the bit time is determined by the oscillator frequency, the baud rate prescaler, and the number of time quanta (tq) clock cycles per bit (as shown in table 11-9 and table 11-10 ). eqn. 11-1 11.3.2.5 mscan receiver flag register (canrflg) a ?g can be cleared only by software (writing a 1 to the corresponding bit position) when the condition which caused the setting is no longer valid. every ?g has an associated interrupt enable bit in the canrier register. table 11-9. time segment 2 values tseg22 tseg21 tseg20 time segment 2 0 0 0 1 tq clock cycle (1) 1. this setting is not valid. please refer to table 11-37 for valid settings. 0 0 1 2 tq clock cycles ::: : 1 1 0 7 tq clock cycles 1 1 1 8 tq clock cycles table 11-10. time segment 1 values tseg13 tseg12 tseg11 tseg10 time segment 1 0 0 0 0 1 tq clock cycle (1) 1. this setting is not valid. please refer to table 11-37 for valid settings. 0 0 0 1 2 tq clock cycles 1 0 0 1 0 3 tq clock cycles 1 0 0 1 1 4 tq clock cycles :::: : 1 1 1 0 15 tq clock cycles 1 1 1 1 16 tq clock cycles module base + 0x0004 access: user read/write (1) 76543210 r wupif cscif rstat1 rstat0 tstat1 tstat0 ovrif rxf w reset: 00000000 = unimplemented figure 11-8. mscan receiver flag register (canrflg) bit time prescaler value () f canclk ----------------------------------------------------- - 1 timesegment1 timesegment2 ++ () ? =
freescales scalable controller area network (s12mscanv3) s12xs family reference manual, rev. 1.10 308 freescale semiconductor note the canrflg register is held in the reset state 1 when the initialization mode is active (initrq = 1 and initak = 1). this register is writable again as soon as the initialization mode is exited (initrq = 0 and initak = 0). 1. read: anytime write: anytime when not in initialization mode, except rstat[1:0] and tstat[1:0] ?gs which are read-only; write of 1 clears ?g; write of 0 is ignored 1. the rstat[1:0], tstat[1:0] bits are not affected by initialization mode. table 11-11. canrflg register field descriptions field description 7 wupif wake-up interrupt flag if the mscan detects can bus activity while in sleep mode (see section 11.4.5.5, ?scan sleep mode ,? and wupe = 1 in cantctl0 (see section 11.3.2.1, ?scan control register 0 (canctl0) ?, the module will set wupif. if not masked, a wake-up interrupt is pending while this ?g is set. 0 no wake-up activity observed while in sleep mode 1 mscan detected activity on the can bus and requested wake-up 6 cscif can status change interrupt flag ?this ?g is set when the mscan changes its current can bus status due to the actual value of the transmit error counter (tec) and the receive error counter (rec). an additional 4- bit (rstat[1:0], tstat[1:0]) status register, which is split into separate sections for tec/rec, informs the system on the actual can bus status (see section 11.3.2.6, ?scan receiver interrupt enable register (canrier) ?. if not masked, an error interrupt is pending while this ?g is set. cscif provides a blocking interrupt. that guarantees that the receiver/transmitter status bits (rstat/tstat) are only updated when no can status change interrupt is pending. if the tecs/recs change their current value after the cscif is asserted, which would cause an additional state change in the rstat/tstat bits, these bits keep their status until the current cscif interrupt is cleared again. 0 no change in can bus status occurred since last interrupt 1 mscan changed current can bus status 5-4 rstat[1:0] receiver status bits the values of the error counters control the actual can bus status of the mscan. as soon as the status change interrupt ?g (cscif) is set, these bits indicate the appropriate receiver related can bus status of the mscan. the coding for the bits rstat1, rstat0 is: 00 rxok: 0 receive error counter 96 01 rxwrn: 96 < receive error counter 127 10 rxerr: 127 < receive error counter 11 bus-off (1) : transmit error counter > 255 3-2 tstat[1:0] transmitter status bits the values of the error counters control the actual can bus status of the mscan. as soon as the status change interrupt ?g (cscif) is set, these bits indicate the appropriate transmitter related can bus status of the mscan. the coding for the bits tstat1, tstat0 is: 00 txok: 0 transmit error counter 96 01 txwrn: 96 < transmit error counter 127 10 txerr: 127 < transmit error counter 255 11 bus-off: transmit error counter > 255
freescales scalable controller area network (s12mscanv3) s12xs family reference manual rev. 1.10 freescale semiconductor 309 11.3.2.6 mscan receiver interrupt enable register (canrier) this register contains the interrupt enable bits for the interrupt ?gs described in the canrflg register. note the canrier register is held in the reset state when the initialization mode is active (initrq=1 and initak=1). this register is writable when not in initialization mode (initrq=0 and initak=0). the rstate[1:0], tstate[1:0] bits are not affected by initialization mode. 1 ovrif overrun interrupt flag this ?g is set when a data overrun condition occurs. if not masked, an error interrupt is pending while this ?g is set. 0 no data overrun condition 1 a data overrun detected 0 rxf (2) receive buffer full flag ?rxf is set by the mscan when a new message is shifted in the receiver fifo. this ?g indicates whether the shifted buffer is loaded with a correctly received message (matching identi?r, matching cyclic redundancy code (crc) and no other errors detected). after the cpu has read that message from the rxfg buffer in the receiver fifo, the rxf ?g must be cleared to release the buffer. a set rxf ?g prohibits the shifting of the next fifo entry into the foreground buffer (rxfg). if not masked, a receive interrupt is pending while this ?g is set. 0 no new message available within the rxfg 1 the receiver fifo is not empty. a new message is available in the rxfg 1. redundant information for the most critical can bus status which is ?us-off? this only occurs if the tx error counter exceeds a number of 255 errors. bus-off affects the receiver state. as soon as the transmitter leaves its bus-off state the receiver state skips to rxok too. refer also to tstat[1:0] coding in this register. 2. to ensure data integrity, do not read the receive buffer registers while the rxf ?g is cleared. for mcus with dual cpus, reading the receive buffer registers while the rxf ?g is cleared may result in a cpu fault condition. module base + 0x0005 access: user read/write (1) 1. read: anytime write: anytime when not in initialization mode 76543210 r wupie cscie rstate1 rstate0 tstate1 tstate0 ovrie rxfie w reset: 00000000 figure 11-9. mscan receiver interrupt enable register (canrier) table 11-11. canrflg register field descriptions (continued) field description
freescales scalable controller area network (s12mscanv3) s12xs family reference manual, rev. 1.10 310 freescale semiconductor 11.3.2.7 mscan transmitter flag register (cantflg) the transmit buffer empty ?gs each have an associated interrupt enable bit in the cantier register. table 11-12. canrier register field descriptions field description 7 wupie (1) 1. wupie and wupe (see section 11.3.2.1, ?scan control register 0 (canctl0) ? must both be enabled if the recovery mechanism from stop or wait is required. wake-up interrupt enable 0 no interrupt request is generated from this event. 1 a wake-up event causes a wake-up interrupt request. 6 cscie can status change interrupt enable 0 no interrupt request is generated from this event. 1 a can status change event causes an error interrupt request. 5-4 rstate[1:0] receiver status change enable these rstat enable bits control the sensitivity level in which receiver state changes are causing cscif interrupts. independent of the chosen sensitivity level the rstat ?gs continue to indicate the actual receiver state and are only updated if no cscif interrupt is pending. 00 do not generate any cscif interrupt caused by receiver state changes. 01 generate cscif interrupt only if the receiver enters or leaves ?us-off?state. discard other receiver state changes for generating cscif interrupt. 10 generate cscif interrupt only if the receiver enters or leaves ?xerr?or ?us-off (2) state. discard other receiver state changes for generating cscif interrupt. 11 generate cscif interrupt on all state changes. 2. bus-off state is only de?ed for transmitters by the can standard (see bosch can 2.0a/b protocol speci?ation). because the only possible state change for the transmitter from bus-off to txok also forces the receiver to skip its current state to rxok, the coding of the rxstat[1:0] ?gs de?e an additional bus-off state for the receiver (see section 11.3.2.5, ?scan receiver flag register (canrflg) ?. 3-2 tstate[1:0] transmitter status change enable these tstat enable bits control the sensitivity level in which transmitter state changes are causing cscif interrupts. independent of the chosen sensitivity level, the tstat ?gs continue to indicate the actual transmitter state and are only updated if no cscif interrupt is pending. 00 do not generate any cscif interrupt caused by transmitter state changes. 01 generate cscif interrupt only if the transmitter enters or leaves ?us-off?state. discard other transmitter state changes for generating cscif interrupt. 10 generate cscif interrupt only if the transmitter enters or leaves ?xerr?or ?us-off?state. discard other transmitter state changes for generating cscif interrupt. 11 generate cscif interrupt on all state changes. 1 ovrie overrun interrupt enable 0 no interrupt request is generated from this event. 1 an overrun event causes an error interrupt request. 0 rxfie receiver full interrupt enable 0 no interrupt request is generated from this event. 1 a receive buffer full (successful message reception) event causes a receiver interrupt request.
freescales scalable controller area network (s12mscanv3) s12xs family reference manual rev. 1.10 freescale semiconductor 311 note the cantflg register is held in the reset state when the initialization mode is active (initrq = 1 and initak = 1). this register is writable when not in initialization mode (initrq = 0 and initak = 0). 11.3.2.8 mscan transmitter interrupt enable register (cantier) this register contains the interrupt enable bits for the transmit buffer empty interrupt ?gs. module base + 0x0006 access: user read/write (1) 1. read: anytime write: anytime when not in initialization mode; write of 1 clears ?g, write of 0 is ignored 76543210 r0 0 0 00 txe2 txe1 txe0 w reset: 00000111 = unimplemented figure 11-10. mscan transmitter flag register (cantflg) table 11-13. cantflg register field descriptions field description 2-0 txe[2:0] transmitter buffer empty this ?g indicates that the associated transmit message buffer is empty, and thus not scheduled for transmission. the cpu must clear the ?g after a message is set up in the transmit buffer and is due for transmission. the mscan sets the ?g after the message is sent successfully. the ?g is also set by the mscan when the transmission request is successfully aborted due to a pending abort request (see section 11.3.2.9, ?scan transmitter message abort request register (cantarq) ?. if not masked, a transmit interrupt is pending while this ?g is set. clearing a txex ?g also clears the corresponding abtakx (see section 11.3.2.10, ?scan transmitter message abort acknowledge register (cantaak) ?. when a txex ?g is set, the corresponding abtrqx bit is cleared (see section 11.3.2.9, ?scan transmitter message abort request register (cantarq) ?. when listen-mode is active (see section 11.3.2.2, ?scan control register 1 (canctl1) ? the txex ?gs cannot be cleared and no transmission is started. read and write accesses to the transmit buffer will be blocked, if the corresponding txex bit is cleared (txex = 0) and the buffer is scheduled for transmission. 0 the associated message buffer is full (loaded with a message due for transmission) 1 the associated message buffer is empty (not scheduled) module base + 0x0007 access: user read/write (1) 76543210 r00000 txeie2 txeie1 txeie0 w reset: 00000000 = unimplemented figure 11-11. mscan transmitter interrupt enable register (cantier)
freescales scalable controller area network (s12mscanv3) s12xs family reference manual, rev. 1.10 312 freescale semiconductor note the cantier register is held in the reset state when the initialization mode is active (initrq = 1 and initak = 1). this register is writable when not in initialization mode (initrq = 0 and initak = 0). 11.3.2.9 mscan transmitter message abort request register (cantarq) the cantarq register allows abort request of queued messages as described below. note the cantarq register is held in the reset state when the initialization mode is active (initrq = 1 and initak = 1). this register is writable when not in initialization mode (initrq = 0 and initak = 0). 1. read: anytime write: anytime when not in initialization mode table 11-14. cantier register field descriptions field description 2-0 txeie[2:0] transmitter empty interrupt enable 0 no interrupt request is generated from this event. 1 a transmitter empty (transmit buffer available for transmission) event causes a transmitter empty interrupt request. module base + 0x0008 access: user read/write (1) 1. read: anytime write: anytime when not in initialization mode 76543210 r00000 abtrq2 abtrq1 abtrq0 w reset: 00000000 = unimplemented figure 11-12. mscan transmitter message abort request register (cantarq) table 11-15. cantarq register field descriptions field description 2-0 abtrq[2:0] abort request ?the cpu sets the abtrqx bit to request that a scheduled message buffer (txex = 0) be aborted. the mscan grants the request if the message has not already started transmission, or if the transmission is not successful (lost arbitration or error). when a message is aborted, the associated txe (see section 11.3.2.7, ?scan transmitter flag register (cantflg) ? and abort acknowledge ?gs (abtak, see section 11.3.2.10, ?scan transmitter message abort acknowledge register (cantaak) ? are set and a transmit interrupt occurs if enabled. the cpu cannot reset abtrqx. abtrqx is reset whenever the associated txe ?g is set. 0 no abort request 1 abort request pending
freescales scalable controller area network (s12mscanv3) s12xs family reference manual rev. 1.10 freescale semiconductor 313 11.3.2.10 mscan transmitter message abort acknowledge register (cantaak) the cantaak register indicates the successful abort of a queued message, if requested by the appropriate bits in the cantarq register. note the cantaak register is held in the reset state when the initialization mode is active (initrq = 1 and initak = 1). 11.3.2.11 mscan transmit buffer selection register (cantbsel) the cantbsel register allows the selection of the actual transmit message buffer, which then will be accessible in the cantxfg register space. module base + 0x0009 access: user read/write (1) 1. read: anytime write: unimplemented 76543210 r00000 abtak2 abtak1 abtak0 w reset: 00000000 = unimplemented figure 11-13. mscan transmitter message abort acknowledge register (cantaak) table 11-16. cantaak register field descriptions field description 2-0 abtak[2:0] abort acknowledge ?this ?g acknowledges that a message was aborted due to a pending abort request from the cpu. after a particular message buffer is ?gged empty, this ?g can be used by the application software to identify whether the message was aborted successfully or was sent anyway. the abtakx ?g is cleared whenever the corresponding txe ?g is cleared. 0 the message was not aborted. 1 the message was aborted. module base + 0x000a access: user read/write (1) 1. read: find the lowest ordered bit set to 1, all other bits will be read as 0 write: anytime when not in initialization mode 76543210 r00000 tx2 tx1 tx0 w reset: 00000000 = unimplemented figure 11-14. mscan transmit buffer selection register (cantbsel)
freescales scalable controller area network (s12mscanv3) s12xs family reference manual, rev. 1.10 314 freescale semiconductor note the cantbsel register is held in the reset state when the initialization mode is active (initrq = 1 and initak=1). this register is writable when not in initialization mode (initrq = 0 and initak = 0). the following gives a short programming example of the usage of the cantbsel register: to get the next available transmit buffer, application software must read the cantflg register and write this value back into the cantbsel register. in this example tx buffers tx1 and tx2 are available. the value read from cantflg is therefore 0b0000_0110. when writing this value back to cantbsel, the tx buffer tx1 is selected in the cantxfg because the lowest numbered bit set to 1 is at bit position 1. reading back this value out of cantbsel results in 0b0000_0010, because only the lowest numbered bit position set to 1 is presented. this mechanism eases the application softwares selection of the next available tx buffer. ldaa cantflg; value read is 0b0000_0110 staa cantbsel; value written is 0b0000_0110 ldaa cantbsel; value read is 0b0000_0010 if all transmit message buffers are deselected, no accesses are allowed to the cantxfg registers. 11.3.2.12 mscan identi?r acceptance control register (canidac) the canidac register is used for identi?r acceptance control as described below. table 11-17. cantbsel register field descriptions field description 2-0 tx[2:0] transmit buffer select ?the lowest numbered bit places the respective transmit buffer in the cantxfg register space (e.g., tx1 = 1 and tx0 = 1 selects transmit buffer tx0; tx1 = 1 and tx0 = 0 selects transmit buffer tx1). read and write accesses to the selected transmit buffer will be blocked, if the corresponding txex bit is cleared and the buffer is scheduled for transmission (see section 11.3.2.7, ?scan transmitter flag register (cantflg) ?. 0 the associated message buffer is deselected 1 the associated message buffer is selected, if lowest numbered bit module base + 0x000b access: user read/write (1) 1. read: anytime write: anytime in initialization mode (initrq = 1 and initak = 1), except bits idhitx, which are read-only 76543210 r0 0 idam1 idam0 0 idhit2 idhit1 idhit0 w reset: 00000000 = unimplemented figure 11-15. mscan identi?r acceptance control register (canidac)
freescales scalable controller area network (s12mscanv3) s12xs family reference manual rev. 1.10 freescale semiconductor 315 the idhitx indicators are always related to the message in the foreground buffer (rxfg). when a message gets shifted into the foreground buffer of the receiver fifo the indicators are updated as well. 11.3.2.13 mscan reserved register this register is reserved for factory testing of the mscan module and is not available in normal system operating modes. table 11-18. canidac register field descriptions field description 5-4 idam[1:0] identi?r acceptance mode the cpu sets these ?gs to de?e the identi?r acceptance ?ter organization (see section 11.4.3, ?denti?r acceptance filter ?. table 11-19 summarizes the different settings. in ?ter closed mode, no message is accepted such that the foreground buffer is never reloaded. 2-0 idhit[2:0] identi?r acceptance hit indicator ?the mscan sets these ?gs to indicate an identi?r acceptance hit (see section 11.4.3, ?denti?r acceptance filter ?. table 11-20 summarizes the different settings. table 11-19. identi?r acceptance mode settings idam1 idam0 identi?r acceptance mode 0 0 two 32-bit acceptance ?ters 0 1 four 16-bit acceptance ?ters 1 0 eight 8-bit acceptance ?ters 1 1 filter closed table 11-20. identi?r acceptance hit indication idhit2 idhit1 idhit0 identi?r acceptance hit 0 0 0 filter 0 hit 0 0 1 filter 1 hit 0 1 0 filter 2 hit 0 1 1 filter 3 hit 1 0 0 filter 4 hit 1 0 1 filter 5 hit 1 1 0 filter 6 hit 1 1 1 filter 7 hit
freescales scalable controller area network (s12mscanv3) s12xs family reference manual, rev. 1.10 316 freescale semiconductor note writing to this register when in special system operating modes can alter the mscan functionality. 11.3.2.14 mscan miscellaneous register (canmisc) this register provides additional features. 11.3.2.15 mscan receive error counter (canrxerr) this register re?cts the status of the mscan receive error counter. module base + 0x000c to module base + 0x000d access: user read/write (1) 1. read: always reads zero in normal system operation modes write: unimplemented in normal system operation modes 76543210 r00000000 w reset: 00000000 = unimplemented figure 11-16. mscan reserved register module base + 0x000d access: user read/write (1) 1. read: anytime write: anytime; write of ??clears ?g; write of ??ignored 76543210 r0000000 bohold w reset: 00000000 = unimplemented figure 11-17. mscan miscellaneous register (canmisc) table 11-21. canmisc register field descriptions field description 0 bohold bus-off state hold until user request ?if borm is set in mscan control register 1 (canctl1) , this bit indicates whether the module has entered the bus-off state. clearing this bit requests the recovery from bus-off. refer to section 11.5.2, ?us-off recovery , for details. 0 module is not bus-off or recovery has been requested by user in bus-off state 1 module is bus-off and holds this state until user request
freescales scalable controller area network (s12mscanv3) s12xs family reference manual rev. 1.10 freescale semiconductor 317 note reading this register when in any other mode other than sleep or initialization mode may return an incorrect value. for mcus with dual cpus, this may result in a cpu fault condition. writing to this register when in special modes can alter the mscan functionality. 11.3.2.16 mscan transmit error counter (cantxerr) this register re?cts the status of the mscan transmit error counter. note reading this register when in any other mode other than sleep or initialization mode, may return an incorrect value. for mcus with dual cpus, this may result in a cpu fault condition. writing to this register when in special modes can alter the mscan functionality. module base + 0x000e access: user read/write (1) 1. read: only when in sleep mode (slprq = 1 and slpak = 1) or initialization mode (initrq = 1 and initak = 1) write: unimplemented 76543210 r rxerr7 rxerr6 rxerr5 rxerr4 rxerr3 rxerr2 rxerr1 rxerr0 w reset: 00000000 = unimplemented figure 11-18. mscan receive error counter (canrxerr) module base + 0x000f access: user read/write (1) 1. read: only when in sleep mode (slprq = 1 and slpak = 1) or initialization mode (initrq = 1 and initak = 1) write: unimplemented 76543210 r txerr7 txerr6 txerr5 txerr4 txerr3 txerr2 txerr1 txerr0 w reset: 00000000 = unimplemented figure 11-19. mscan transmit error counter (cantxerr)
freescales scalable controller area network (s12mscanv3) s12xs family reference manual, rev. 1.10 318 freescale semiconductor 11.3.2.17 mscan identi?r acceptance registers (canidar0-7) on reception, each message is written into the background receive buffer. the cpu is only signalled to read the message if it passes the criteria in the identi?r acceptance and identi?r mask registers (accepted); otherwise, the message is overwritten by the next message (dropped). the acceptance registers of the mscan are applied on the idr0?dr3 registers (see section 11.3.3.1, ?denti?r registers (idr0?dr3) ? of incoming messages in a bit by bit manner (see section 11.4.3, ?denti?r acceptance filter ?. for extended identi?rs, all four acceptance and mask registers are applied. for standard identi?rs, only the ?st two (canidar0/1, canidmr0/1) are applied. module base + 0x0010 to module base + 0x0013 access: user read/write (1) 1. read: anytime write: anytime in initialization mode (initrq = 1 and initak = 1) 76543210 r ac7 ac6 ac5 ac4 ac3 ac2 ac1 ac0 w reset 00000000 figure 11-20. mscan identi?r acceptance registers (first bank) ?canidar0?anidar3 table 11-22. canidar0?anidar3 register field descriptions field description 7-0 ac[7:0] acceptance code bits ac[7:0] comprise a user-de?ed sequence of bits with which the corresponding bits of the related identi?r register (idrn) of the receive message buffer are compared. the result of this comparison is then masked with the corresponding identi?r mask register. module base + 0x0018 to module base + 0x001b access: user read/write (1) 1. read: anytime write: anytime in initialization mode (initrq = 1 and initak = 1) 76543210 r ac7 ac6 ac5 ac4 ac3 ac2 ac1 ac0 w reset 00000000 figure 11-21. mscan identi?r acceptance registers (second bank) ?canidar4?anidar7
freescales scalable controller area network (s12mscanv3) s12xs family reference manual rev. 1.10 freescale semiconductor 319 11.3.2.18 mscan identi?r mask registers (canidmr0?anidmr7) the identi?r mask register speci?s which of the corresponding bits in the identi?r acceptance register are relevant for acceptance ?tering. to receive standard identi?rs in 32 bit ?ter mode, it is required to program the last three bits (am[2:0]) in the mask registers canidmr1 and canidmr5 to ?ont care. to receive standard identi?rs in 16 bit ?ter mode, it is required to program the last three bits (am[2:0]) in the mask registers canidmr1, canidmr3, canidmr5, and canidmr7 to ?ont care. table 11-23. canidar4?anidar7 register field descriptions field description 7-0 ac[7:0] acceptance code bits ac[7:0] comprise a user-de?ed sequence of bits with which the corresponding bits of the related identi?r register (idrn) of the receive message buffer are compared. the result of this comparison is then masked with the corresponding identi?r mask register. module base + 0x0014 to module base + 0x0017 access: user read/write (1) 1. read: anytime write: anytime in initialization mode (initrq = 1 and initak = 1) 76543210 r am7 am6 am5 am4 am3 am2 am1 am0 w reset 00000000 figure 11-22. mscan identi?r mask registers (first bank) ?canidmr0?anidmr3 table 11-24. canidmr0?anidmr3 register field descriptions field description 7-0 am[7:0] acceptance mask bits if a particular bit in this register is cleared, this indicates that the corresponding bit in the identi?r acceptance register must be the same as its identi?r bit before a match is detected. the message is accepted if all such bits match. if a bit is set, it indicates that the state of the corresponding bit in the identi?r acceptance register does not affect whether or not the message is accepted. 0 match corresponding acceptance code register and identi?r bits 1 ignore corresponding acceptance code register bit module base + 0x001c to module base + 0x001f access: user read/write (1) 76543210 r am7 am6 am5 am4 am3 am2 am1 am0 w reset 00000000 figure 11-23. mscan identi?r mask registers (second bank) ?canidmr4?anidmr7
freescales scalable controller area network (s12mscanv3) s12xs family reference manual, rev. 1.10 320 freescale semiconductor 11.3.3 programmers model of message storage the following section details the organization of the receive and transmit message buffers and the associated control registers. to simplify the programmer interface, the receive and transmit message buffers have the same outline. each message buffer allocates 16 bytes in the memory map containing a 13 byte data structure. an additional transmit buffer priority register (tbpr) is de?ed for the transmit buffers. within the last two bytes of this memory map, the mscan stores a special 16-bit time stamp, which is sampled from an internal timer after successful transmission or reception of a message. this feature is only available for transmit and receiver buffers, if the time bit is set (see section 11.3.2.1, ?scan control register 0 (canctl0) ?. the time stamp register is written by the mscan. the cpu can only read these registers. 1. read: anytime write: anytime in initialization mode (initrq = 1 and initak = 1) table 11-25. canidmr4?anidmr7 register field descriptions field description 7-0 am[7:0] acceptance mask bits if a particular bit in this register is cleared, this indicates that the corresponding bit in the identi?r acceptance register must be the same as its identi?r bit before a match is detected. the message is accepted if all such bits match. if a bit is set, it indicates that the state of the corresponding bit in the identi?r acceptance register does not affect whether or not the message is accepted. 0 match corresponding acceptance code register and identi?r bits 1 ignore corresponding acceptance code register bit
freescales scalable controller area network (s12mscanv3) s12xs family reference manual rev. 1.10 freescale semiconductor 321 figure 11-24 shows the common 13-byte data structure of receive and transmit buffers for extended identi?rs. the mapping of standard identi?rs into the idr registers is shown in figure 11-25 . all bits of the receive and transmit buffers are ??out of reset because of ram-based implementation 1 . all reserved or unused bits of the receive and transmit buffers always read ?? table 11-26. message buffer organization offset address register access 0x00x0 identi?r register 0 r/w 0x00x1 identi?r register 1 r/w 0x00x2 identi?r register 2 r/w 0x00x3 identi?r register 3 r/w 0x00x4 data segment register 0 r/w 0x00x5 data segment register 1 r/w 0x00x6 data segment register 2 r/w 0x00x7 data segment register 3 r/w 0x00x8 data segment register 4 r/w 0x00x9 data segment register 5 r/w 0x00xa data segment register 6 r/w 0x00xb data segment register 7 r/w 0x00xc data length register r/w 0x00xd transmit buffer priority register (1) 1. not applicable for receive buffers r/w 0x00xe time stamp register (high byte) r 0x00xf time stamp register (low byte) r 1. exception: the transmit buffer priority registers are 0 out of reset.
freescales scalable controller area network (s12mscanv3) s12xs family reference manual, rev. 1.10 322 freescale semiconductor figure 11-24. receive/transmit message buffer ?extended identi?r mapping register name bit 7 654321 bit0 0x00x0 idr0 r id28 id27 id26 id25 id24 id23 id22 id21 w 0x00x1 idr1 r id20 id19 id18 srr (=1) ide (=1) id17 id16 id15 w 0x00x2 idr2 r id14 id13 id12 id11 id10 id9 id8 id7 w 0x00x3 idr3 r id6 id5 id4 id3 id2 id1 id0 rtr w 0x00x4 dsr0 r db7 db6 db5 db4 db3 db2 db1 db0 w 0x00x5 dsr1 r db7 db6 db5 db4 db3 db2 db1 db0 w 0x00x6 dsr2 r db7 db6 db5 db4 db3 db2 db1 db0 w 0x00x7 dsr3 r db7 db6 db5 db4 db3 db2 db1 db0 w 0x00x8 dsr4 r db7 db6 db5 db4 db3 db2 db1 db0 w 0x00x9 dsr5 r db7 db6 db5 db4 db3 db2 db1 db0 w 0x00xa dsr6 r db7 db6 db5 db4 db3 db2 db1 db0 w 0x00xb dsr7 r db7 db6 db5 db4 db3 db2 db1 db0 w 0x00xc dlr r dlc3 dlc2 dlc1 dlc0 w
freescales scalable controller area network (s12mscanv3) s12xs family reference manual rev. 1.10 freescale semiconductor 323 read: for transmit buffers, anytime when txex ?g is set (see section 11.3.2.7, ?scan transmitter flag register (cantflg) ? and the corresponding transmit buffer is selected in cantbsel (see section 11.3.2.11, ?scan transmit buffer selection register (cantbsel) ?. for receive buffers, only when rxf ?g is set (see section 11.3.2.5, ?scan receiver flag register (canrflg) ?. write: for transmit buffers, anytime when txex ?g is set (see section 11.3.2.7, ?scan transmitter flag register (cantflg) ? and the corresponding transmit buffer is selected in cantbsel (see section 11.3.2.11, ?scan transmit buffer selection register (cantbsel) ?. unimplemented for receive buffers. reset: unde?ed because of ram-based implementation 11.3.3.1 identi?r registers (idr0?dr3) the identi?r registers for an extended format identi?r consist of a total of 32 bits: id[28:0], srr, ide, and rtr. the identi?r registers for a standard format identi?r consist of a total of 13 bits: id[10:0], rtr, and ide. = unused, always read ? figure 11-25. receive/transmit message buffer ?standard identi?r mapping register name bit 7 654321 bit 0 idr0 0x00x0 r id10 id9 id8 id7 id6 id5 id4 id3 w idr1 0x00x1 r id2 id1 id0 rtr ide (=0) w idr2 0x00x2 r w idr3 0x00x3 r w = unused, always read ? figure 11-24. receive/transmit message buffer ?extended identi?r mapping (continued) register name bit 7 654321 bit0
freescales scalable controller area network (s12mscanv3) s12xs family reference manual, rev. 1.10 324 freescale semiconductor 11.3.3.1.1 idr0?dr3 for extended identi?r mapping module base + 0x00x0 76543210 r id28 id27 id26 id25 id24 id23 id22 id21 w reset: xxxxxxxx figure 11-26. identi?r register 0 (idr0) ?extended identi?r mapping table 11-27. idr0 register field descriptions ?extended field description 7-0 id[28:21] extended format identi?r the identi?rs consist of 29 bits (id[28:0]) for the extended format. id28 is the most signi?ant bit and is transmitted ?st on the can bus during the arbitration procedure. the priority of an identi?r is de?ed to be highest for the smallest binary number. module base + 0x00x1 76543210 r id20 id19 id18 srr (=1) ide (=1) id17 id16 id15 w reset: xxxxxxxx figure 11-27. identi?r register 1 (idr1) ?extended identi?r mapping table 11-28. idr1 register field descriptions ?extended field description 7-5 id[20:18] extended format identi?r the identi?rs consist of 29 bits (id[28:0]) for the extended format. id28 is the most signi?ant bit and is transmitted ?st on the can bus during the arbitration procedure. the priority of an identi?r is de?ed to be highest for the smallest binary number. 4 srr substitute remote request ?this ?ed recessive bit is used only in extended format. it must be set to 1 by the user for transmission buffers and is stored as received on the can bus for receive buffers. 3 ide id extended this ?g indicates whether the extended or standard identi?r format is applied in this buffer. in the case of a receive buffer, the ?g is set as received and indicates to the cpu how to process the buffer identi?r registers. in the case of a transmit buffer, the ?g indicates to the mscan what type of identi?r to send. 0 standard format (11 bit) 1 extended format (29 bit) 2-0 id[17:15] extended format identi?r the identi?rs consist of 29 bits (id[28:0]) for the extended format. id28 is the most signi?ant bit and is transmitted ?st on the can bus during the arbitration procedure. the priority of an identi?r is de?ed to be highest for the smallest binary number.
freescales scalable controller area network (s12mscanv3) s12xs family reference manual rev. 1.10 freescale semiconductor 325 module base + 0x00x2 76543210 r id14 id13 id12 id11 id10 id9 id8 id7 w reset: xxxxxxxx figure 11-28. identi?r register 2 (idr2) ?extended identi?r mapping table 11-29. idr2 register field descriptions ?extended field description 7-0 id[14:7] extended format identi?r the identi?rs consist of 29 bits (id[28:0]) for the extended format. id28 is the most signi?ant bit and is transmitted ?st on the can bus during the arbitration procedure. the priority of an identi?r is de?ed to be highest for the smallest binary number. module base + 0x00x3 76543210 r id6 id5 id4 id3 id2 id1 id0 rtr w reset: xxxxxxxx figure 11-29. identi?r register 3 (idr3) ?extended identi?r mapping table 11-30. idr3 register field descriptions ?extended field description 7-1 id[6:0] extended format identi?r the identi?rs consist of 29 bits (id[28:0]) for the extended format. id28 is the most signi?ant bit and is transmitted ?st on the can bus during the arbitration procedure. the priority of an identi?r is de?ed to be highest for the smallest binary number. 0 rtr remote transmission request ?this ?g re?cts the status of the remote transmission request bit in the can frame. in the case of a receive buffer, it indicates the status of the received frame and supports the transmission of an answering frame in software. in the case of a transmit buffer, this ?g de?es the setting of the rtr bit to be sent. 0 data frame 1 remote frame
freescales scalable controller area network (s12mscanv3) s12xs family reference manual, rev. 1.10 326 freescale semiconductor 11.3.3.1.2 idr0?dr3 for standard identi?r mapping module base + 0x00x0 76543210 r id10 id9 id8 id7 id6 id5 id4 id3 w reset: xxxxxxxx figure 11-30. identi?r register 0 ?standard mapping table 11-31. idr0 register field descriptions ?standard field description 7-0 id[10:3] standard format identi?r the identi?rs consist of 11 bits (id[10:0]) for the standard format. id10 is the most signi?ant bit and is transmitted ?st on the can bus during the arbitration procedure. the priority of an identi?r is de?ed to be highest for the smallest binary number. see also id bits in table 11-32 . module base + 0x00x1 76543210 r id2 id1 id0 rtr ide (=0) w reset: xxxxxxxx = unused; always read ? figure 11-31. identi?r register 1 ?standard mapping table 11-32. idr1 register field descriptions field description 7-5 id[2:0] standard format identi?r the identi?rs consist of 11 bits (id[10:0]) for the standard format. id10 is the most signi?ant bit and is transmitted ?st on the can bus during the arbitration procedure. the priority of an identi?r is de?ed to be highest for the smallest binary number. see also id bits in table 11-31 . 4 rtr remote transmission request this ?g re?cts the status of the remote transmission request bit in the can frame. in the case of a receive buffer, it indicates the status of the received frame and supports the transmission of an answering frame in software. in the case of a transmit buffer, this ?g de?es the setting of the rtr bit to be sent. 0 data frame 1 remote frame 3 ide id extended this ?g indicates whether the extended or standard identi?r format is applied in this buffer. in the case of a receive buffer, the ?g is set as received and indicates to the cpu how to process the buffer identi?r registers. in the case of a transmit buffer, the ?g indicates to the mscan what type of identi?r to send. 0 standard format (11 bit) 1 extended format (29 bit)
freescales scalable controller area network (s12mscanv3) s12xs family reference manual rev. 1.10 freescale semiconductor 327 11.3.3.2 data segment registers (dsr0-7) the eight data segment registers, each with bits db[7:0], contain the data to be transmitted or received. the number of bytes to be transmitted or received is determined by the data length code in the corresponding dlr register. module base + 0x00x2 76543210 r w reset: xxxxxxxx = unused; always read ? figure 11-32. identi?r register 2 ?standard mapping module base + 0x00x3 76543210 r w reset: xxxxxxxx = unused; always read ? figure 11-33. identi?r register 3 ?standard mapping module base + 0x00x4 to module base + 0x00xb 76543210 r db7 db6 db5 db4 db3 db2 db1 db0 w reset: xxxxxxxx figure 11-34. data segment registers (dsr0?sr7) ?extended identi?r mapping table 11-33. dsr0?sr7 register field descriptions field description 7-0 db[7:0] data bits 7-0
freescales scalable controller area network (s12mscanv3) s12xs family reference manual, rev. 1.10 328 freescale semiconductor 11.3.3.3 data length register (dlr) this register keeps the data length ?ld of the can frame. 11.3.3.4 transmit buffer priority register (tbpr) this register de?es the local priority of the associated message buffer. the local priority is used for the internal prioritization process of the mscan and is de?ed to be highest for the smallest binary number. the mscan implements the following internal prioritization mechanisms: all transmission buffers with a cleared txex ?g participate in the prioritization immediately before the sof (start of frame) is sent. module base + 0x00xc 76543210 r dlc3 dlc2 dlc1 dlc0 w reset: xxxxxxxx = unused; always read ? figure 11-35. data length register (dlr) ?extended identi?r mapping table 11-34. dlr register field descriptions field description 3-0 dlc[3:0] data length code bits the data length code contains the number of bytes (data byte count) of the respective message. during the transmission of a remote frame, the data length code is transmitted as programmed while the number of transmitted data bytes is always 0. the data byte count ranges from 0 to 8 for a data frame. table 11-35 shows the effect of setting the dlc bits. table 11-35. data length codes data length code data byte count dlc3 dlc2 dlc1 dlc0 00000 00011 00102 00113 01004 01015 01106 01117 10008
freescales scalable controller area network (s12mscanv3) s12xs family reference manual rev. 1.10 freescale semiconductor 329 the transmission buffer with the lowest local priority ?ld wins the prioritization. in cases of more than one buffer having the same lowest priority, the message buffer with the lower index number wins. 11.3.3.5 time stamp register (tsrh?srl) if the time bit is enabled, the mscan will write a time stamp to the respective registers in the active transmit or receive buffer right after the eof of a valid message on the can bus (see section 11.3.2.1, ?scan control register 0 (canctl0) ?. in case of a transmission, the cpu can only read the time stamp after the respective transmit buffer has been ?gged empty. the timer value, which is used for stamping, is taken from a free running internal can bit clock. a timer overrun is not indicated by the mscan. the timer is reset (all bits set to 0) during initialization mode. the cpu can only read the time stamp registers. module base + 0x00xd access: user read/write (1) 1. read: anytime when txex ?g is set (see section 11.3.2.7, ?scan transmitter flag register (cantflg) ? and the corresponding transmit buffer is selected in cantbsel (see section 11.3.2.11, ?scan transmit buffer selection register (cantbsel) ? write: anytime when txex ?g is set (see section 11.3.2.7, ?scan transmitter flag register (cantflg) ? and the corresponding transmit buffer is selected in cantbsel (see section 11.3.2.11, ?scan transmit buffer selection register (cantbsel) ? 76543210 r prio7 prio6 prio5 prio4 prio3 prio2 prio1 prio0 w reset: 00000000 figure 11-36. transmit buffer priority register (tbpr) module base + 0x00xe access: user read/write (1) 1. read: anytime when txex ?g is set (see section 11.3.2.7, ?scan transmitter flag register (cantflg) ? and the corresponding transmit buffer is selected in cantbsel (see section 11.3.2.11, ?scan transmit buffer selection register (cantbsel) ? write: unimplemented 76543210 r tsr15 tsr14 tsr13 tsr12 tsr11 tsr10 tsr9 tsr8 w reset: xxxxxxxx figure 11-37. time stamp register ?high byte (tsrh)
freescales scalable controller area network (s12mscanv3) s12xs family reference manual, rev. 1.10 330 freescale semiconductor module base + 0x00xf access: user read/write (1) 1. read: anytime when txex ?g is set (see section 11.3.2.7, ?scan transmitter flag register (cantflg) ? and the corresponding transmit buffer is selected in cantbsel (see section 11.3.2.11, ?scan transmit buffer selection register (cantbsel) ? write: unimplemented 76543210 r tsr7 tsr6 tsr5 tsr4 tsr3 tsr2 tsr1 tsr0 w reset: xxxxxxxx figure 11-38. time stamp register ?low byte (tsrl)
freescales scalable controller area network (s12mscanv3) s12xs family reference manual rev. 1.10 freescale semiconductor 331 11.4 functional description 11.4.1 general this section provides a complete functional description of the mscan. 11.4.2 message storage figure 11-39. user model for message buffer organization mscan rx0 rx1 can receive / transmit engine memory mapped i/o cpu bus mscan tx2 txe2 prio receiver transmitter rxbg txbg tx0 txe0 prio txbg tx1 prio txe1 txfg cpu bus rx2 rx3 rx4 rxf rxfg
freescales scalable controller area network (s12mscanv3) s12xs family reference manual, rev. 1.10 332 freescale semiconductor the mscan facilitates a sophisticated message storage system which addresses the requirements of a broad range of network applications. 11.4.2.1 message transmit background modern application layer software is built upon two fundamental assumptions: any can node is able to send out a stream of scheduled messages without releasing the can bus between the two messages. such nodes arbitrate for the can bus immediately after sending the previous message and only release the can bus in case of lost arbitration. the internal message queue within any can node is organized such that the highest priority message is sent out ?st, if more than one message is ready to be sent. the behavior described in the bullets above cannot be achieved with a single transmit buffer. that buffer must be reloaded immediately after the previous message is sent. this loading process lasts a ?ite amount of time and must be completed within the inter-frame sequence (ifs) to be able to send an uninterrupted stream of messages. even if this is feasible for limited can bus speeds, it requires that the cpu reacts with short latencies to the transmit interrupt. a double buffer scheme de-couples the reloading of the transmit buffer from the actual message sending and, therefore, reduces the reactiveness requirements of the cpu. problems can arise if the sending of a message is ?ished while the cpu re-loads the second buffer. no buffer would then be ready for transmission, and the can bus would be released. at least three transmit buffers are required to meet the ?st of the above requirements under all circumstances. the mscan has three transmit buffers. the second requirement calls for some sort of internal prioritization which the mscan implements with the ?ocal priority?concept described in section 11.4.2.2, ?ransmit structures . 11.4.2.2 transmit structures the mscan triple transmit buffer scheme optimizes real-time performance by allowing multiple messages to be set up in advance. the three buffers are arranged as shown in figure 11-39 . all three buffers have a 13-byte data structure similar to the outline of the receive buffers (see section 11.3.3, ?rogrammers model of message storage ?. an additional transmit buffer priority register (tbpr) contains an 8-bit local priority ?ld (prio) (see section 11.3.3.4, ?ransmit buffer priority register (tbpr) ?. the remaining two bytes are used for time stamping of a message, if required (see section 11.3.3.5, ?ime stamp register (tsrh?srl) ?. to transmit a message, the cpu must identify an available transmit buffer, which is indicated by a set transmitter buffer empty (txex) ?g (see section 11.3.2.7, ?scan transmitter flag register (cantflg) ?. if a transmit buffer is available, the cpu must set a pointer to this buffer by writing to the cantbsel register (see section 11.3.2.11, ?scan transmit buffer selection register (cantbsel) ?. this makes the respective buffer accessible within the cantxfg address space (see section 11.3.3, ?rogrammers model of message storage ?. the algorithmic feature associated with the cantbsel register simpli?s the transmit buffer selection. in addition, this scheme makes the handler
freescales scalable controller area network (s12mscanv3) s12xs family reference manual rev. 1.10 freescale semiconductor 333 software simpler because only one address area is applicable for the transmit process, and the required address space is minimized. the cpu then stores the identi?r, the control bits, and the data content into one of the transmit buffers. finally, the buffer is ?gged as ready for transmission by clearing the associated txe ?g. the mscan then schedules the message for transmission and signals the successful transmission of the buffer by setting the associated txe ?g. a transmit interrupt (see section 11.4.7.2, ?ransmit interrupt ? is generated 1 when txex is set and can be used to drive the application software to re-load the buffer. if more than one buffer is scheduled for transmission when the can bus becomes available for arbitration, the mscan uses the local priority setting of the three buffers to determine the prioritization. for this purpose, every transmit buffer has an 8-bit local priority ?ld (prio). the application software programs this ?ld when the message is set up. the local priority re?cts the priority of this particular message relative to the set of messages being transmitted from this node. the lowest binary value of the prio ?ld is de?ed to be the highest priority. the internal scheduling process takes place whenever the mscan arbitrates for the can bus. this is also the case after the occurrence of a transmission error. when a high priority message is scheduled by the application software, it may become necessary to abort a lower priority message in one of the three transmit buffers. because messages that are already in transmission cannot be aborted, the user must request the abort by setting the corresponding abort request bit (abtrq) (see section 11.3.2.9, ?scan transmitter message abort request register (cantarq) ?) the mscan then grants the request, if possible, by: 1. setting the corresponding abort acknowledge ?g (abtak) in the cantaak register. 2. setting the associated txe ?g to release the buffer. 3. generating a transmit interrupt. the transmit interrupt handler software can determine from the setting of the abtak ?g whether the message was aborted (abtak = 1) or sent (abtak = 0). 11.4.2.3 receive structures the received messages are stored in a ve stage input fifo. the ve message buffers are alternately mapped into a single memory area (see figure 11-39 ). the background receive buffer (rxbg) is exclusively associated with the mscan, but the foreground receive buffer (rxfg) is addressable by the cpu (see figure 11-39 ). this scheme simpli?s the handler software because only one address area is applicable for the receive process. all receive buffers have a size of 15 bytes to store the can control bits, the identi?r (standard or extended), the data contents, and a time stamp, if enabled (see section 11.3.3, ?rogrammers model of message storage ?. the receiver full ?g (rxf) (see section 11.3.2.5, ?scan receiver flag register (canrflg) ? signals the status of the foreground receive buffer. when the buffer contains a correctly received message with a matching identi?r, this ?g is set. on reception, each message is checked to see whether it passes the ?ter (see section 11.4.3, ?denti?r acceptance filter ? and simultaneously is written into the active rxbg. after successful reception of a valid message, the mscan shifts the content of rxbg into the receiver fifo, sets the rxf ?g, and 1. the transmit interrupt occurs only if not masked. a polling scheme can be applied on txex also.
freescales scalable controller area network (s12mscanv3) s12xs family reference manual, rev. 1.10 334 freescale semiconductor generates a receive interrupt 1 (see section 11.4.7.3, ?eceive interrupt ? to the cpu. the users receive handler must read the received message from the rxfg and then reset the rxf ?g to acknowledge the interrupt and to release the foreground buffer. a new message, which can follow immediately after the ifs ?ld of the can frame, is received into the next available rxbg. if the mscan receives an invalid message in its rxbg (wrong identi?r, transmission errors, etc.) the actual contents of the buffer will be over-written by the next message. the buffer will then not be shifted into the fifo. when the mscan module is transmitting, the mscan receives its own transmitted messages into the background receive buffer, rxbg, but does not shift it into the receiver fifo, generate a receive interrupt, or acknowledge its own messages on the can bus. the exception to this rule is in loopback mode (see section 11.3.2.2, ?scan control register 1 (canctl1) ? where the mscan treats its own messages exactly like all other incoming messages. the mscan receives its own transmitted messages in the event that it loses arbitration. if arbitration is lost, the mscan must be prepared to become a receiver. an overrun condition occurs when all receive message buffers in the fifo are ?led with correctly received messages with accepted identi?rs and another message is correctly received from the can bus with an accepted identi?r. the latter message is discarded and an error interrupt with overrun indication is generated if enabled (see section 11.4.7.5, ?rror interrupt ?. the mscan remains able to transmit messages while the receiver fifo is being ?led, but all incoming messages are discarded. as soon as a receive buffer in the fifo is available again, new valid messages will be accepted. 11.4.3 identi?r acceptance filter the mscan identi?r acceptance registers (see section 11.3.2.12, ?scan identi?r acceptance control register (canidac) ? de?e the acceptable patterns of the standard or extended identi?r (id[10:0] or id[28:0]). any of these bits can be marked ?ont care?in the mscan identi?r mask registers (see section 11.3.2.18, ?scan identi?r mask registers (canidmr0?anidmr7) ?. a ?ter hit is indicated to the application software by a set receive buffer full ?g (rxf = 1) and three bits in the canidac register (see section 11.3.2.12, ?scan identi?r acceptance control register (canidac) ?. these identi?r hit ?gs (idhit[2:0]) clearly identify the ?ter section that caused the acceptance. they simplify the application softwares task to identify the cause of the receiver interrupt. if more than one hit occurs (two or more ?ters match), the lower hit has priority. a very ?xible programmable generic identi?r acceptance ?ter has been introduced to reduce the cpu interrupt loading. the ?ter is programmable to operate in four different modes: two identi?r acceptance ?ters, each to be applied to: the full 29 bits of the extended identi?r and to the following bits of the can 2.0b frame: remote transmission request (rtr) identi?r extension (ide) substitute remote request (srr) the 11 bits of the standard identi?r plus the rtr and ide bits of the can 2.0a/b messages. this mode implements two ?ters for a full length can 2.0b compliant extended identi?r. although this mode can be used for standard identi?rs, it is recommended to use the four or eight identi?r acceptance ?ters. 1. the receive interrupt occurs only if not masked. a polling scheme can be applied on rxf also.
freescales scalable controller area network (s12mscanv3) s12xs family reference manual rev. 1.10 freescale semiconductor 335 figure 11-40 shows how the ?st 32-bit ?ter bank (canidar0?anidar3, canidmr0?anidmr3) produces a ?ter 0 hit. similarly, the second ?ter bank (canidar4?anidar7, canidmr4?anidmr7) produces a ?ter 1 hit. four identi?r acceptance ?ters, each to be applied to: the 14 most signi?ant bits of the extended identi?r plus the srr and ide bits of can 2.0b messages. the 11 bits of the standard identi?r, the rtr and ide bits of can 2.0a/b messages. figure 11-41 shows how the ?st 32-bit ?ter bank (canidar0?anida3, canidmr0?canidmr) produces ?ter 0 and 1 hits. similarly, the second ?ter bank (canidar4?anidar7, canidmr4?anidmr7) produces ?ter 2 and 3 hits. eight identi?r acceptance ?ters, each to be applied to the ?st 8 bits of the identi?r. this mode implements eight independent ?ters for the ?st 8 bits of a can 2.0a/b compliant standard identi?r or a can 2.0b compliant extended identi?r. figure 11-42 shows how the ?st 32-bit ?ter bank (canidar0?anidar3, canidmr0?anidmr3) produces ?ter 0 to 3 hits. similarly, the second ?ter bank (canidar4?anidar7, canidmr4?anidmr7) produces ?ter 4 to 7 hits. closed ?ter. no can message is copied into the foreground buffer rxfg, and the rxf ?g is never set. figure 11-40. 32-bit maskable identi?r acceptance filter id28 id21 idr0 id10 id3 idr0 id20 id15 idr1 id2 ide idr1 id14 id7 idr2 id10 id3 idr2 id6 rtr idr3 id10 id3 idr3 ac7 ac0 canidar0 am7 am0 canidmr0 ac7 ac0 canidar1 am7 am0 canidmr1 ac7 ac0 canidar2 am7 am0 canidmr2 ac7 ac0 canidar3 am7 am0 canidmr3 id accepted (filter 0 hit) can 2.0b extended identi?r can 2.0a/b standard identi?r
freescales scalable controller area network (s12mscanv3) s12xs family reference manual, rev. 1.10 336 freescale semiconductor figure 11-41. 16-bit maskable identi?r acceptance filters id28 id21 idr0 id10 id3 idr0 id20 id15 idr1 id2 ide idr1 id14 id7 idr2 id10 id3 idr2 id6 rtr idr3 id10 id3 idr3 ac7 ac0 canidar0 am7 am0 canidmr0 ac7 ac0 canidar1 am7 am0 canidmr1 id accepted (filter 0 hit) ac7 ac0 canidar2 am7 am0 canidmr2 ac7 ac0 canidar3 am7 am0 canidmr3 id accepted (filter 1 hit) can 2.0b extended identi?r can 2.0a/b standard identi?r
freescales scalable controller area network (s12mscanv3) s12xs family reference manual rev. 1.10 freescale semiconductor 337 figure 11-42. 8-bit maskable identi?r acceptance filters can 2.0b extended identi?r can 2.0a/b standard identi?r ac7 ac0 cidar3 am7 am0 cidmr3 id accepted (filter 3 hit) ac7 ac0 cidar2 am7 am0 cidmr2 id accepted (filter 2 hit) ac7 ac0 cidar1 am7 am0 cidmr1 id accepted (filter 1 hit) id28 id21 idr0 id10 id3 idr0 id20 id15 idr1 id2 ide idr1 id14 id7 idr2 id10 id3 idr2 id6 rtr idr3 id10 id3 idr3 ac7 ac0 cidar0 am7 am0 cidmr0 id accepted (filter 0 hit)
freescales scalable controller area network (s12mscanv3) s12xs family reference manual, rev. 1.10 338 freescale semiconductor 11.4.3.1 protocol violation protection the mscan protects the user from accidentally violating the can protocol through programming errors. the protection logic implements the following features: the receive and transmit error counters cannot be written or otherwise manipulated. all registers which control the con?uration of the mscan cannot be modi?d while the mscan is on-line. the mscan has to be in initialization mode. the corresponding initrq/initak handshake bits in the canctl0/canctl1 registers (see section 11.3.2.1, ?scan control register 0 (canctl0) ? serve as a lock to protect the following registers: mscan control 1 register (canctl1) mscan bus timing registers 0 and 1 (canbtr0, canbtr1) mscan identi?r acceptance control register (canidac) mscan identi?r acceptance registers (canidar0?anidar7) mscan identi?r mask registers (canidmr0?anidmr7) the txcan is immediately forced to a recessive state when the mscan goes into the power down mode or initialization mode (see section 11.4.5.6, ?scan power down mode , and section 11.4.4.5, ?scan initialization mode ?. the mscan enable bit (cane) is writable only once in normal system operation modes, which provides further protection against inadvertently disabling the mscan. 11.4.3.2 clock system figure 11-43 shows the structure of the mscan clock generation circuitry. figure 11-43. mscan clocking scheme the clock source bit (clksrc) in the canctl1 register ( 11.3.2.2/11-303 ) de?es whether the internal canclk is connected to the output of a crystal oscillator (oscillator clock) or to the bus clock. the clock source has to be chosen such that the tight oscillator tolerance requirements (up to 0.4%) of the can protocol are met. additionally, for high can bus rates (1 mbps), a 45% to 55% duty cycle of the clock is required. if the bus clock is generated from a pll, it is recommended to select the oscillator clock rather than the bus clock due to jitter considerations, especially at the faster can bus rates. bus clock oscillator clock mscan canclk clksrc clksrc prescaler (1 .. 64) time quanta clock (tq)
freescales scalable controller area network (s12mscanv3) s12xs family reference manual rev. 1.10 freescale semiconductor 339 for microcontrollers without a clock and reset generator (crg), canclk is driven from the crystal oscillator (oscillator clock). a programmable prescaler generates the time quanta (tq) clock from canclk. a time quantum is the atomic unit of time handled by the mscan. eqn. 11-2 a bit time is subdivided into three segments as described in the bosch can speci?ation. (see figure 11- 44 ): sync_seg: this segment has a ?ed length of one time quantum. signal edges are expected to happen within this section. time segment 1: this segment includes the prop_seg and the phase_seg1 of the can standard. it can be programmed by setting the parameter tseg1 to consist of 4 to 16 time quanta. time segment 2: this segment represents the phase_seg2 of the can standard. it can be programmed by setting the tseg2 parameter to be 2 to 8 time quanta long. eqn. 11-3 figure 11-44. segments within the bit time tq f canclk prescaler value ( ) ---------------------------------------------------- -- = bit rate f tq number of time quanta () -------------------------------------------------------------------------------- - = sync_seg time segment 1 time segment 2 1 4 ... 16 2 ... 8 8 ... 25 time quanta = 1 bit time nrz signal sample point (single or triple sampling) (prop_seg + phase_seg1) (phase_seg2) transmit point
freescales scalable controller area network (s12mscanv3) s12xs family reference manual, rev. 1.10 340 freescale semiconductor the synchronization jump width (see the bosch can speci?ation for details) can be programmed in a range of 1 to 4 time quanta by setting the sjw parameter. the sync_seg, tseg1, tseg2, and sjw parameters are set by programming the mscan bus timing registers (canbtr0, canbtr1) (see section 11.3.2.3, ?scan bus timing register 0 (canbtr0) and section 11.3.2.4, ?scan bus timing register 1 (canbtr1) ?. table 11-37 gives an overview of the can compliant segment settings and the related parameter values. note it is the users responsibility to ensure the bit time settings are in compliance with the can standard. 11.4.4 modes of operation 11.4.4.1 normal system operating modes the mscan module behaves as described within this speci?ation in all normal system operating modes. write restrictions exist for some registers. table 11-36. time segment syntax syntax description sync_seg system expects transitions to occur on the can bus during this period. transmit point a node in transmit mode transfers a new value to the can bus at this point. sample point a node in receive mode samples the can bus at this point. if the three samples per bit option is selected, then this point marks the position of the third sample. table 11-37. can standard compliant bit time segment settings time segment 1 tseg1 time segment 2 tseg2 synchronization jump width sjw 5 .. 10 4 .. 9 2 1 1 .. 2 0 .. 1 4 .. 11 3 .. 10 3 2 1 .. 3 0 .. 2 5 .. 12 4 .. 11 4 3 1 .. 4 0 .. 3 6 .. 13 5 .. 12 5 4 1 .. 4 0 .. 3 7 .. 14 6 .. 13 6 5 1 .. 4 0 .. 3 8 .. 15 7 .. 14 7 6 1 .. 4 0 .. 3 9 .. 16 8 .. 15 8 7 1 .. 4 0 .. 3
freescales scalable controller area network (s12mscanv3) s12xs family reference manual rev. 1.10 freescale semiconductor 341 11.4.4.2 special system operating modes the mscan module behaves as described within this speci?ation in all special system operating modes. write restrictions which exist on speci? registers in normal modes are lifted for test purposes in special modes. 11.4.4.3 emulation modes in all emulation modes, the mscan module behaves just like in normal system operating modes as described within this speci?ation. 11.4.4.4 listen-only mode in an optional can bus monitoring mode (listen-only), the can node is able to receive valid data frames and valid remote frames, but it sends only ?ecessive?bits on the can bus. in addition, it cannot start a transmission. if the mac sub-layer is required to send a ?ominant bit (ack bit, overload ?g, or active error ?g), the bit is rerouted internally so that the mac sub-layer monitors this ?ominant?bit, although the can bus may remain in recessive state externally. 11.4.4.5 mscan initialization mode the mscan enters initialization mode when it is enabled (cane=1). when entering initialization mode during operation, any on-going transmission or reception is immediately aborted and synchronization to the can bus is lost, potentially causing can protocol violations. to protect the can bus system from fatal consequences of violations, the mscan immediately drives txcan into a recessive state. note the user is responsible for ensuring that the mscan is not active when initialization mode is entered. the recommended procedure is to bring the mscan into sleep mode (slprq = 1 and slpak = 1) before setting the initrq bit in the canctl0 register. otherwise, the abort of an on-going message can cause an error condition and can impact other can bus devices. in initialization mode, the mscan is stopped. however, interface registers remain accessible. this mode is used to reset the canctl0, canrflg, canrier, cantflg, cantier, cantarq, cantaak, and cantbsel registers to their default values. in addition, the mscan enables the con?uration of the canbtr0, canbtr1 bit timing registers; canidac; and the canidar, canidmr message ?ters. see section 11.3.2.1, ?scan control register 0 (canctl0) , for a detailed description of the initialization mode.
freescales scalable controller area network (s12mscanv3) s12xs family reference manual, rev. 1.10 342 freescale semiconductor figure 11-45. initialization request/acknowledge cycle due to independent clock domains within the mscan, initrq must be synchronized to all domains by using a special handshake mechanism. this handshake causes additional synchronization delay (see figure 11-45 ). if there is no message transfer ongoing on the can bus, the minimum delay will be two additional bus clocks and three additional can clocks. when all parts of the mscan are in initialization mode, the initak ?g is set. the application software must use initak as a handshake indication for the request (initrq) to go into initialization mode. note the cpu cannot clear initrq before initialization mode (initrq = 1 and initak = 1) is active. 11.4.5 low-power options if the mscan is disabled (cane = 0), the mscan clocks are stopped for power saving. if the mscan is enabled (cane = 1), the mscan has two additional modes with reduced power consumption, compared to normal mode: sleep and power down mode. in sleep mode, power consumption is reduced by stopping all clocks except those to access the registers from the cpu side. in power down mode, all clocks are stopped and no power is consumed. table 11-38 summarizes the combinations of mscan and cpu modes. a particular combination of modes is entered by the given settings on the cswai and slprq/slpak bits. sync sync bus cloc k domain can cloc k domain cpu init request init flag initak flag initrq sync. initak sync. initrq initak
freescales scalable controller area network (s12mscanv3) s12xs family reference manual rev. 1.10 freescale semiconductor 343 11.4.5.1 operation in run mode as shown in table 11-38 , only mscan sleep mode is available as low power option when the cpu is in run mode. 11.4.5.2 operation in wait mode the wai instruction puts the mcu in a low power consumption stand-by mode. if the cswai bit is set, additional power can be saved in power down mode because the cpu clocks are stopped. after leaving this power down mode, the mscan restarts and enters normal mode again. while the cpu is in wait mode, the mscan can be operated in normal mode and generate interrupts (registers can be accessed via background debug mode). 11.4.5.3 operation in stop mode the stop instruction puts the mcu in a low power consumption stand-by mode. in stop mode, the mscan is set in power down mode regardless of the value of the slprq/slpak and cswai bits ( table 11-38 ). 11.4.5.4 mscan normal mode this is a non-power-saving mode. enabling the mscan puts the module from disabled mode into normal mode. in this mode the module can either be in initialization mode or out of initialization mode. see section 11.4.4.5, ?scan initialization mode ? table 11-38. cpu vs. mscan operating modes cpu mode mscan mode normal reduced power consumption sleep power down disabled (cane=0) run cswai = x (1) slprq = 0 slpak = 0 1. ??means don? care. cswai = x slprq = 1 slpak = 1 cswai = x slprq = x slpak = x wait cswai = 0 slprq = 0 slpak = 0 cswai = 0 slprq = 1 slpak = 1 cswai = 1 slprq = x slpak = x cswai = x slprq = x slpak = x stop cswai = x slprq = x slpak = x cswai = x slprq = x slpak = x
freescales scalable controller area network (s12mscanv3) s12xs family reference manual, rev. 1.10 344 freescale semiconductor 11.4.5.5 mscan sleep mode the cpu can request the mscan to enter this low power mode by asserting the slprq bit in the canctl0 register. the time when the mscan enters sleep mode depends on a ?ed synchronization delay and its current activity: if there are one or more message buffers scheduled for transmission (txex = 0), the mscan will continue to transmit until all transmit message buffers are empty (txex = 1, transmitted successfully or aborted) and then goes into sleep mode. if the mscan is receiving, it continues to receive and goes into sleep mode as soon as the can bus next becomes idle. if the mscan is neither transmitting nor receiving, it immediately goes into sleep mode. figure 11-46. sleep request / acknowledge cycle note the application software must avoid setting up a transmission (by clearing one or more txex ?g(s)) and immediately request sleep mode (by setting slprq). whether the mscan starts transmitting or goes into sleep mode directly depends on the exact sequence of operations. if sleep mode is active, the slprq and slpak bits are set ( figure 11-46 ). the application software must use slpak as a handshake indication for the request (slprq) to go into sleep mode. when in sleep mode (slprq = 1 and slpak = 1), the mscan stops its internal clocks. however, clocks that allow register accesses from the cpu side continue to run. if the mscan is in bus-off state, it stops counting the 128 occurrences of 11 consecutive recessive bits due to the stopped clocks. txcan remains in a recessive state. if rxf = 1, the message can be read and rxf can be cleared. shifting a new message into the foreground buffer of the receiver fifo (rxfg) does not take place while in sleep mode. it is possible to access the transmit buffers and to clear the associated txe ?gs. no message abort takes place while in sleep mode. sync sync bus cloc k domain can cloc k domain mscan in sleep mode cpu sleep request slprq flag slpak flag slprq sync. slpak sync. slprq slpak
freescales scalable controller area network (s12mscanv3) s12xs family reference manual rev. 1.10 freescale semiconductor 345 if the wupe bit in canctl0 is not asserted, the mscan will mask any activity it detects on can. rxcan is therefore held internally in a recessive state. this locks the mscan in sleep mode. wupe must be set before entering sleep mode to take effect. the mscan is able to leave sleep mode (wake up) only when: can bus activity occurs and wupe = 1 or the cpu clears the slprq bit note the cpu cannot clear the slprq bit before sleep mode (slprq = 1 and slpak = 1) is active. after wake-up, the mscan waits for 11 consecutive recessive bits to synchronize to the can bus. as a consequence, if the mscan is woken-up by a can frame, this frame is not received. the receive message buffers (rxfg and rxbg) contain messages if they were received before sleep mode was entered. all pending actions will be executed upon wake-up; copying of rxbg into rxfg, message aborts and message transmissions. if the mscan remains in bus-off state after sleep mode was exited, it continues counting the 128 occurrences of 11 consecutive recessive bits. 11.4.5.6 mscan power down mode the mscan is in power down mode ( table 11-38 ) when cpu is in stop mode or cpu is in wait mode and the cswai bit is set when entering the power down mode, the mscan immediately stops all ongoing transmissions and receptions, potentially causing can protocol violations. to protect the can bus system from fatal consequences of violations to the above rule, the mscan immediately drives txcan into a recessive state. note the user is responsible for ensuring that the mscan is not active when power down mode is entered. the recommended procedure is to bring the mscan into sleep mode before the stop or wai instruction (if cswai is set) is executed. otherwise, the abort of an ongoing message can cause an error condition and impact other can bus devices. in power down mode, all clocks are stopped and no registers can be accessed. if the mscan was not in sleep mode before power down mode became active, the module performs an internal recovery cycle after powering up. this causes some ?ed delay before the module enters normal mode again.
freescales scalable controller area network (s12mscanv3) s12xs family reference manual, rev. 1.10 346 freescale semiconductor 11.4.5.7 disabled mode the mscan is in disabled mode out of reset (cane=0). all module clocks are stopped for power saving, however the register map can still be accessed as speci?d. 11.4.5.8 programmable wake-up function the mscan can be programmed to wake up from sleep or power down mode as soon as can bus activity is detected (see control bit wupe in mscan control register 0 (canctl0). the sensitivity to existing can bus action can be modi?d by applying a low-pass ?ter function to the rxcan input line (see control bit wupm in section 11.3.2.2, ?scan control register 1 (canctl1) ?. this feature can be used to protect the mscan from wake-up due to short glitches on the can bus lines. such glitches can result from?or example?lectromagnetic interference within noisy environments. 11.4.6 reset initialization the reset state of each individual bit is listed in section 11.3.2, ?egister descriptions , which details all the registers and their bit-?lds. 11.4.7 interrupts this section describes all interrupts originated by the mscan. it documents the enable bits and generated ?gs. each interrupt is listed and described separately. 11.4.7.1 description of interrupt operation the mscan supports four interrupt vectors (see table 11-39 ), any of which can be individually masked (for details see section 11.3.2.6, ?scan receiver interrupt enable register (canrier) ?to section 11.3.2.8, ?scan transmitter interrupt enable register (cantier) ?. refer to the device overview section to determine the dedicated interrupt vector addresses. 11.4.7.2 transmit interrupt at least one of the three transmit buffers is empty (not scheduled) and can be loaded to schedule a message for transmission. the txex ?g of the empty message buffer is set. table 11-39. interrupt vectors interrupt source ccr mask local enable wake-up interrupt (wupif) i bit canrier (wupie) error interrupts interrupt (cscif, ovrif) i bit canrier (cscie, ovrie) receive interrupt (rxf) i bit canrier (rxfie) transmit interrupts (txe[2:0]) i bit cantier (txeie[2:0])
freescales scalable controller area network (s12mscanv3) s12xs family reference manual rev. 1.10 freescale semiconductor 347 11.4.7.3 receive interrupt a message is successfully received and shifted into the foreground buffer (rxfg) of the receiver fifo. this interrupt is generated immediately after receiving the eof symbol. the rxf ?g is set. if there are multiple messages in the receiver fifo, the rxf ?g is set as soon as the next message is shifted to the foreground buffer. 11.4.7.4 wake-up interrupt a wake-up interrupt is generated if activity on the can bus occurs during mscan sleep or power-down mode. note this interrupt can only occur if the mscan was in sleep mode (slprq = 1 and slpak = 1) before entering power down mode, the wake-up option is enabled (wupe = 1), and the wake-up interrupt is enabled (wupie = 1). 11.4.7.5 error interrupt an error interrupt is generated if an overrun of the receiver fifo, error, warning, or bus-off condition occurrs. mscan receiver flag register (canrflg) indicates one of the following conditions: overrun an overrun condition of the receiver fifo as described in section 11.4.2.3, ?eceive structures , occurred. can status change ?the actual value of the transmit and receive error counters control the can bus state of the mscan. as soon as the error counters skip into a critical range (tx/rx- warning, tx/rx-error, bus-off) the mscan ?gs an error condition. the status change, which caused the error condition, is indicated by the tstat and rstat ?gs (see section 11.3.2.5, ?scan receiver flag register (canrflg) ?and section 11.3.2.6, ?scan receiver interrupt enable register (canrier) ?. 11.4.7.6 interrupt acknowledge interrupts are directly associated with one or more status ?gs in either the mscan receiver flag register (canrflg) or the mscan transmitter flag register (cantflg). interrupts are pending as long as one of the corresponding ?gs is set. the ?gs in canrflg and cantflg must be reset within the interrupt handler to handshake the interrupt. the ?gs are reset by writing a 1 to the corresponding bit position. a ?g cannot be cleared if the respective condition prevails. note it must be guaranteed that the cpu clears only the bit causing the current interrupt. for this reason, bit manipulation instructions (bset) must not be used to clear interrupt ?gs. these instructions may cause accidental clearing of interrupt ?gs which are set after entering the current interrupt service routine.
freescales scalable controller area network (s12mscanv3) s12xs family reference manual, rev. 1.10 348 freescale semiconductor 11.5 initialization/application information 11.5.1 mscan initialization the procedure to initially start up the mscan module out of reset is as follows: 1. assert cane 2. write to the con?uration registers in initialization mode 3. clear initrq to leave initialization mode if the con?uration of registers which are only writable in initialization mode shall be changed: 1. bring the module into sleep mode by setting slprq and awaiting slpak to assert after the can bus becomes idle. 2. enter initialization mode: assert initrq and await initak 3. write to the con?uration registers in initialization mode 4. clear initrq to leave initialization mode and continue 11.5.2 bus-off recovery the bus-off recovery is user con?urable. the bus-off state can either be left automatically or on user request. for reasons of backwards compatibility, the mscan defaults to automatic recovery after reset. in this case, the mscan will become error active again after counting 128 occurrences of 11 consecutive recessive bits on the can bus (see the bosch can speci?ation for details). if the mscan is con?ured for user request (borm set in mscan control register 1 (canctl1)), the recovery from bus-off starts after both independent events have become true: 128 occurrences of 11 consecutive recessive bits on the can bus have been monitored bohold in mscan miscellaneous register (canmisc) has been cleared by the user these two events may occur in any order.
s12xs family reference manual, rev. 1.10 freescale semiconductor 349 chapter 12 periodic interrupt timer (s12pit24b4cv1) table 12-1. revision history 12.1 introduction the period interrupt timer (pit) is an array of 24-bit timers that can be used to trigger peripheral modules or raise periodic interrupts. refer to figure 12-1 for a simpli?d block diagram. 12.1.1 glossary 12.1.2 features the pit includes these features: four timers implemented as modulus down-counters with independent time-out periods. time-out periods selectable between 1 and 2 24 bus clock cycles. time-out equals m*n bus clock cycles with 1 <= m <= 256 and 1 <= n <= 65536. timers that can be enabled individually. four time-out interrupts. four time-out trigger output signals available to trigger peripheral modules. start of timer channels can be aligned to each other. 12.1.3 modes of operation refer to the soc guide for a detailed explanation of the chip modes. version number revision date effective date author description of changes 01.00 28-apr-05 28-apr-05 initial release 01.01 05-jul-05 05-jul-05 added application section, removed table 1-1 acronyms and abbreviations pit periodic interrupt timer isr interrupt service routine ccr condition code register soc system on chip micro time bases clock periods of the 16-bit timer modulus down-counters, which are generated by the 8-bit modulus down-counters.
periodic interrupt timer (s12pit24b4cv1) s12xs family reference manual, rev. 1.10 350 freescale semiconductor run mode this is the basic mode of operation. wait mode pit operation in wait mode is controlled by the pitswai bit located in the pitcflmt register. in wait mode, if the bus clock is globally enabled and if the pitswai bit is clear, the pit operates like in run mode. in wait mode, if the pitswai bit is set, the pit module is stalled. stop mode in full stop mode or pseudo stop mode, the pit module is stalled. freeze mode pit operation in freeze mode is controlled by the pitfrz bit located in the pitcflmt register. in freeze mode, if the pitfrz bit is clear, the pit operates like in run mode. in freeze mode, if the pitfrz bit is set, the pit module is stalled. 12.1.4 block diagram figure 12-1 shows a block diagram of the pit module. figure 12-1. pit24b4c block diagram 12.2 external signal description the pit module has no external pins. time-out 0 time-out 1 time-out 2 time-out 3 16-bit timer 1 16-bit timer 3 16-bit timer 0 16-bit timer 2 bus clock micro time base 0 micro time base 1 interrupt 0 trigger 0 interface interrupt 1 trigger 1 interface interrupt 2 trigger 2 interface interrupt 3 trigger 3 interface 8-bit micro timer 0 8-bit micro timer 1
periodic interrupt timer (s12pit24b4cv1) s12xs family reference manual, rev. 1.10 freescale semiconductor 351 12.3 register de?ition this section consists of register descriptions in address order of the pit. each description includes a standard register diagram with an associated ?ure number. details of register bit and ?ld function follow the register diagrams, in bit order. register name bit 7 6 5 4 3 2 1 bit 0 0x0000 pitcflmt r pite pitswai pitfrz 00000 w pflmt1 pflmt0 0x0001 pitflt r00000000 w pflt3 pflt2 pflt1 pflt0 0x0002 pitce r0000 pce3 pce2 pce1 pce0 w 0x0003 pitmux r0000 pmux3 pmux2 pmux1 pmux0 w 0x0004 pitinte r0000 pinte3 pinte2 pinte1 pinte0 w 0x0005 pittf r0000 ptf3 ptf2 ptf1 ptf0 w 0x0006 pitmtld0 r pmtld7 pmtld6 pmtld5 pmtld4 pmtld3 pmtld2 pmtld1 pmtld0 w 0x0007 pitmtld1 r pmtld7 pmtld6 pmtld5 pmtld4 pmtld3 pmtld2 pmtld1 pmtld0 w 0x0008 pitld0 (high) r pld15 pld14 pld13 pld12 pld11 pld10 pld9 pld8 w 0x0009 pitld0 (low) r pld7 pld6 pld5 pld4 pld3 pld2 pld1 pld0 w 0x000a pitcnt0 (high) r pcnt15 pcnt14 pcnt13 pcnt12 pcnt11 pcnt10 pcnt9 pcnt8 w 0x000b pitcnt0 (low) r pcnt7 pcnt6 pcnt5 pcnt4 pcnt3 pcnt2 pcnt1 pcnt0 w 0x000c pitld1 (high) r pld15 pld14 pld13 pld12 pld11 pld10 pld9 pld8 w = unimplemented or reserved figure 12-2. pit register summary (sheet 1 of 2)
periodic interrupt timer (s12pit24b4cv1) s12xs family reference manual, rev. 1.10 352 freescale semiconductor 0x000d pitld1 (low) r pld7 pld6 pld5 pld4 pld3 pld2 pld1 pld0 w 0x000e pitcnt1 (high) r pcnt15 pcnt14 pcnt13 pcnt12 pcnt11 pcnt10 pcnt9 pcnt8 w 0x000f pitcnt1 (low) r pcnt7 pcnt6 pcnt5 pcnt4 pcnt3 pcnt2 pcnt1 pcnt0 w 0x0010 pitld2 (high) r pld15 pld14 pld13 pld12 pld11 pld10 pld9 pld8 w 0x0011 pitld2 (low) r pld7 pld6 pld5 pld4 pld3 pld2 pld1 pld0 w 0x0012 pitcnt2 (high) r pcnt15 pcnt14 pcnt13 pcnt12 pcnt11 pcnt10 pcnt9 pcnt8 w 0x0013 pitcnt2 (low) r pcnt7 pcnt6 pcnt5 pcnt4 pcnt3 pcnt2 pcnt1 pcnt0 w 0x0014 pitld3 (high) r pld15 pld14 pld13 pld12 pld11 pld10 pld9 pld8 w 0x0015 pitld3 (low) r pld7 pld6 pld5 pld4 pld3 pld2 pld1 pld0 w 0x0016 pitcnt3 (high) r pcnt15 pcnt14 pcnt13 pcnt12 pcnt11 pcnt10 pcnt9 pcnt8 w 0x0017 pitcnt3 (low) r pcnt7 pcnt6 pcnt5 pcnt4 pcnt3 pcnt2 pcnt1 pcnt0 w 0x0018 ? 0x0027 reserved r00000000 w register name bit 7 6 5 4 3 2 1 bit 0 = unimplemented or reserved figure 12-2. pit register summary (sheet 2 of 2)
periodic interrupt timer (s12pit24b4cv1) s12xs family reference manual, rev. 1.10 freescale semiconductor 353 12.3.0.1 pit control and force load micro timer register (pitcflmt) read: anytime write: anytime; writes to the reserved bits have no effect module base + 0x0000 76543210 r pite pitswai pitfrz 00000 w pflmt1 pflmt0 reset 0 0 0 00000 = unimplemented or reserved figure 12-3. pit control and force load micro timer register (pitcflmt) table 12-2. pitcflmt field descriptions field description 7 pite pit module enable bit ?this bit enables the pit module. if pite is cleared, the pit module is disabled and ?g bits in the pittf register are cleared. when pite is set, individually enabled timers (pce set) start down- counting with the corresponding load register values. 0 pit disabled (lower power consumption). 1 pit is enabled. 6 pitswai pit stop in wait mode bit ?this bit is used for power conservation while in wait mode. 0 pit operates normally in wait mode 1 pit clock generation stops and freezes the pit module when in wait mode 5 pitfrz pit counter freeze while in freeze mode bit ?when during debugging a breakpoint (freeze mode) is encountered it is useful in many cases to freeze the pit counters to avoid e.g. interrupt generation. the pitfrz bit controls the pit operation while in freeze mode. 0 pit operates normally in freeze mode 1 pit counters are stalled when in freeze mode 1:0 pflmt[1:0] pit force load bits for micro timer 1:0 these bits have only an effect if the corresponding micro timer is active and if the pit module is enabled (pite set). writing a one into a pflmt bit loads the corresponding 8-bit micro timer load register into the 8-bit micro timer down-counter. writing a zero has no effect. reading these bits will always return zero. note: a micro timer force load affects all timer channels that use the corresponding micro time base.
periodic interrupt timer (s12pit24b4cv1) s12xs family reference manual, rev. 1.10 354 freescale semiconductor 12.3.0.2 pit force load timer register (pitflt) read: anytime write: anytime 12.3.0.3 pit channel enable register (pitce) read: anytime write: anytime module base + 0x0001 76543210 r00000000 w pflt3 pflt2 pflt1 pflt0 reset 0 0 0 00000 figure 12-4. pit force load timer register (pitflt) table 12-3. pitflt field descriptions field description 3:0 pflt[3:0] pit force load bits for timer 3-0 ?these bits have only an effect if the corresponding timer channel (pce set) is enabled and if the pit module is enabled (pite set). writing a one into a pflt bit loads the corresponding 16-bit timer load register into the 16-bit timer down-counter. writing a zero has no effect. reading these bits will always return zero. module base + 0x0002 76543210 r0000 pce3 pce2 pce1 pce0 w reset 0 0 0 00000 figure 12-5. pit channel enable register (pitce) table 12-4. pitce field descriptions field description 3:0 pce[3:0] pit enable bits for timer channel 3:0 ?these bits enable the pit channels 3-0. if pce is cleared, the pit channel is disabled and the corresponding ?g bit in the pittf register is cleared. when pce is set, and if the pit module is enabled (pite = 1) the 16-bit timer counter is loaded with the start count value and starts down- counting. 0 the corresponding pit channel is disabled. 1 the corresponding pit channel is enabled.
periodic interrupt timer (s12pit24b4cv1) s12xs family reference manual, rev. 1.10 freescale semiconductor 355 12.3.0.4 pit multiplex register (pitmux) read: anytime write: anytime 12.3.0.5 pit interrupt enable register (pitinte) read: anytime write: anytime module base + 0x0003 76543210 r0000 pmux3 pmux2 pmux1 pmux0 w reset 0 0 0 00000 figure 12-6. pit multiplex register (pitmux) table 12-5. pitmux field descriptions field description 3:0 pmux[3:0] pit multiplex bits for timer channel 3:0 these bits select if the corresponding 16-bit timer is connected to micro time base 1 or 0. if pmux is modi?d, the corresponding 16-bit timer is switched to the other micro time base immediately. 0 the corresponding 16-bit timer counts with micro time base 0. 1 the corresponding 16-bit timer counts with micro time base 1. module base + 0x0004 76543210 r0000 pinte3 pinte2 pinte1 pinte0 w reset 0 0 0 00000 figure 12-7. pit interrupt enable register (pitinte) table 12-6. pitinte field descriptions field description 3:0 pinte[3:0] pit time-out interrupt enable bits for timer channel 3:0 ?these bits enable an interrupt service request whenever the time-out ?g ptf of the corresponding pit channel is set. when an interrupt is pending (ptf set) enabling the interrupt will immediately cause an interrupt. to avoid this, the corresponding ptf ?g has to be cleared ?st. 0 interrupt of the corresponding pit channel is disabled. 1 interrupt of the corresponding pit channel is enabled.
periodic interrupt timer (s12pit24b4cv1) s12xs family reference manual, rev. 1.10 356 freescale semiconductor 12.3.0.6 pit time-out flag register (pittf) read: anytime write: anytime (write to clear) 12.3.0.7 pit micro timer load register 0 to 1 (pitmtld0?) read: anytime write: anytime module base + 0x0005 76543210 r0000 ptf3 ptf2 ptf1 ptf0 w reset 0 0 0 00000 figure 12-8. pit time-out flag register (pittf) table 12-7. pittf field descriptions field description 3:0 ptf[3:0] pit time-out flag bits for timer channel 3:0 ?ptf is set when the corresponding 16-bit timer modulus down-counter and the selected 8-bit micro timer modulus down-counter have counted to zero. the ?g can be cleared by writing a one to the ?g bit. writing a zero has no effect. if ?g clearing by writing a one and ?g setting happen in the same bus clock cycle, the ?g remains set. the ?g bits are cleared if the pit module is disabled or if the corresponding timer channel is disabled. 0 time-out of the corresponding pit channel has not yet occurred. 1 time-out of the corresponding pit channel has occurred. module base + 0x0006 76543210 r pmtld7 pmtld6 pmtld5 pmtld4 pmtld3 pmtld2 pmtld1 pmtld0 w reset 0 0 0 00000 figure 12-9. pit micro timer load register 0 (pitmtld0) module base + 0x0007 76543210 r pmtld7 pmtld6 pmtld5 pmtld4 pmtld3 pmtld2 pmtld1 pmtld0 w reset 0 0 0 00000 figure 12-10. pit micro timer load register 1 (pitmtld1)
periodic interrupt timer (s12pit24b4cv1) s12xs family reference manual, rev. 1.10 freescale semiconductor 357 table 12-8. pitmtld0? field descriptions field description 7:0 pmtld[7:0] pit micro timer load bits 7:0 these bits set the 8-bit modulus down-counter load value of the micro timers. writing a new value into the pitmtld register will not restart the timer. when the micro timer has counted down to zero, the pmtld register value will be loaded. the pflmt bits in the pitcflmt register can be used to immediately update the count register with the new value if an immediate load is desired.
periodic interrupt timer (s12pit24b4cv1) s12xs family reference manual, rev. 1.10 358 freescale semiconductor 12.3.0.8 pit load register 0 to 3 (pitld0?) read: anytime write: anytime module base + 0x0008, 0x0009 15 14 13 12 11 10 9876543210 r pld15 pld14 pld13 pld12 pld11 pld10 pld9 pld8 pld7 pld6 pld5 pld4 pld3 pld2 pld1 pld0 w reset 000000 0000000000 figure 12-11. pit load register 0 (pitld0) module base + 0x000c, 0x000d 15 14 13 12 11 10 9876543210 r pld15 pld14 pld13 pld12 pld11 pld10 pld9 pld8 pld7 pld6 pld5 pld4 pld3 pld2 pld1 pld0 w reset 000000 0000000000 figure 12-12. pit load register 1 (pitld1) module base + 0x0010, 0x0011 15 14 13 12 11 10 9876543210 r pld15 pld14 pld13 pld12 pld11 pld10 pld9 pld8 pld7 pld6 pld5 pld4 pld3 pld2 pld1 pld0 w reset 000000 0000000000 figure 12-13. pit load register 2 (pitld2) module base + 0x0014, 0x0015 15 14 13 12 11 10 9876543210 r pld15 pld14 pld13 pld12 pld11 pld10 pld9 pld8 pld7 pld6 pld5 pld4 pld3 pld2 pld1 pld0 w reset 000000 0000000000 figure 12-14. pit load register 3 (pitld3) table 12-9. pitld0? field descriptions field description 15:0 pld[15:0] pit load bits 15:0 these bits set the 16-bit modulus down-counter load value. writing a new value into the pitld register must be a 16-bit access, to ensure data consistency. it will not restart the timer. when the timer has counted down to zero the ptf time-out ?g will be set and the register value will be loaded. the pflt bits in the pitflt register can be used to immediately update the count register with the new value if an immediate load is desired.
periodic interrupt timer (s12pit24b4cv1) s12xs family reference manual, rev. 1.10 freescale semiconductor 359 12.3.0.9 pit count register 0 to 3 (pitcnt0?) read: anytime write: has no meaning or effect module base + 0x000a, 0x000b 15 14 13 12 11 10 9876543210 r pcnt 15 pcnt 14 pcnt 13 pcnt 12 pcnt 11 pcnt 10 pcnt 9 pcnt 8 pcnt 7 pcnt 6 pcnt 5 pcnt 4 pcnt 3 pcnt 2 pcnt 1 pcnt 0 w reset 000000 0000000000 figure 12-15. pit count register 0 (pitcnt0) module base + 0x000e, 0x000f 15 14 13 12 11 10 9876543210 r pcnt 15 pcnt 14 pcnt 13 pcnt 12 pcnt 11 pcnt 10 pcnt 9 pcnt 8 pcnt 7 pcnt 6 pcnt 5 pcnt 4 pcnt 3 pcnt 2 pcnt 1 pcnt 0 w reset 000000 0000000000 figure 12-16. pit count register 1 (pitcnt1) module base + 0x0012, 0x0013 15 14 13 12 11 10 9876543210 r pcnt 15 pcnt 14 pcnt 13 pcnt 12 pcnt 11 pcnt 10 pcnt 9 pcnt 8 pcnt 7 pcnt 6 pcnt 5 pcnt 4 pcnt 3 pcnt 2 pcnt 1 pcnt 0 w reset 000000 0000000000 figure 12-17. pit count register 2 (pitcnt2) module base + 0x0016, 0x0017 15 14 13 12 11 10 9876543210 r pcnt 15 pcnt 14 pcnt 13 pcnt 12 pcnt 11 pcnt 10 pcnt 9 pcnt 8 pcnt 7 pcnt 6 pcnt 5 pcnt 4 pcnt 3 pcnt 2 pcnt 1 pcnt 0 w reset 000000 0000000000 figure 12-18. pit count register 3 (pitcnt3) table 12-10. pitcnt0? field descriptions field description 15:0 pcnt[15:0] pit count bits 15-0 ?these bits represent the current 16-bit modulus down-counter value. the read access for the count register must take place in one clock cycle as a 16-bit access.
periodic interrupt timer (s12pit24b4cv1) s12xs family reference manual, rev. 1.10 360 freescale semiconductor 12.4 functional description figure 12-19 shows a detailed block diagram of the pit module. the main parts of the pit are status, control and data registers, two 8-bit down-counters, four 16-bit down-counters and an interrupt/trigger interface. figure 12-19. pit24b4c detailed block diagram 12.4.1 timer as shown in figure 12-1 and figure 12-19 , the 24-bit timers are built in a two-stage architecture with four 16-bit modulus down-counters and two 8-bit modulus down-counters. the 16-bit timers are clocked with two selectable micro time bases which are generated with 8-bit modulus down-counters. each 16-bit timer is connected to micro time base 0 or 1 via the pmux[3:0] bit setting in the pit multiplex (pitmux) register. a timer channel is enabled if the module enable bit pite in the pit control and force load micro timer (pitcflmt) register is set and if the corresponding pce bit in the pit channel enable (pitce) register is set. two 8-bit modulus down-counters are used to generate two micro time bases. as soon as a micro time base is selected for an enabled timer channel, the corresponding micro timer modulus down-counter will load its start value as speci?d in the pitmtld0 or pitmtld1 register and will start down-counting. whenever the micro timer down-counter has counted to zero the pitmtld register is reloaded and the connected 16-bit modulus down-counters count one cycle. pitmld0 register 8-bit micro timer 0 pitcflmt register pitld0 register pitmld1 register 8-bit micro timer 1 pitmux register pitcnt0 register timer 0 pmux0 pflt0 4 4 pittf register pitinte register interrupt / hardware trigger 4 interrupt request 4 pitld1 register pitcnt1 register timer 1 [1] pflt1 pitld2 register pitcnt2 register timer 2 [2] pflt2 pitld3 register pitcnt3 register timer 3 pflt3 time-out 0 pflmt [1] [0] pmux trigger interface bus clock pit24b4c [3] time- out 3 time-out 1 pitflt register time- out 3
periodic interrupt timer (s12pit24b4cv1) s12xs family reference manual, rev. 1.10 freescale semiconductor 361 whenever a 16-bit timer counter and the connected 8-bit micro timer counter have counted to zero, the pitld register is reloaded and the corresponding time-out ?g ptf in the pit time-out ?g (pittf) register is set, as shown in figure 12-20 . the time-out period is a function of the timer load (pitld) and micro timer load (pitmtld) registers and the bus clock f bus : time-out period = (pitmtld + 1) * (pitld + 1) / f bus . for example, for a 40 mhz bus clock, the maximum time-out period equals: 256 * 65536 * 25 ns = 419.43 ms. the current 16-bit modulus down-counter value can be read via the pitcnt register. the micro timer down-counter values cannot be read. the 8-bit micro timers can individually be restarted by writing a one to the corresponding force load micro timer pflmt bits in the pit control and force load micro timer (pitcflmt) register. the 16-bit timers can individually be restarted by writing a one to the corresponding force load timer pflt bits in the pit forceload timer (pitflt) register. if desired, any group of timers and micro timers can be restarted at the same time by using one 16-bit write to the adjacent pitcflmt and pitflt registers with the relevant bits set, as shown in figure 12-20 . figure 12-20. pit trigger and flag signal timing 12.4.2 interrupt interface each time-out event can be used to trigger an interrupt service request. for each timer channel, an individual bit pinte in the pit interrupt enable (pitinte) register exists to enable this feature. if pinte bus clock 02 1 0 8-bit micro 2 1 0 2 1 0 2 1 2 1 0 pitcnt register 0001 0000 00 0001 0000 8-bit force load 2 1 0 2 1 0 ptf flag 1 pittrig 16-bit force load 0001 0000 0001 2 time-out period time-out period after restart timer counter note 1. the ptf ?g clearing depends on the software
periodic interrupt timer (s12pit24b4cv1) s12xs family reference manual, rev. 1.10 362 freescale semiconductor is set, an interrupt service is requested whenever the corresponding time-out ?g ptf in the pit time-out ?g (pittf) register is set. the ?g can be cleared by writing a one to the ?g bit. note be careful when resetting the pite, pinte or pitce bits in case of pending pit interrupt requests, to avoid spurious interrupt requests. 12.4.3 hardware trigger the pit module contains four hardware trigger signal lines pittrig[3:0], one for each timer channel. these signals can be connected on soc level to peripheral modules enabling e.g. periodic atd conversion (please refer to the soc guide for the mapping of pittrig[3:0] signals to peripheral modules). whenever a timer channel time-out is reached, the corresponding ptf ?g is set and the corresponding trigger signal pittrig triggers a rising edge. the trigger feature requires a minimum time-out period of two bus clock cycles because the trigger is asserted high for at least one bus clock cycle. for load register values pitld = 0x0001 and pitmtld = 0x0002 the ?g setting, trigger timing and a restart with force load is shown in figure 12-20 . 12.5 initialization 12.5.1 startup set the con?uration registers before the pite bit in the pitcflmt register is set. before pite is set, the con?uration registers can be written in arbitrary order. 12.5.2 shutdown when the pitce register bits, the pitinte register bits or the pite bit in the pitcflmt register are cleared, the corresponding pit interrupt ?gs are cleared. in case of a pending pit interrupt request, a spurious interrupt can be generated. two strategies, which avoid spurious interrupts, are recommended: 1. reset the pit interrupt ?gs only in an isr. when entering the isr, the i mask bit in the ccr is set automatically. the i mask bit must not be cleared before the pit interrupt ?gs are cleared. 2. after setting the i mask bit with the sei instruction, the pit interrupt ?gs can be cleared. then clear the i mask bit with the cli instruction to re-enable interrupts. 12.5.3 flag clearing a ?g is cleared by writing a one to the ?g bit. always use store or move instructions to write a one in certain bit positions. do not use the bset instructions. do not use any c-constructs that compile to bset instructions. ?set ?g_register, #mask?must not be used for ?g clearing because bset is a read- modify-write instruction which writes back the ?it-wise or?of the ?g_register and the mask into the ?g_register. bset would clear all ?g bits that were set, independent from the mask. for example, to clear ?g bit 0 use: movb #$01,pittf.
periodic interrupt timer (s12pit24b4cv1) s12xs family reference manual, rev. 1.10 freescale semiconductor 363 12.6 application information to get started quickly with the pit24b8c module this section provides a small code example how to use the block. please note that the example provided is only one speci? case out of the possible con?urations and implementations. functionality: generate an pit interrupt on channel 0 every 500 pit clock cycles. org codestart ; place the program into speci? ; range (to be selected) lds ramend ; load stack pointer to top of ram movw #ch0_isr,vec_pit_ch0 ; change value of channel 0 isr adr ; ******************** start pit initialization ******************************************************* clr pitcflmt ; disable pit movb #$01,pitce ; enable timer channel 0 clr pitmux ; ch0 connected to micro timer 0 movb #$63,pitmtld0 ; micro time base 0 equals 100 clock cycles movw #$0004,pitld0 ; time base 0 eq. 5 micro time bases 0 =5*100 = 500 movb #$01,pitinte ; enable interupt channel 0 movb #$80,pitcflmt ; enable pit cli ; clear interupt disable mask bit ;******************** main program ************************************************************* main: bra * ; loop until interrupt ;******************** channel 0 interupt routine *************************************************** ch0_isr: ldaa pittf ; 8 bit read of pit time out ?gs movb #$01,pittf ; clear pit channel 0 time out ?g rti ; return to main
periodic interrupt timer (s12pit24b4cv1) s12xs family reference manual, rev. 1.10 364 freescale semiconductor
s12xs family reference manual, rev. 1.10 freescale semiconductor 365 chapter 13 pulse-width modulator (s12pwm8b8cv1) 13.1 introduction the pwm de?ition is based on the hc12 pwm de?itions. it contains the basic features from the hc11 with some of the enhancements incorporated on the hc12: center aligned output mode and four available clock sources.the pwm module has eight channels with independent control of left and center aligned outputs on each channel. each of the eight channels has a programmable period and duty cycle as well as a dedicated counter. a ?xible clock select scheme allows a total of four different clock sources to be used with the counters. each of the modulators can create independent continuous waveforms with software-selectable duty rates from 0% to 100%. the pwm outputs can be programmed as left aligned outputs or center aligned outputs. 13.1.1 features the pwm block includes these distinctive features: eight independent pwm channels with programmable period and duty cycle dedicated counter for each pwm channel programmable pwm enable/disable for each channel software selection of pwm duty pulse polarity for each channel period and duty cycle are double buffered. change takes effect when the end of the effective period is reached (pwm counter reaches zero) or when the channel is disabled. programmable center or left aligned outputs on individual channels eight 8-bit channel or four 16-bit channel pwm resolution four clock sources (a, b, sa, and sb) provide for a wide range of frequencies programmable clock select logic emergency shutdown version number revision date effective date author description of changes 01.17 08-01-2004 added clari?ation of pwmif operation in stop and wait mode. added notes on minimum pulse width of emergency shutdown signal.
pulse-width modulator (s12pwm8b8cv1) s12xs family reference manual, rev. 1.10 366 freescale semiconductor 13.1.2 modes of operation there is a software programmable option for low power consumption in wait mode that disables the input clock to the prescaler. in freeze mode there is a software programmable option to disable the input clock to the prescaler. this is useful for emulation. 13.1.3 block diagram figure 13-1 shows the block diagram for the 8-bit 8-channel pwm block. figure 13-1. pwm block diagram 13.2 external signal description the pwm module has a total of 8 external pins. period and duty counter channel 6 clock select pwm clock period and duty counter channel 5 period and duty counter channel 4 period and duty counter channel 3 period and duty counter channel 2 period and duty counter channel 1 alignment polarity control pwm8b8c pwm6 pwm5 pwm4 pwm3 pwm2 pwm1 enable pwm channels period and duty counter channel 7 period and duty counter channel 0 pwm0 pwm7 bus clock
pulse-width modulator (s12pwm8b8cv1) s12xs family reference manual, rev. 1.10 freescale semiconductor 367 13.2.1 pwm7 ?pwm channel 7 this pin serves as waveform output of pwm channel 7 and as an input for the emergency shutdown feature. 13.2.2 pwm6 ?pwm channel 6 this pin serves as waveform output of pwm channel 6. 13.2.3 pwm5 ?pwm channel 5 this pin serves as waveform output of pwm channel 5. 13.2.4 pwm4 ?pwm channel 4 this pin serves as waveform output of pwm channel 4. 13.2.5 pwm3 ?pwm channel 3 this pin serves as waveform output of pwm channel 3. 13.2.6 pwm3 ?pwm channel 2 this pin serves as waveform output of pwm channel 2. 13.2.7 pwm3 ?pwm channel 1 this pin serves as waveform output of pwm channel 1. 13.2.8 pwm3 ?pwm channel 0 this pin serves as waveform output of pwm channel 0. 13.3 memory map and register de?ition this section describes in detail all the registers and register bits in the pwm module. the special-purpose registers and register bit functions that are not normally available to device end users, such as factory test control registers and reserved registers, are clearly identi?d by means of shading the appropriate portions of address maps and register diagrams. notes explaining the reasons for restricting access to the registers and functions are also explained in the individual register descriptions. 13.3.1 module memory map this section describes the content of the registers in the pwm module. the base address of the pwm module is determined at the mcu level when the mcu is de?ed. the register decode map is ?ed and begins at the ?st address of the module address offset. the ?ure below shows the registers associated
pulse-width modulator (s12pwm8b8cv1) s12xs family reference manual, rev. 1.10 368 freescale semiconductor with the pwm and their relative offset from the base address. the register detail description follows the order they appear in the register map. reserved bits within a register will always read as 0 and the write will be unimplemented. unimplemented functions are indicated by shading the bit. . note register address = base address + address offset, where the base address is de?ed at the mcu level and the address offset is de?ed at the module level. 13.3.2 register descriptions this section describes in detail all the registers and register bits in the pwm module. register name bit 7 6 5 4 3 2 1 bit 0 0x0000 pwme r pwme7 pwme6 pwme5 pwme4 pwme3 pwme2 pwme1 pwme0 w 0x0001 pwmpol r ppol7 ppol6 ppol5 ppol4 ppol3 ppol2 ppol1 ppol0 w 0x0002 pwmclk r pclk7 pclkl6 pclk5 pclk4 pclk3 pclk2 pclk1 pclk0 w 0x0003 pwmprclk r0 pckb2 pckb1 pckb0 0 pcka2 pcka1 pcka0 w 0x0004 pwmcae r cae7 cae6 cae5 cae4 cae3 cae2 cae1 cae0 w 0x0005 pwmctl r con67 con45 con23 con01 pswai pfrz 00 w 0x0006 pwmtst 1 r00 0 00000 w 0x0007 pwmprsc 1 r00 0 00000 w 0x0008 pwmscla r bit 7 6 5 4 3 2 1 bit 0 w 0x0009 pwmsclb r bit 7 6 5 4 3 2 1 bit 0 w = unimplemented or reserved figure 13-2. pwm register summary (sheet 1 of 3)
pulse-width modulator (s12pwm8b8cv1) s12xs family reference manual, rev. 1.10 freescale semiconductor 369 0x000a pwmscnta 1 r00 0 00000 w 0x000b pwmscntb 1 r00 0 00000 w 0x000c pwmcnt0 r bit 7 6 5 4 3 2 1 bit 0 w00 0 00000 0x000d pwmcnt1 r bit 7 6 5 4 3 2 1 bit 0 w00 0 00000 0x000e pwmcnt2 r bit 7 6 5 4 3 2 1 bit 0 w00 0 00000 0x000f pwmcnt3 r bit 7 6 5 4 3 2 1 bit 0 w00 0 00000 0x0010 pwmcnt4 r bit 7 6 5 4 3 2 1 bit 0 w00 0 00000 0x0011 pwmcnt5 r bit 7 6 5 4 3 2 1 bit 0 w00 0 00000 0x0012 pwmcnt6 r bit 7 6 5 4 3 2 1 bit 0 w00 0 00000 0x0013 pwmcnt7 r bit 7 6 5 4 3 2 1 bit 0 w00 0 00000 0x0014 pwmper0 r bit 7 6 5 4 3 2 1 bit 0 w 0x0015 pwmper1 r bit 7 6 5 4 3 2 1 bit 0 w 0x0016 pwmper2 r bit 7 6 5 4 3 2 1 bit 0 w 0x0017 pwmper3 r bit 7 6 5 4 3 2 1 bit 0 w 0x0018 pwmper4 r bit 7 6 5 4 3 2 1 bit 0 w register name bit 7 6 5 4 3 2 1 bit 0 = unimplemented or reserved figure 13-2. pwm register summary (sheet 2 of 3)
pulse-width modulator (s12pwm8b8cv1) s12xs family reference manual, rev. 1.10 370 freescale semiconductor 13.3.2.1 pwm enable register (pwme) each pwm channel has an enable bit (pwmex) to start its waveform output. when any of the pwmex bits are set (pwmex = 1), the associated pwm output is enabled immediately. however, the actual pwm waveform is not available on the associated pwm output until its clock source begins its next cycle due to the synchronization of pwmex and the clock source. 0x0019 pwmper5 r bit 7 6 5 4 3 2 1 bit 0 w 0x001a pwmper6 r bit 7 6 5 4 3 2 1 bit 0 w 0x001b pwmper7 r bit 7 6 5 4 3 2 1 bit 0 w 0x001c pwmdty0 r bit 7 6 5 4 3 2 1 bit 0 w 0x001d pwmdty1 r bit 7 6 5 4 3 2 1 bit 0 w 0x001e pwmdty2 r bit 7 6 5 4 3 2 1 bit 0 w 0x001f pwmdty3 r bit 7 6 5 4 3 2 1 bit 0 w 0x0010 pwmdty4 r bit 7 6 5 4 3 2 1 bit 0 w 0x0021 pwmdty5 r bit 7 6 5 4 3 2 1 bit 0 w 0x0022 pwmdty6 r bit 7 6 5 4 3 2 1 bit 0 w 0x0023 pwmdty7 r bit 7 6 5 4 3 2 1 bit 0 w 0x0024 pwmsdn r pwmif pwmie 0 pwmlvl 0 pwm7in pwm7inl pwm7ena w pwmrstrt 1 intended for factory test purposes only. register name bit 7 6 5 4 3 2 1 bit 0 = unimplemented or reserved figure 13-2. pwm register summary (sheet 3 of 3)
pulse-width modulator (s12pwm8b8cv1) s12xs family reference manual, rev. 1.10 freescale semiconductor 371 note the ?st pwm cycle after enabling the channel can be irregular. an exception to this is when channels are concatenated. once concatenated mode is enabled (conxx bits set in pwmctl register), enabling/disabling the corresponding 16-bit pwm channel is controlled by the low order pwmex bit.in this case, the high order bytes pwmex bits have no effect and their corresponding pwm output lines are disabled. while in run mode, if all eight pwm channels are disabled (pwme7? = 0), the prescaler counter shuts off for power savings. read: anytime write: anytime module base + 0x0000 76543210 r pwme7 pwme6 pwme5 pwme4 pwme3 pwme2 pwme1 pwme0 w reset 0 0 0 00000 figure 13-3. pwm enable register (pwme) table 13-1. pwme field descriptions field description 7 pwme7 pulse width channel 7 enable 0 pulse width channel 7 is disabled. 1 pulse width channel 7 is enabled. the pulse modulated signal becomes available at pwm output bit 7 when its clock source begins its next cycle. 6 pwme6 pulse width channel 6 enable 0 pulse width channel 6 is disabled. 1 pulse width channel 6 is enabled. the pulse modulated signal becomes available at pwm output bit6 when its clock source begins its next cycle. if con67=1, then bit has no effect and pwm output line 6 is disabled. 5 pwme5 pulse width channel 5 enable 0 pulse width channel 5 is disabled. 1 pulse width channel 5 is enabled. the pulse modulated signal becomes available at pwm output bit 5 when its clock source begins its next cycle. 4 pwme4 pulse width channel 4 enable 0 pulse width channel 4 is disabled. 1 pulse width channel 4 is enabled. the pulse modulated signal becomes available at pwm, output bit 4 when its clock source begins its next cycle. if con45 = 1, then bit has no effect and pwm output bit4 is disabled. 3 pwme3 pulse width channel 3 enable 0 pulse width channel 3 is disabled. 1 pulse width channel 3 is enabled. the pulse modulated signal becomes available at pwm, output bit 3 when its clock source begins its next cycle. 2 pwme2 pulse width channel 2 enable 0 pulse width channel 2 is disabled. 1 pulse width channel 2 is enabled. the pulse modulated signal becomes available at pwm, output bit 2 when its clock source begins its next cycle. if con23 = 1, then bit has no effect and pwm output bit2 is disabled.
pulse-width modulator (s12pwm8b8cv1) s12xs family reference manual, rev. 1.10 372 freescale semiconductor 13.3.2.2 pwm polarity register (pwmpol) the starting polarity of each pwm channel waveform is determined by the associated ppolx bit in the pwmpol register. if the polarity bit is one, the pwm channel output is high at the beginning of the cycle and then goes low when the duty count is reached. conversely, if the polarity bit is zero, the output starts low and then goes high when the duty count is reached. read: anytime write: anytime note ppolx register bits can be written anytime. if the polarity is changed while a pwm signal is being generated, a truncated or stretched pulse can occur during the transition 13.3.2.3 pwm clock select register (pwmclk) each pwm channel has a choice of two clocks to use as the clock source for that channel as described below. 1 pwme1 pulse width channel 1 enable 0 pulse width channel 1 is disabled. 1 pulse width channel 1 is enabled. the pulse modulated signal becomes available at pwm, output bit 1 when its clock source begins its next cycle. 0 pwme0 pulse width channel 0 enable 0 pulse width channel 0 is disabled. 1 pulse width channel 0 is enabled. the pulse modulated signal becomes available at pwm, output bit 0 when its clock source begins its next cycle. if con01 = 1, then bit has no effect and pwm output line0 is disabled. module base + 0x0001 76543210 r ppol7 ppol6 ppol5 ppol4 ppol3 ppol2 ppol1 ppol0 w reset 0 0 0 00000 figure 13-4. pwm polarity register (pwmpol) table 13-2. pwmpol field descriptions field description 7? ppol[7:0] p ulse width channel 7? polarity bits 0 pwm channel 7? outputs are low at the beginning of the period, then go high when the duty count is reached. 1 pwm channel 7? outputs are high at the beginning of the period, then go low when the duty count is reached. table 13-1. pwme field descriptions (continued) field description
pulse-width modulator (s12pwm8b8cv1) s12xs family reference manual, rev. 1.10 freescale semiconductor 373 read: anytime write: anytime note register bits pclk0 to pclk7 can be written anytime. if a clock select is changed while a pwm signal is being generated, a truncated or stretched pulse can occur during the transition. 13.3.2.4 pwm prescale clock select register (pwmprclk) this register selects the prescale clock source for clocks a and b independently. module base + 0x0002 76543210 r pclk7 pclkl6 pclk5 pclk4 pclk3 pclk2 pclk1 pclk0 w reset 0 0 0 00000 figure 13-5. pwm clock select register (pwmclk) table 13-3. pwmclk field descriptions field description 7 pclk7 pulse width channel 7 clock select 0 clock b is the clock source for pwm channel 7. 1 clock sb is the clock source for pwm channel 7. 6 pclk6 pulse width channel 6 clock select 0 clock b is the clock source for pwm channel 6. 1 clock sb is the clock source for pwm channel 6. 5 pclk5 pulse width channel 5 clock select 0 clock a is the clock source for pwm channel 5. 1 clock sa is the clock source for pwm channel 5. 4 pclk4 pulse width channel 4 clock select 0 clock a is the clock source for pwm channel 4. 1 clock sa is the clock source for pwm channel 4. 3 pclk3 pulse width channel 3 clock select 0 clock b is the clock source for pwm channel 3. 1 clock sb is the clock source for pwm channel 3. 2 pclk2 pulse width channel 2 clock select 0 clock b is the clock source for pwm channel 2. 1 clock sb is the clock source for pwm channel 2. 1 pclk1 pulse width channel 1 clock select 0 clock a is the clock source for pwm channel 1. 1 clock sa is the clock source for pwm channel 1. 0 pclk0 pulse width channel 0 clock select 0 clock a is the clock source for pwm channel 0. 1 clock sa is the clock source for pwm channel 0.
pulse-width modulator (s12pwm8b8cv1) s12xs family reference manual, rev. 1.10 374 freescale semiconductor read: anytime write: anytime note pckb2? and pcka2? register bits can be written anytime. if the clock pre-scale is changed while a pwm signal is being generated, a truncated or stretched pulse can occur during the transition. s module base + 0x0003 76543210 r0 pckb2 pckb1 pckb0 0 pcka2 pcka1 pcka0 w reset 0 0 0 00000 = unimplemented or reserved figure 13-6. pwm prescale clock select register (pwmprclk) table 13-4. pwmprclk field descriptions field description 6? pckb[2:0] prescaler select for clock b clock b is one of two clock sources which can be used for channels 2, 3, 6, or 7. these three bits determine the rate of clock b, as shown in table 13-5 . 2? pcka[2:0] prescaler select for clock a clock a is one of two clock sources which can be used for channels 0, 1, 4 or 5. these three bits determine the rate of clock a, as shown in table 13-6 . table 13-5. clock b prescaler selects pckb2 pckb1 pckb0 value of clock b 0 0 0 bus clock 0 0 1 bus clock / 2 0 1 0 bus clock / 4 0 1 1 bus clock / 8 1 0 0 bus clock / 16 1 0 1 bus clock / 32 1 1 0 bus clock / 64 1 1 1 bus clock / 128 table 13-6. clock a prescaler selects pcka2 pcka1 pcka0 value of clock a 0 0 0 bus clock 0 0 1 bus clock / 2 0 1 0 bus clock / 4 0 1 1 bus clock / 8 1 0 0 bus clock / 16 1 0 1 bus clock / 32 1 1 0 bus clock / 64 1 1 1 bus clock / 128
pulse-width modulator (s12pwm8b8cv1) s12xs family reference manual, rev. 1.10 freescale semiconductor 375 13.3.2.5 pwm center align enable register (pwmcae) the pwmcae register contains eight control bits for the selection of center aligned outputs or left aligned outputs for each pwm channel. if the caex bit is set to a one, the corresponding pwm output will be center aligned. if the caex bit is cleared, the corresponding pwm output will be left aligned. see section 13.4.2.5, ?eft aligned outputs and section 13.4.2.6, ?enter aligned outputs for a more detailed description of the pwm output modes. read: anytime write: anytime note write these bits only when the corresponding channel is disabled. 13.3.2.6 pwm control register (pwmctl) the pwmctl register provides for various control of the pwm module. read: anytime write: anytime there are three control bits for concatenation, each of which is used to concatenate a pair of pwm channels into one 16-bit channel. when channels 6 and 7are concatenated, channel 6 registers become the high order bytes of the double byte channel. when channels 4 and 5 are concatenated, channel 4 registers become the high order bytes of the double byte channel. when channels 2 and 3 are concatenated, channel module base + 0x0004 76543210 r cae7 cae6 cae5 cae4 cae3 cae2 cae1 cae0 w reset 0 0 0 00000 figure 13-7. pwm center align enable register (pwmcae) table 13-7. pwmcae field descriptions field description 7? cae[7:0] center aligned output modes on channels 7? 0 channels 7? operate in left aligned output mode. 1 channels 7? operate in center aligned output mode. module base + 0x0005 76543210 r con67 con45 con23 con01 pswai pfrz 00 w reset 0 0 0 00000 = unimplemented or reserved figure 13-8. pwm control register (pwmctl)
pulse-width modulator (s12pwm8b8cv1) s12xs family reference manual, rev. 1.10 376 freescale semiconductor 2 registers become the high order bytes of the double byte channel. when channels 0 and 1 are concatenated, channel 0 registers become the high order bytes of the double byte channel. see section 13.4.2.7, ?wm 16-bit functions for a more detailed description of the concatenation pwm function. note change these bits only when both corresponding channels are disabled. table 13-8. pwmctl field descriptions field description 7 con67 concatenate channels 6 and 7 0 channels 6 and 7 are separate 8-bit pwms. 1 channels 6 and 7 are concatenated to create one 16-bit pwm channel. channel 6 becomes the high order byte and channel 7 becomes the low order byte. channel 7 output pin is used as the output for this 16-bit pwm (bit 7 of port pwmp). channel 7 clock select control-bit determines the clock source, channel 7 polarity bit determines the polarity, channel 7 enable bit enables the output and channel 7 center aligned enable bit determines the output mode. 6 con45 concatenate channels 4 and 5 0 channels 4 and 5 are separate 8-bit pwms. 1 channels 4 and 5 are concatenated to create one 16-bit pwm channel. channel 4 becomes the high order byte and channel 5 becomes the low order byte. channel 5 output pin is used as the output for this 16-bit pwm (bit 5 of port pwmp). channel 5 clock select control-bit determines the clock source, channel 5 polarity bit determines the polarity, channel 5 enable bit enables the output and channel 5 center aligned enable bit determines the output mode. 5 con23 concatenate channels 2 and 3 0 channels 2 and 3 are separate 8-bit pwms. 1 channels 2 and 3 are concatenated to create one 16-bit pwm channel. channel 2 becomes the high order byte and channel 3 becomes the low order byte. channel 3 output pin is used as the output for this 16-bit pwm (bit 3 of port pwmp). channel 3 clock select control-bit determines the clock source, channel 3 polarity bit determines the polarity, channel 3 enable bit enables the output and channel 3 center aligned enable bit determines the output mode. 4 con01 concatenate channels 0 and 1 0 channels 0 and 1 are separate 8-bit pwms. 1 channels 0 and 1 are concatenated to create one 16-bit pwm channel. channel 0 becomes the high order byte and channel 1 becomes the low order byte. channel 1 output pin is used as the output for this 16-bit pwm (bit 1 of port pwmp). channel 1 clock select control-bit determines the clock source, channel 1 polarity bit determines the polarity, channel 1 enable bit enables the output and channel 1 center aligned enable bit determines the output mode. 3 pswai pwm stops in wait mode enabling this bit allows for lower power consumption in wait mode by disabling the input clock to the prescaler. 0 allow the clock to the prescaler to continue while in wait mode. 1 stop the input clock to the prescaler whenever the mcu is in wait mode. 2 pfrez pwm counters stop in freeze mode ?in freeze mode, there is an option to disable the input clock to the prescaler by setting the pfrz bit in the pwmctl register. if this bit is set, whenever the mcu is in freeze mode, the input clock to the prescaler is disabled. this feature is useful during emulation as it allows the pwm function to be suspended. in this way, the counters of the pwm can be stopped while in freeze mode so that once normal program ow is continued, the counters are re-enabled to simulate real-time operations. since the registers can still be accessed in this mode, to re-enable the prescaler clock, either disable the pfrz bit or exit freeze mode. 0 allow pwm to continue while in freeze mode. 1 disable pwm input clock to the prescaler whenever the part is in freeze mode. this is useful for emulation.
pulse-width modulator (s12pwm8b8cv1) s12xs family reference manual, rev. 1.10 freescale semiconductor 377 13.3.2.7 reserved register (pwmtst) this register is reserved for factory testing of the pwm module and is not available in normal modes. read: always read $00 in normal modes write: unimplemented in normal modes note writing to this register when in special modes can alter the pwm functionality. 13.3.2.8 reserved register (pwmprsc) this register is reserved for factory testing of the pwm module and is not available in normal modes. read: always read $00 in normal modes write: unimplemented in normal modes note writing to this register when in special modes can alter the pwm functionality. 13.3.2.9 pwm scale a register (pwmscla) pwmscla is the programmable scale value used in scaling clock a to generate clock sa. clock sa is generated by taking clock a, dividing it by the value in the pwmscla register and dividing that by two. clock sa = clock a / (2 * pwmscla) module base + 0x0006 76543210 r00000000 w reset 0 0 0 00000 = unimplemented or reserved figure 13-9. reserved register (pwmtst) module base + 0x0007 76543210 r00000000 w reset 0 0 0 00000 = unimplemented or reserved figure 13-10. reserved register (pwmprsc)
pulse-width modulator (s12pwm8b8cv1) s12xs family reference manual, rev. 1.10 378 freescale semiconductor note when pwmscla = $00, pwmscla value is considered a full scale value of 256. clock a is thus divided by 512. any value written to this register will cause the scale counter to load the new scale value (pwmscla). read: anytime write: anytime (causes the scale counter to load the pwmscla value) 13.3.2.10 pwm scale b register (pwmsclb) pwmsclb is the programmable scale value used in scaling clock b to generate clock sb. clock sb is generated by taking clock b, dividing it by the value in the pwmsclb register and dividing that by two. clock sb = clock b / (2 * pwmsclb) note when pwmsclb = $00, pwmsclb value is considered a full scale value of 256. clock b is thus divided by 512. any value written to this register will cause the scale counter to load the new scale value (pwmsclb). read: anytime write: anytime (causes the scale counter to load the pwmsclb value). 13.3.2.11 reserved registers (pwmscntx) the registers pwmscnta and pwmscntb are reserved for factory testing of the pwm module and are not available in normal modes. module base + 0x0008 76543210 r bit 7 6 5 4 3 2 1 bit 0 w reset 0 0 0 00000 figure 13-11. pwm scale a register (pwmscla) module base + 0x0009 76543210 r bit 7 6 5 4 3 2 1 bit 0 w reset 0 0 0 00000 figure 13-12. pwm scale b register (pwmsclb)
pulse-width modulator (s12pwm8b8cv1) s12xs family reference manual, rev. 1.10 freescale semiconductor 379 read: always read $00 in normal modes write: unimplemented in normal modes note writing to these registers when in special modes can alter the pwm functionality. 13.3.2.12 pwm channel counter registers (pwmcntx) each channel has a dedicated 8-bit up/down counter which runs at the rate of the selected clock source. the counter can be read at any time without affecting the count or the operation of the pwm channel. in left aligned output mode, the counter counts from 0 to the value in the period register - 1. in center aligned output mode, the counter counts from 0 up to the value in the period register and then back down to 0. any value written to the counter causes the counter to reset to $00, the counter direction to be set to up, the immediate load of both duty and period registers with values from the buffers, and the output to change according to the polarity bit. the counter is also cleared at the end of the effective period (see section 13.4.2.5, ?eft aligned outputs and section 13.4.2.6, ?enter aligned outputs for more details). when the channel is disabled (pwmex = 0), the pwmcntx register does not count. when a channel becomes enabled (pwmex = 1), the associated pwm counter starts at the count in the pwmcntx register. for more detailed information on the operation of the counters, see section 13.4.2.4, ?wm timer counters . in concatenated mode, writes to the 16-bit counter by using a 16-bit access or writes to either the low or high order byte of the counter will reset the 16-bit counter. reads of the 16-bit counter must be made by 16-bit access to maintain data coherency. note writing to the counter while the channel is enabled can cause an irregular pwm cycle to occur. read: anytime module base + 0x000a, 0x000b 76543210 r00000000 w reset 0 0 0 00000 = unimplemented or reserved figure 13-13. reserved registers (pwmscntx) module base + 0x000c = pwmcnt0, 0x000d = pwmcnt1, 0x000e = pwmcnt2, 0x000f = pwmcnt3 module base + 0x0010 = pwmcnt4, 0x0011 = pwmcnt5, 0x0012 = pwmcnt6, 0x0013 = pwmcnt7 76543210 r bit 7 6 5 4 3 2 1 bit 0 w00000000 reset 0 0 0 00000 figure 13-14. pwm channel counter registers (pwmcntx)
pulse-width modulator (s12pwm8b8cv1) s12xs family reference manual, rev. 1.10 380 freescale semiconductor write: anytime (any value written causes pwm counter to be reset to $00). 13.3.2.13 pwm channel period registers (pwmperx) there is a dedicated period register for each channel. the value in this register determines the period of the associated pwm channel. the period registers for each channel are double buffered so that if they change while the channel is enabled, the change will not take effect until one of the following occurs: the effective period ends the counter is written (counter resets to $00) the channel is disabled in this way, the output of the pwm will always be either the old waveform or the new waveform, not some variation in between. if the channel is not enabled, then writes to the period register will go directly to the latches as well as the buffer. note reads of this register return the most recent value written. reads do not necessarily return the value of the currently active period due to the double buffering scheme. see section 13.4.2.3, ?wm period and duty for more information. to calculate the output period, take the selected clock source period for the channel of interest (a, b, sa, or sb) and multiply it by the value in the period register for that channel: left aligned output (caex = 0) pwmx period = channel clock period * pwmperx center aligned output (caex = 1) pwmx period = channel clock period * (2 * pwmperx) for boundary case programming values, please refer to section 13.4.2.8, ?wm boundary cases . read: anytime write: anytime module base + 0x0014 = pwmper0, 0x0015 = pwmper1, 0x0016 = pwmper2, 0x0017 = pwmper3 module base + 0x0018 = pwmper4, 0x0019 = pwmper5, 0x001a = pwmper6, 0x001b = pwmper7 76543210 r bit 7 6 5 4 3 2 1 bit 0 w reset 1 1 1 11111 figure 13-15. pwm channel period registers (pwmperx)
pulse-width modulator (s12pwm8b8cv1) s12xs family reference manual, rev. 1.10 freescale semiconductor 381 13.3.2.14 pwm channel duty registers (pwmdtyx) there is a dedicated duty register for each channel. the value in this register determines the duty of the associated pwm channel. the duty value is compared to the counter and if it is equal to the counter value a match occurs and the output changes state. the duty registers for each channel are double buffered so that if they change while the channel is enabled, the change will not take effect until one of the following occurs: the effective period ends the counter is written (counter resets to $00) the channel is disabled in this way, the output of the pwm will always be either the old duty waveform or the new duty waveform, not some variation in between. if the channel is not enabled, then writes to the duty register will go directly to the latches as well as the buffer. note reads of this register return the most recent value written. reads do not necessarily return the value of the currently active duty due to the double buffering scheme. see section 13.4.2.3, ?wm period and duty for more information. note depending on the polarity bit, the duty registers will contain the count of either the high time or the low time. if the polarity bit is one, the output starts high and then goes low when the duty count is reached, so the duty registers contain a count of the high time. if the polarity bit is zero, the output starts low and then goes high when the duty count is reached, so the duty registers contain a count of the low time. to calculate the output duty cycle (high time as a% of period) for a particular channel: polarity = 0 (ppol x =0) duty cycle = [(pwmperx-pwmdtyx)/pwmperx] * 100% polarity = 1 (ppolx = 1) duty cycle = [pwmdtyx / pwmperx] * 100% for boundary case programming values, please refer to section 13.4.2.8, ?wm boundary cases . read: anytime module base + 0x001c = pwmdty0, 0x001d = pwmdty1, 0x001e = pwmdty2, 0x001f = pwmdty3 module base + 0x0020 = pwmdty4, 0x0021 = pwmdty5, 0x0022 = pwmdty6, 0x0023 = pwmdty7 76543210 r bit 7 6 5 4 3 2 1 bit 0 w reset 1 1 1 11111 figure 13-16. pwm channel duty registers (pwmdtyx)
pulse-width modulator (s12pwm8b8cv1) s12xs family reference manual, rev. 1.10 382 freescale semiconductor write: anytime 13.3.2.15 pwm shutdown register (pwmsdn) the pwmsdn register provides for the shutdown functionality of the pwm module in the emergency cases. for proper operation, channel 7 must be driven to the active level for a minimum of two bus clocks. read: anytime write: anytime module base + 0x0024 76543210 r pwmif pwmie 0 pwmlvl 0 pwm7in pwm7inl pwm7ena w pwmrstrt reset 0 0 0 00000 = unimplemented or reserved figure 13-17. pwm shutdown register (pwmsdn) table 13-9. pwmsdn field descriptions field description 7 pwmif pwm interrupt flag ?any change from passive to asserted (active) state or from active to passive state will be ?gged by setting the pwmif ?g = 1. the ?g is cleared by writing a logic 1 to it. writing a 0 has no effect. 0 no change on pwm7in input. 1 change on pwm7in input 6 pwmie pwm interrupt enable ?if interrupt is enabled an interrupt to the cpu is asserted. 0 pwm interrupt is disabled. 1 pwm interrupt is enabled. 5 pwmrstrt pwm restart the pwm can only be restarted if the pwm channel input 7 is de-asserted. after writing a logic 1 to the pwmrstrt bit (trigger event) the pwm channels start running after the corresponding counter passes next ?ounter == 0?phase. also, if the pwm7ena bit is reset to 0, the pwm do not start before the counter passes $00. the bit is always read as ?? 4 pwmlvl pwm shutdown output level if active level as de?ed by the pwm7in input, gets asserted all enabled pwm channels are immediately driven to the level de?ed by pwmlvl. 0 pwm outputs are forced to 0 1 outputs are forced to 1. 2 pwm7in pwm channel 7 input status ?this re?cts the current status of the pwm7 pin. 1 pwm7inl pwm shutdown active input level for channel 7 ?if the emergency shutdown feature is enabled (pwm7ena = 1), this bit determines the active level of the pwm7channel. 0 active level is low 1 active level is high 0 pwm7ena pwm emergency shutdown enable if this bit is logic 1, the pin associated with channel 7 is forced to input and the emergency shutdown feature is enabled. all the other bits in this register are meaningful only if pwm7ena = 1. 0 pwm emergency feature disabled. 1 pwm emergency feature is enabled.
pulse-width modulator (s12pwm8b8cv1) s12xs family reference manual, rev. 1.10 freescale semiconductor 383 13.4 functional description 13.4.1 pwm clock select there are four available clocks: clock a, clock b, clock sa (scaled a), and clock sb (scaled b). these four clocks are based on the bus clock. clock a and b can be software selected to be 1, 1/2, 1/4, 1/8,..., 1/64, 1/128 times the bus clock. clock sa uses clock a as an input and divides it further with a reloadable counter. similarly, clock sb uses clock b as an input and divides it further with a reloadable counter. the rates available for clock sa are software selectable to be clock a divided by 2, 4, 6, 8,..., or 512 in increments of divide by 2. similar rates are available for clock sb. each pwm channel has the capability of selecting one of two clocks, either the pre-scaled clock (clock a or b) or the scaled clock (clock sa or sb). the block diagram in figure 13-18 shows the four different clocks and how the scaled clocks are created. 13.4.1.1 prescale the input clock to the pwm prescaler is the bus clock. it can be disabled whenever the part is in freeze mode by setting the pfrz bit in the pwmctl register. if this bit is set, whenever the mcu is in freeze mode (freeze mode signal active) the input clock to the prescaler is disabled. this is useful for emulation in order to freeze the pwm. the input clock can also be disabled when all eight pwm channels are disabled (pwme7-0 = 0). this is useful for reducing power by disabling the prescale counter. clock a and clock b are scaled values of the input clock. the value is software selectable for both clock a and clock b and has options of 1, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, or 1/128 times the bus clock. the value selected for clock a is determined by the pcka2, pcka1, pcka0 bits in the pwmprclk register. the value selected for clock b is determined by the pckb2, pckb1, pckb0 bits also in the pwmprclk register. 13.4.1.2 clock scale the scaled a clock uses clock a as an input and divides it further with a user programmable value and then divides this by 2. the scaled b clock uses clock b as an input and divides it further with a user programmable value and then divides this by 2. the rates available for clock sa are software selectable to be clock a divided by 2, 4, 6, 8,..., or 512 in increments of divide by 2. similar rates are available for clock sb.
pulse-width modulator (s12pwm8b8cv1) s12xs family reference manual, rev. 1.10 384 freescale semiconductor figure 13-18. pwm clock select block diagram 128 248163264 pckb2 pckb1 pckb0 m u x clock a clock b clock sa clock a/2, a/4, a/6,....a/512 prescale scale divide by pfrz freeze mode signal bus clock clock select m u x pclk0 clock to pwm ch 0 m u x pclk2 clock to pwm ch 2 m u x pclk1 clock to pwm ch 1 m u x pclk4 clock to pwm ch 4 m u x pclk5 clock to pwm ch 5 m u x pclk6 clock to pwm ch 6 m u x pclk7 clock to pwm ch 7 m u x pclk3 clock to pwm ch 3 load div 2 pwmsclb clock sb clock b/2, b/4, b/6,....b/512 m u x pcka2 pcka1 pcka0 pwme7-0 count = 1 load div 2 pwmscla count = 1 8-bit down counter 8-bit down counter prescaler taps:
pulse-width modulator (s12pwm8b8cv1) s12xs family reference manual, rev. 1.10 freescale semiconductor 385 clock a is used as an input to an 8-bit down counter. this down counter loads a user programmable scale value from the scale register (pwmscla). when the down counter reaches one, a pulse is output and the 8-bit counter is re-loaded. the output signal from this circuit is further divided by two. this gives a greater range with only a slight reduction in granularity. clock sa equals clock a divided by two times the value in the pwmscla register. note clock sa = clock a / (2 * pwmscla) when pwmscla = $00, pwmscla value is considered a full scale value of 256. clock a is thus divided by 512. similarly, clock b is used as an input to an 8-bit down counter followed by a divide by two producing clock sb. thus, clock sb equals clock b divided by two times the value in the pwmsclb register. note clock sb = clock b / (2 * pwmsclb) when pwmsclb = $00, pwmsclb value is considered a full scale value of 256. clock b is thus divided by 512. as an example, consider the case in which the user writes $ff into the pwmscla register. clock a for this case will be e divided by 4. a pulse will occur at a rate of once every 255x4 e cycles. passing this through the divide by two circuit produces a clock signal at an e divided by 2040 rate. similarly, a value of $01 in the pwmscla register when clock a is e divided by 4 will produce a clock at an e divided by 8 rate. writing to pwmscla or pwmsclb causes the associated 8-bit down counter to be re-loaded. otherwise, when changing rates the counter would have to count down to $01 before counting at the proper rate. forcing the associated counter to re-load the scale register value every time pwmscla or pwmsclb is written prevents this. note writing to the scale registers while channels are operating can cause irregularities in the pwm outputs. 13.4.1.3 clock select each pwm channel has the capability of selecting one of two clocks. for channels 0, 1, 4, and 5 the clock choices are clock a or clock sa. for channels 2, 3, 6, and 7 the choices are clock b or clock sb. the clock selection is done with the pclkx control bits in the pwmclk register. note changing clock control bits while channels are operating can cause irregularities in the pwm outputs.
pulse-width modulator (s12pwm8b8cv1) s12xs family reference manual, rev. 1.10 386 freescale semiconductor 13.4.2 pwm channel timers the main part of the pwm module are the actual timers. each of the timer channels has a counter, a period register and a duty register (each are 8-bit). the waveform output period is controlled by a match between the period register and the value in the counter. the duty is controlled by a match between the duty register and the counter value and causes the state of the output to change during the period. the starting polarity of the output is also selectable on a per channel basis. shown below in figure 13-19 is the block diagram for the pwm timer. figure 13-19. pwm timer channel block diagram 13.4.2.1 pwm enable each pwm channel has an enable bit (pwmex) to start its waveform output. when any of the pwmex bits are set (pwmex = 1), the associated pwm output signal is enabled immediately. however, the actual pwm waveform is not available on the associated pwm output until its clock source begins its next cycle due to the synchronization of pwmex and the clock source. an exception to this is when channels are concatenated. refer to section 13.4.2.7, ?wm 16-bit functions for more detail. note the ?st pwm cycle after enabling the channel can be irregular. clock source t r q q ppolx from port pwmp data register pwmex to pin driver gate 8-bit compare = pwmdtyx 8-bit compare = pwmperx caex t r q q 8-bit counter pwmcntx m u x m u x (clock edge sync) up/down reset
pulse-width modulator (s12pwm8b8cv1) s12xs family reference manual, rev. 1.10 freescale semiconductor 387 on the front end of the pwm timer, the clock is enabled to the pwm circuit by the pwmex bit being high. there is an edge-synchronizing circuit to guarantee that the clock will only be enabled or disabled at an edge. when the channel is disabled (pwmex = 0), the counter for the channel does not count. 13.4.2.2 pwm polarity each channel has a polarity bit to allow starting a waveform cycle with a high or low signal. this is shown on the block diagram as a mux select of either the q output or the q output of the pwm output ?p ?p. when one of the bits in the pwmpol register is set, the associated pwm channel output is high at the beginning of the waveform, then goes low when the duty count is reached. conversely, if the polarity bit is zero, the output starts low and then goes high when the duty count is reached. 13.4.2.3 pwm period and duty dedicated period and duty registers exist for each channel and are double buffered so that if they change while the channel is enabled, the change will not take effect until one of the following occurs: the effective period ends the counter is written (counter resets to $00) the channel is disabled in this way, the output of the pwm will always be either the old waveform or the new waveform, not some variation in between. if the channel is not enabled, then writes to the period and duty registers will go directly to the latches as well as the buffer. a change in duty or period can be forced into effect ?mmediately?by writing the new value to the duty and/or period registers and then writing to the counter. this forces the counter to reset and the new duty and/or period values to be latched. in addition, since the counter is readable, it is possible to know where the count is with respect to the duty value and software can be used to make adjustments note when forcing a new period or duty into effect immediately, an irregular pwm cycle can occur. depending on the polarity bit, the duty registers will contain the count of either the high time or the low time. 13.4.2.4 pwm timer counters each channel has a dedicated 8-bit up/down counter which runs at the rate of the selected clock source (see section 13.4.1, ?wm clock select for the available clock sources and rates). the counter compares to two registers, a duty register and a period register as shown in figure 13-19 . when the pwm counter matches the duty register, the output ?p-?p changes state, causing the pwm waveform to also change state. a match between the pwm counter and the period register behaves differently depending on what output mode is selected as shown in figure 13-19 and described in section 13.4.2.5, ?eft aligned outputs and section 13.4.2.6, ?enter aligned outputs .
pulse-width modulator (s12pwm8b8cv1) s12xs family reference manual, rev. 1.10 388 freescale semiconductor each channel counter can be read at anytime without affecting the count or the operation of the pwm channel. any value written to the counter causes the counter to reset to $00, the counter direction to be set to up, the immediate load of both duty and period registers with values from the buffers, and the output to change according to the polarity bit. when the channel is disabled (pwmex = 0), the counter stops. when a channel becomes enabled (pwmex = 1), the associated pwm counter continues from the count in the pwmcntx register. this allows the waveform to continue where it left off when the channel is re- enabled. when the channel is disabled, writing ? to the period register will cause the counter to reset on the next selected clock. note if the user wants to start a new ?lean?pwm waveform without any ?istory?from the old waveform, the user must write to channel counter (pwmcntx) prior to enabling the pwm channel (pwmex = 1). generally, writes to the counter are done prior to enabling a channel in order to start from a known state. however, writing a counter can also be done while the pwm channel is enabled (counting). the effect is similar to writing the counter when the channel is disabled, except that the new period is started immediately with the output set according to the polarity bit. note writing to the counter while the channel is enabled can cause an irregular pwm cycle to occur. the counter is cleared at the end of the effective period (see section 13.4.2.5, ?eft aligned outputs and section 13.4.2.6, ?enter aligned outputs for more details). 13.4.2.5 left aligned outputs the pwm timer provides the choice of two types of outputs, left aligned or center aligned. they are selected with the caex bits in the pwmcae register. if the caex bit is cleared (caex = 0), the corresponding pwm output will be left aligned. in left aligned output mode, the 8-bit counter is con?ured as an up counter only. it compares to two registers, a duty register and a period register as shown in the block diagram in figure 13-19 . when the pwm counter matches the duty register the output ?p-?p changes state causing the pwm waveform to also change state. a match between the pwm counter and the period register resets the counter and the output ?p-?p, as shown in figure 13-19 , as well as performing a load from the double buffer period and duty register to the associated registers, as described in section 13.4.2.3, ?wm period and duty . the counter counts from 0 to the value in the period register ?1. table 13-10. pwm timer counter conditions counter clears ($00) counter counts counter stops when pwmcntx register written to any value when pwm channel is enabled (pwmex = 1). counts from last value in pwmcntx. when pwm channel is disabled (pwmex = 0) effective period ends
pulse-width modulator (s12pwm8b8cv1) s12xs family reference manual, rev. 1.10 freescale semiconductor 389 note changing the pwm output mode from left aligned to center aligned output (or vice versa) while channels are operating can cause irregularities in the pwm output. it is recommended to program the output mode before enabling the pwm channel. figure 13-20. pwm left aligned output waveform to calculate the output frequency in left aligned output mode for a particular channel, take the selected clock source frequency for the channel (a, b, sa, or sb) and divide it by the value in the period register for that channel. pwmx frequency = clock (a, b, sa, or sb) / pwmperx pwmx duty cycle (high time as a% of period): polarity = 0 (ppolx = 0) duty cycle = [(pwmperx-pwmdtyx)/pwmperx] * 100% polarity = 1 (ppolx = 1) duty cycle = [pwmdtyx / pwmperx] * 100% as an example of a left aligned output, consider the following case: clock source = e, where e = 10 mhz (100 ns period) ppolx = 0 pwmperx = 4 pwmdtyx = 1 pwmx frequency = 10 mhz/4 = 2.5 mhz pwmx period = 400 ns pwmx duty cycle = 3/4 *100% = 75% the output waveform generated is shown in figure 13-21 . pwmdtyx period = pwmperx ppolx = 0 ppolx = 1
pulse-width modulator (s12pwm8b8cv1) s12xs family reference manual, rev. 1.10 390 freescale semiconductor figure 13-21. pwm left aligned output example waveform 13.4.2.6 center aligned outputs for center aligned output mode selection, set the caex bit (caex = 1) in the pwmcae register and the corresponding pwm output will be center aligned. the 8-bit counter operates as an up/down counter in this mode and is set to up whenever the counter is equal to $00. the counter compares to two registers, a duty register and a period register as shown in the block diagram in figure 13-19 . when the pwm counter matches the duty register, the output ?p-?p changes state, causing the pwm waveform to also change state. a match between the pwm counter and the period register changes the counter direction from an up-count to a down-count. when the pwm counter decrements and matches the duty register again, the output ?p-?p changes state causing the pwm output to also change state. when the pwm counter decrements and reaches zero, the counter direction changes from a down-count back to an up-count and a load from the double buffer period and duty registers to the associated registers is performed, as described in section 13.4.2.3, ?wm period and duty . the counter counts from 0 up to the value in the period register and then back down to 0. thus the effective period is pwmperx*2. note changing the pwm output mode from left aligned to center aligned output (or vice versa) while channels are operating can cause irregularities in the pwm output. it is recommended to program the output mode before enabling the pwm channel. figure 13-22. pwm center aligned output waveform period = 400 ns e = 100 ns duty cycle = 75% ppolx = 0 ppolx = 1 pwmdtyx pwmdtyx period = pwmperx*2 pwmperx pwmperx
pulse-width modulator (s12pwm8b8cv1) s12xs family reference manual, rev. 1.10 freescale semiconductor 391 to calculate the output frequency in center aligned output mode for a particular channel, take the selected clock source frequency for the channel (a, b, sa, or sb) and divide it by twice the value in the period register for that channel. pwmx frequency = clock (a, b, sa, or sb) / (2*pwmperx) pwmx duty cycle (high time as a% of period): polarity = 0 (ppolx = 0) duty cycle = [(pwmperx-pwmdtyx)/pwmperx] * 100% polarity = 1 (ppolx = 1) duty cycle = [pwmdtyx / pwmperx] * 100%
pulse-width modulator (s12pwm8b8cv1) s12xs family reference manual, rev. 1.10 392 freescale semiconductor as an example of a center aligned output, consider the following case: clock source = e, where e = 10 mhz (100 ns period) ppolx = 0 pwmperx = 4 pwmdtyx = 1 pwmx frequency = 10 mhz/8 = 1.25 mhz pwmx period = 800 ns pwmx duty cycle = 3/4 *100% = 75% shown in figure 13-23 is the output waveform generated. figure 13-23. pwm center aligned output example waveform 13.4.2.7 pwm 16-bit functions the pwm timer also has the option of generating 8-channels of 8-bits or 4-channels of 16-bits for greater pwm resolution. this 16-bit channel option is achieved through the concatenation of two 8-bit channels. the pwmctl register contains four control bits, each of which is used to concatenate a pair of pwm channels into one 16-bit channel. channels 6 and 7 are concatenated with the con67 bit, channels 4 and 5 are concatenated with the con45 bit, channels 2 and 3 are concatenated with the con23 bit, and channels 0 and 1 are concatenated with the con01 bit. note change these bits only when both corresponding channels are disabled. when channels 6 and 7 are concatenated, channel 6 registers become the high order bytes of the double byte channel, as shown in figure 13-24 . similarly, when channels 4 and 5 are concatenated, channel 4 registers become the high order bytes of the double byte channel. when channels 2 and 3 are concatenated, channel 2 registers become the high order bytes of the double byte channel. when channels 0 and 1 are concatenated, channel 0 registers become the high order bytes of the double byte channel. when using the 16-bit concatenated mode, the clock source is determined by the low order 8-bit channel clock select control bits. that is channel 7 when channels 6 and 7 are concatenated, channel 5 when channels 4 and 5 are concatenated, channel 3 when channels 2 and 3 are concatenated, and channel 1 when channels 0 and 1 are concatenated. the resulting pwm is output to the pins of the corresponding low order 8-bit channel as also shown in figure 13-24 . the polarity of the resulting pwm output is controlled by the ppolx bit of the corresponding low order 8-bit channel as well. e = 100 ns duty cycle = 75% e = 100 ns period = 800 ns
pulse-width modulator (s12pwm8b8cv1) s12xs family reference manual, rev. 1.10 freescale semiconductor 393 figure 13-24. pwm 16-bit mode once concatenated mode is enabled (conxx bits set in pwmctl register), enabling/disabling the corresponding 16-bit pwm channel is controlled by the low order pwmex bit. in this case, the high order bytes pwmex bits have no effect and their corresponding pwm output is disabled. in concatenated mode, writes to the 16-bit counter by using a 16-bit access or writes to either the low or high order byte of the counter will reset the 16-bit counter. reads of the 16-bit counter must be made by 16-bit access to maintain data coherency. pwmcnt6 pwcnt7 pwm7 clock source 7 high low period/duty compare pwmcnt4 pwcnt5 pwm5 clock source 5 high low period/duty compare pwmcnt2 pwcnt3 pwm3 clock source 3 high low period/duty compare pwmcnt0 pwcnt1 pwm1 clock source 1 high low period/duty compare
pulse-width modulator (s12pwm8b8cv1) s12xs family reference manual, rev. 1.10 394 freescale semiconductor either left aligned or center aligned output mode can be used in concatenated mode and is controlled by the low order caex bit. the high order caex bit has no effect. table 13-11 is used to summarize which channels are used to set the various control bits when in 16-bit mode. 13.4.2.8 pwm boundary cases table 13-12 summarizes the boundary conditions for the pwm regardless of the output mode (left aligned or center aligned) and 8-bit (normal) or 16-bit (concatenation). 13.5 resets the reset state of each individual bit is listed within the section 13.3.2, ?egister descriptions which details the registers and their bit-?lds. all special functions or modes which are initialized during or just following reset are described within this section. the 8-bit up/down counter is con?ured as an up counter out of reset. all the channels are disabled and all the counters do not count. table 13-11. 16-bit concatenation mode summary conxx pwmex ppolx pclkx caex pwmx output con67 pwme7 ppol7 pclk7 cae7 pwm7 con45 pwme5 ppol5 pclk5 cae5 pwm5 con23 pwme3 ppol3 pclk3 cae3 pwm3 con01 pwme1 ppol1 pclk1 cae1 pwm1 table 13-12. pwm boundary cases pwmdtyx pwmperx ppolx pwmx output $00 (indicates no duty) >$00 1 always low $00 (indicates no duty) >$00 0 always high xx $00 1 (indicates no period) 1 counter = $00 and does not count. 1 always high xx $00 1 (indicates no period) 0 always low >= pwmperx xx 1 always high >= pwmperx xx 0 always low
pulse-width modulator (s12pwm8b8cv1) s12xs family reference manual, rev. 1.10 freescale semiconductor 395 13.6 interrupts the pwm module has only one interrupt which is generated at the time of emergency shutdown, if the corresponding enable bit (pwmie) is set. this bit is the enable for the interrupt. the interrupt ?g pwmif is set whenever the input level of the pwm7 channel changes while pwm7ena = 1 or when pwmena is being asserted while the level at pwm7 is active. in stop mode or wait mode (with the pswai bit set), the emergency shutdown feature will drive the pwm outputs to their shutdown output levels but the pwmif ?g will not be set. a description of the registers involved and affected due to this interrupt is explained in section 13.3.2.15, ?wm shutdown register (pwmsdn) . the pwm block only generates the interrupt and does not service it. the interrupt signal name is pwm interrupt signal.
pulse-width modulator (s12pwm8b8cv1) s12xs family reference manual, rev. 1.10 396 freescale semiconductor
s12xs family reference manual, rev. 1.10 freescale semiconductor 397 chapter 14 serial communication interface (s12sciv5) 14.1 introduction this block guide provides an overview of the serial communication interface (sci) module. the sci allows asynchronous serial communications with peripheral devices and other cpus. 14.1.1 glossary ir: infrared irda: infrared design associate irq: interrupt request lin: local interconnect network lsb: least signi?ant bit msb: most signi?ant bit nrz: non-return-to-zero rzi: return-to-zero-inverted rxd: receive pin sci : serial communication interface txd: transmit pin table 14-1. revision history version number revision date effective date author description of changes 05.01 04/16/2004 update or and pf flag description; correct baud rate tolerance in 4.7.5.1 and 4.7.5.2; clean up classification and nda message banners 05.02 10/14/2005 correct alternative registers address; remove unavailable baud rate in table1-16 05.03 12/25/2008 remove redundancy comments in figure1-2 05.04 08/05/2009 fix typo, scibdl reset value be 0x04, not 0x00
serial communication interface (s12sciv5) s12xs family reference manual, rev. 1.10 398 freescale semiconductor 14.1.2 features the sci includes these distinctive features: full-duplex or single-wire operation standard mark/space non-return-to-zero (nrz) format selectable irda 1.4 return-to-zero-inverted (rzi) format with programmable pulse widths 13-bit baud rate selection programmable 8-bit or 9-bit data format separately enabled transmitter and receiver programmable polarity for transmitter and receiver programmable transmitter output parity two receiver wakeup methods: idle line wakeup address mark wakeup interrupt-driven operation with eight flags: transmitter empty transmission complete receiver full idle receiver input receiver overrun noise error framing error parity error receive wakeup on active edge transmit collision detect supporting lin break detect supporting lin receiver framing error detection hardware parity checking 1/16 bit-time noise detection 14.1.3 modes of operation the sci functions the same in normal, special, and emulation modes. it has two low power modes, wait and stop modes. run mode wait mode stop mode
serial communication interface (s12sciv5) s12xs family reference manual, rev. 1.10 freescale semiconductor 399 14.1.4 block diagram figure 14-1 is a high level block diagram of the sci module, showing the interaction of various function blocks. figure 14-1. sci block diagram sci data register rxd data in data out txd receive shift register infrared decoder receive & wakeup control data format control transmit control baud rate generator bus clock 1/16 transmit shift register sci data register receive interrupt generation transmit interrupt generation infrared encoder idle rdrf/or tc tdre brkd berr rxedg sci interrupt request
serial communication interface (s12sciv5) s12xs family reference manual, rev. 1.10 400 freescale semiconductor 14.2 external signal description the sci module has a total of two external pins. 14.2.1 txd ?transmit pin the txd pin transmits sci (standard or infrared) data. it will idle high in either mode and is high impedance anytime the transmitter is disabled. 14.2.2 rxd ?receive pin the rxd pin receives sci (standard or infrared) data. an idle line is detected as a line high. this input is ignored when the receiver is disabled and should be terminated to a known voltage. 14.3 memory map and register de?ition this section provides a detailed description of all the sci registers. 14.3.1 module memory map and register de?ition the memory map for the sci module is given below in figure 14-2 . the address listed for each register is the address offset. the total address for each register is the sum of the base address for the sci module and the address offset for each register.
serial communication interface (s12sciv5) s12xs family reference manual, rev. 1.10 freescale semiconductor 401 14.3.2 register descriptions this section consists of register descriptions in address order. each description includes a standard register diagram with an associated ?ure number. writes to a reserved register locations do not have any effect and reads of these locations return a zero. details of register bit and ?ld function follow the register diagrams, in bit order. register name bit 7 6 5 4 3 2 1 bit 0 0x0000 scibdh 1 r iren tnp1 tnp0 sbr12 sbr11 sbr10 sbr9 sbr8 w 0x0001 scibdl 1 r sbr7 sbr6 sbr5 sbr4 sbr3 sbr2 sbr1 sbr0 w 0x0002 scicr1 1 r loops sciswai rsrc m wake ilt pe pt w 0x0000 sciasr1 2 r rxedgif 0000 berrv berrif bkdif w 0x0001 sciacr1 2 r rxedgie 00000 berrie bkdie w 0x0002 sciacr2 2 r00000 berrm1 berrm0 bkdfe w 0x0003 scicr2 r tie tcie rie ilie te re rwu sbk w 0x0004 scisr1 r tdre tc rdrf idle or nf fe pf w 0x0005 scisr2 r amap 00 txpol rxpol brk13 txdir raf w 0x0006 scidrh rr8 t8 000000 w 0x0007 scidrl rr7r6r5r4r3r2r1r0 wt7t6t5t4t3t2t1t0 1.these registers are accessible if the amap bit in the scisr2 register is set to zero. 2,these registers are accessible if the amap bit in the scisr2 register is set to one. = unimplemented or reserved figure 14-2. sci register summary
serial communication interface (s12sciv5) s12xs family reference manual, rev. 1.10 402 freescale semiconductor 14.3.2.1 sci baud rate registers (scibdh, scibdl) read: anytime, if amap = 0. if only scibdh is written to, a read will not return the correct data until scibdl is written to as well, following a write to scibdh. write: anytime, if amap = 0. note those two registers are only visible in the memory map if amap = 0 (reset condition). the sci baud rate register is used by to determine the baud rate of the sci, and to control the infrared modulation/demodulation submodule. module base + 0x0000 76543210 r iren tnp1 tnp0 sbr12 sbr11 sbr10 sbr9 sbr8 w reset 0 0 0 00000 figure 14-3. sci baud rate register (scibdh) module base + 0x0001 76543210 r sbr7 sbr6 sbr5 sbr4 sbr3 sbr2 sbr1 sbr0 w reset 0 0 0 00100 figure 14-4. sci baud rate register (scibdl) table 14-2. scibdh and scibdl field descriptions field description 7 iren infrared enable bit ?this bit enables/disables the infrared modulation/demodulation submodule. 0 ir disabled 1 ir enabled 6:5 tnp[1:0] transmitter narrow pulse bits these bits enable whether the sci transmits a 1/16, 3/16, 1/32 or 1/4 narrow pulse. see table 14-3 . 4:0 7:0 sbr[12:0] sci baud rate bits ?the baud rate for the sci is determined by the bits in this register. the baud rate is calculated two different ways depending on the state of the iren bit. the formulas for calculating the baud rate are: when iren = 0 then, sci baud rate = sci bus clock / (16 x sbr[12:0]) when iren = 1 then, sci baud rate = sci bus clock / (32 x sbr[12:1]) note: the baud rate generator is disabled after reset and not started until the te bit or the re bit is set for the ?st time. the baud rate generator is disabled when (sbr[12:0] = 0 and iren = 0) or (sbr[12:1] = 0 and iren = 1). note: writing to scibdh has no effect without writing to scibdl, because writing to scibdh puts the data in a temporary location until scibdl is written to.
serial communication interface (s12sciv5) s12xs family reference manual, rev. 1.10 freescale semiconductor 403 14.3.2.2 sci control register 1 (scicr1) read: anytime, if amap = 0. write: anytime, if amap = 0. note this register is only visible in the memory map if amap = 0 (reset condition). table 14-3. irsci transmit pulse width tnp[1:0] narrow pulse width 11 1/4 10 1/32 01 1/16 00 3/16 module base + 0x0002 76543210 r loops sciswai rsrc m wake ilt pe pt w reset 0 0 0 00000 figure 14-5. sci control register 1 (scicr1) table 14-4. scicr1 field descriptions field description 7 loops loop select bit loops enables loop operation. in loop operation, the rxd pin is disconnected from the sci and the transmitter output is internally connected to the receiver input. both the transmitter and the receiver must be enabled to use the loop function. 0 normal operation enabled 1 loop operation enabled the receiver input is determined by the rsrc bit. 6 sciswai sci stop in wait mode bit ?sciswai disables the sci in wait mode. 0 sci enabled in wait mode 1 sci disabled in wait mode 5 rsrc receiver source bit ?when loops = 1, the rsrc bit determines the source for the receiver shift register input. see table 14-5 . 0 receiver input internally connected to transmitter output 1 receiver input connected externally to transmitter 4 m data format mode bit ?mode determines whether data characters are eight or nine bits long. 0 one start bit, eight data bits, one stop bit 1 one start bit, nine data bits, one stop bit 3 wake wakeup condition bit wake determines which condition wakes up the sci: a logic 1 (address mark) in the most signi?ant bit position of a received data character or an idle condition on the rxd pin. 0 idle line wakeup 1 address mark wakeup
serial communication interface (s12sciv5) s12xs family reference manual, rev. 1.10 404 freescale semiconductor 2 ilt idle line type bit ?ilt determines when the receiver starts counting logic 1s as idle character bits. the counting begins either after the start bit or after the stop bit. if the count begins after the start bit, then a string of logic 1s preceding the stop bit may cause false recognition of an idle character. beginning the count after the stop bit avoids false idle character recognition, but requires properly synchronized transmissions. 0 idle character bit count begins after start bit 1 idle character bit count begins after stop bit 1 pe parity enable bit pe enables the parity function. when enabled, the parity function inserts a parity bit in the most signi?ant bit position. 0 parity function disabled 1 parity function enabled 0 pt parity type bit pt determines whether the sci generates and checks for even parity or odd parity. with even parity, an even number of 1s clears the parity bit and an odd number of 1s sets the parity bit. with odd parity, an odd number of 1s clears the parity bit and an even number of 1s sets the parity bit. 1 even parity 1 odd parity table 14-5. loop functions loops rsrc function 0 x normal operation 1 0 loop mode with transmitter output internally connected to receiver input 1 1 single-wire mode with txd pin connected to receiver input table 14-4. scicr1 field descriptions (continued) field description
serial communication interface (s12sciv5) s12xs family reference manual, rev. 1.10 freescale semiconductor 405 14.3.2.3 sci alternative status register 1 (sciasr1) read: anytime, if amap = 1 write: anytime, if amap = 1 module base + 0x0000 76543210 r rxedgif 0 0 0 0 berrv berrif bkdif w reset 0 0 0 00000 = unimplemented or reserved figure 14-6. sci alternative status register 1 (sciasr1) table 14-6. sciasr1 field descriptions field description 7 rxedgif receive input active edge interrupt flag ?rxedgif is asserted, if an active edge (falling if rxpol = 0, rising if rxpol = 1) on the rxd input occurs. rxedgif bit is cleared by writing a ??to it. 0 no active receive on the receive input has occurred 1 an active edge on the receive input has occurred 2 berrv bit error value berrv re?cts the state of the rxd input when the bit error detect circuitry is enabled and a mismatch to the expected value happened. the value is only meaningful, if berrif = 1. 0 a low input was sampled, when a high was expected 1 a high input reassembled, when a low was expected 1 berrif bit error interrupt flag ?berrif is asserted, when the bit error detect circuitry is enabled and if the value sampled at the rxd input does not match the transmitted value. if the berrie interrupt enable bit is set an interrupt will be generated. the berrif bit is cleared by writing a ??to it. 0 no mismatch detected 1 a mismatch has occurred 0 bkdif break detect interrupt flag bkdif is asserted, if the break detect circuitry is enabled and a break signal is received. if the bkdie interrupt enable bit is set an interrupt will be generated. the bkdif bit is cleared by writing a ??to it. 0 no break signal was received 1 a break signal was received
serial communication interface (s12sciv5) s12xs family reference manual, rev. 1.10 406 freescale semiconductor 14.3.2.4 sci alternative control register 1 (sciacr1) read: anytime, if amap = 1 write: anytime, if amap = 1 module base + 0x0001 76543210 r rxedgie 00000 berrie bkdie w reset 0 0 0 00000 = unimplemented or reserved figure 14-7. sci alternative control register 1 (sciacr1) table 14-7. sciacr1 field descriptions field description 7 rsedgie receive input active edge interrupt enable rxedgie enables the receive input active edge interrupt ?g, rxedgif, to generate interrupt requests. 0 rxedgif interrupt requests disabled 1 rxedgif interrupt requests enabled 1 berrie bit error interrupt enable ?berrie enables the bit error interrupt ?g, berrif, to generate interrupt requests. 0 berrif interrupt requests disabled 1 berrif interrupt requests enabled 0 bkdie break detect interrupt enable ?bkdie enables the break detect interrupt ?g, bkdif, to generate interrupt requests. 0 bkdif interrupt requests disabled 1 bkdif interrupt requests enabled
serial communication interface (s12sciv5) s12xs family reference manual, rev. 1.10 freescale semiconductor 407 14.3.2.5 sci alternative control register 2 (sciacr2) read: anytime, if amap = 1 write: anytime, if amap = 1 module base + 0x0002 76543210 r00000 berrm1 berrm0 bkdfe w reset 0 0 0 00000 = unimplemented or reserved figure 14-8. sci alternative control register 2 (sciacr2) table 14-8. sciacr2 field descriptions field description 2:1 berrm[1:0] bit error mode ?those two bits determines the functionality of the bit error detect feature. see table 14-9 . 0 bkdfe break detect feature enable ?bkdfe enables the break detect circuitry. 0 break detect circuit disabled 1 break detect circuit enabled table 14-9. bit error mode coding berrm1 berrm0 function 0 0 bit error detect circuit is disabled 0 1 receive input sampling occurs during the 9th time tick of a transmitted bit (refer to figure 14-19 ) 1 0 receive input sampling occurs during the 13th time tick of a transmitted bit (refer to figure 14-19 ) 1 1 reserved
serial communication interface (s12sciv5) s12xs family reference manual, rev. 1.10 408 freescale semiconductor 14.3.2.6 sci control register 2 (scicr2) read: anytime write: anytime module base + 0x0003 76543210 r tie tcie rie ilie te re rwu sbk w reset 0 0 0 00000 figure 14-9. sci control register 2 (scicr2) table 14-10. scicr2 field descriptions field description 7 tie transmitter interrupt enable bit ?tie enables the transmit data register empty ?g, tdre, to generate interrupt requests. 0 tdre interrupt requests disabled 1 tdre interrupt requests enabled 6 tcie transmission complete interrupt enable bit tcie enables the transmission complete ?g, tc, to generate interrupt requests. 0 tc interrupt requests disabled 1 tc interrupt requests enabled 5 rie receiver full interrupt enable bit rie enables the receive data register full ?g, rdrf, or the overrun ?g, or, to generate interrupt requests. 0 rdrf and or interrupt requests disabled 1 rdrf and or interrupt requests enabled 4 ilie idle line interrupt enable bit ?ilie enables the idle line ?g, idle, to generate interrupt requests. 0 idle interrupt requests disabled 1 idle interrupt requests enabled 3 te transmitter enable bit ?te enables the sci transmitter and con?ures the txd pin as being controlled by the sci. the te bit can be used to queue an idle preamble. 0 transmitter disabled 1 transmitter enabled 2 re receiver enable bit ?re enables the sci receiver. 0 receiver disabled 1 receiver enabled 1 rwu receiver wakeup bit ?standby state 0 normal operation. 1 rwu enables the wakeup function and inhibits further receiver interrupt requests. normally, hardware wakes the receiver by automatically clearing rwu. 0 sbk send break bit ?toggling sbk sends one break character (10 or 11 logic 0s, respectively 13 or 14 logics 0s if brk13 is set). toggling implies clearing the sbk bit before the break character has ?ished transmitting. as long as sbk is set, the transmitter continues to send complete break characters (10 or 11 bits, respectively 13 or 14 bits). 0 no break characters 1 transmit break characters
serial communication interface (s12sciv5) s12xs family reference manual, rev. 1.10 freescale semiconductor 409 14.3.2.7 sci status register 1 (scisr1) the scisr1 and scisr2 registers provides inputs to the mcu for generation of sci interrupts. also, these registers can be polled by the mcu to check the status of these bits. the ?g-clearing procedures require that the status register be read followed by a read or write to the sci data register.it is permissible to execute other instructions between the two steps as long as it does not compromise the handling of i/o, but the order of operations is important for ?g clearing. read: anytime write: has no meaning or effect module base + 0x0004 76543210 r tdre tc rdrf idle or nf fe pf w reset 1 1 0 00000 = unimplemented or reserved figure 14-10. sci status register 1 (scisr1) table 14-11. scisr1 field descriptions field description 7 tdre transmit data register empty flag ?tdre is set when the transmit shift register receives a byte from the sci data register. when tdre is 1, the transmit data register (scidrh/l) is empty and can receive a new value to transmit.clear tdre by reading sci status register 1 (scisr1), with tdre set and then writing to sci data register low (scidrl). 0 no byte transferred to transmit shift register 1 byte transferred to transmit shift register; transmit data register empty 6 tc transmit complete flag tc is set low when there is a transmission in progress or when a preamble or break character is loaded. tc is set high when the tdre ?g is set and no data, preamble, or break character is being transmitted.when tc is set, the txd pin becomes idle (logic 1). clear tc by reading sci status register 1 (scisr1) with tc set and then writing to sci data register low (scidrl). tc is cleared automatically when data, preamble, or break is queued and ready to be sent. tc is cleared in the event of a simultaneous set and clear of the tc ?g (transmission not complete). 0 transmission in progress 1 no transmission in progress 5 rdrf receive data register full flag rdrf is set when the data in the receive shift register transfers to the sci data register. clear rdrf by reading sci status register 1 (scisr1) with rdrf set and then reading sci data register low (scidrl). 0 data not available in sci data register 1 received data available in sci data register 4 idle idle line flag idle is set when 10 consecutive logic 1s (if m = 0) or 11 consecutive logic 1s (if m =1) appear on the receiver input. once the idle ?g is cleared, a valid frame must again set the rdrf ?g before an idle condition can set the idle ?g.clear idle by reading sci status register 1 (scisr1) with idle set and then reading sci data register low (scidrl). 0 receiver input is either active now or has never become active since the idle ?g was last cleared 1 receiver input has become idle note: when the receiver wakeup bit (rwu) is set, an idle line condition does not set the idle ?g.
serial communication interface (s12sciv5) s12xs family reference manual, rev. 1.10 410 freescale semiconductor 3 or overrun flag ?or is set when software fails to read the sci data register before the receive shift register receives the next frame. the or bit is set immediately after the stop bit has been completely received for the second frame. the data in the shift register is lost, but the data already in the sci data registers is not affected. clear or by reading sci status register 1 (scisr1) with or set and then reading sci data register low (scidrl). 0 no overrun 1 overrun note: or ?g may read back as set when rdrf ?g is clear. this may happen if the following sequence of events occurs: 1. after the ?st frame is received, read status register scisr1 (returns rdrf set and or ?g clear); 2. receive second frame without reading the ?st frame in the data register (the second frame is not received and or ?g is set); 3. read data register scidrl (returns ?st frame and clears rdrf ?g in the status register); 4. read status register scisr1 (returns rdrf clear and or set). event 3 may be at exactly the same time as event 2 or any time after. when this happens, a dummy scidrl read following event 4 will be required to clear the or ?g if further frames are to be received. 2 nf noise flag nf is set when the sci detects noise on the receiver input. nf bit is set during the same cycle as the rdrf ?g but does not get set in the case of an overrun. clear nf by reading sci status register 1(scisr1), and then reading sci data register low (scidrl). 0 no noise 1 noise 1 fe framing error flag fe is set when a logic 0 is accepted as the stop bit. fe bit is set during the same cycle as the rdrf ?g but does not get set in the case of an overrun. fe inhibits further data reception until it is cleared. clear fe by reading sci status register 1 (scisr1) with fe set and then reading the sci data register low (scidrl). 0 no framing error 1 framing error 0 pf parity error flag pf is set when the parity enable bit (pe) is set and the parity of the received data does not match the parity type bit (pt). pf bit is set during the same cycle as the rdrf ?g but does not get set in the case of an overrun. clear pf by reading sci status register 1 (scisr1), and then reading sci data register low (scidrl). 0 no parity error 1 parity error table 14-11. scisr1 field descriptions (continued) field description
serial communication interface (s12sciv5) s12xs family reference manual, rev. 1.10 freescale semiconductor 411 14.3.2.8 sci status register 2 (scisr2) read: anytime write: anytime module base + 0x0005 76543210 r amap 00 txpol rxpol brk13 txdir raf w reset 0 0 0 00000 = unimplemented or reserved figure 14-11. sci status register 2 (scisr2) table 14-12. scisr2 field descriptions field description 7 amap alternative map this bit controls which registers sharing the same address space are accessible. in the reset condition the sci behaves as previous versions. setting amap=1 allows the access to another set of control and status registers and hides the baud rate and sci control register 1. 0 the registers labelled scibdh (0x0000),scibdl (0x0001), scicr1 (0x0002) are accessible 1 the registers labelled sciasr1 (0x0000),sciacr1 (0x0001), sciacr2 (0x00002) are accessible 4 txpol transmit polarity this bit control the polarity of the transmitted data. in nrz format, a one is represented by a mark and a zero is represented by a space for normal polarity, and the opposite for inverted polarity. in irda format, a zero is represented by short high pulse in the middle of a bit time remaining idle low for a one for normal polarity, and a zero is represented by short low pulse in the middle of a bit time remaining idle high for a one for inverted polarity. 0 normal polarity 1 inverted polarity 3 rxpol receive polarity ?this bit control the polarity of the received data. in nrz format, a one is represented by a mark and a zero is represented by a space for normal polarity, and the opposite for inverted polarity. in irda format, a zero is represented by short high pulse in the middle of a bit time remaining idle low for a one for normal polarity, and a zero is represented by short low pulse in the middle of a bit time remaining idle high for a one for inverted polarity. 0 normal polarity 1 inverted polarity 2 brk13 break transmit character length this bit determines whether the transmit break character is 10 or 11 bit respectively 13 or 14 bits long. the detection of a framing error is not affected by this bit. 0 break character is 10 or 11 bit long 1 break character is 13 or 14 bit long 1 txdir transmitter pin data direction in single-wire mode ?this bit determines whether the txd pin is going to be used as an input or output, in the single-wire mode of operation. this bit is only relevant in the single-wire mode of operation. 0 txd pin to be used as an input in single-wire mode 1 txd pin to be used as an output in single-wire mode 0 raf receiver active flag raf is set when the receiver detects a logic 0 during the rt1 time period of the start bit search. raf is cleared when the receiver detects an idle character. 0 no reception in progress 1 reception in progress
serial communication interface (s12sciv5) s12xs family reference manual, rev. 1.10 412 freescale semiconductor 14.3.2.9 sci data registers (scidrh, scidrl) read: anytime; reading accesses sci receive data register write: anytime; writing accesses sci transmit data register; writing to r8 has no effect note if the value of t8 is the same as in the previous transmission, t8 does not have to be rewritten.the same value is transmitted until t8 is rewritten in 8-bit data format, only sci data register low (scidrl) needs to be accessed. when transmitting in 9-bit data format and using 8-bit write instructions, write ?st to sci data register high (scidrh), then scidrl. module base + 0x0006 76543210 rr8 t8 000000 w reset 0 0 0 00000 = unimplemented or reserved figure 14-12. sci data registers (scidrh) module base + 0x0007 76543210 rr7r6r5r4r3r2r1r0 w t7 t6 t5 t4 t3 t2 t1 t0 reset 0 0 0 00000 figure 14-13. sci data registers (scidrl) table 14-13. scidrh and scidrl field descriptions field description scidrh 7 r8 received bit 8 ?r8 is the ninth data bit received when the sci is con?ured for 9-bit data format (m = 1). scidrh 6 t8 transmit bit 8 ?t8 is the ninth data bit transmitted when the sci is con?ured for 9-bit data format (m = 1). scidrl 7:0 r[7:0] t[7:0] r7:r0 ?received bits seven through zero for 9-bit or 8-bit data formats t7:t0 ?transmit bits seven through zero for 9-bit or 8-bit formats
serial communication interface (s12sciv5) s12xs family reference manual, rev. 1.10 freescale semiconductor 413 14.4 functional description this section provides a complete functional description of the sci block, detailing the operation of the design from the end user perspective in a number of subsections. figure 14-14 shows the structure of the sci module. the sci allows full duplex, asynchronous, serial communication between the cpu and remote devices, including other cpus. the sci transmitter and receiver operate independently, although they use the same baud rate generator. the cpu monitors the status of the sci, writes the data to be transmitted, and processes received data. figure 14-14. detailed sci block diagram sci data receive shift register sci data register transmit shift register register baud rate generator sbr12:sbr0 bus transmit control 16 receive and wakeup data format control control t8 pf fe nf rdrf idle tie or tcie tdre tc r8 raf loops rwu re pe ilt pt wake m clock ilie rie rxd rsrc sbk loops te rsrc iren r16xclk ir_rxd txd ir_txd r16xclk r32xclk tnp[1:0] iren transmit encoder receive decoder scrxd sctxd infrared infrared tc tdre rdrf/or idle active edge detect break detect rxd bkdfe berrm[1:0] bkdie bkdif rxedgie rxedgif berrie berrif sci interrupt request lin transmit collision detect
serial communication interface (s12sciv5) s12xs family reference manual, rev. 1.10 414 freescale semiconductor 14.4.1 infrared interface submodule this module provides the capability of transmitting narrow pulses to an ir led and receiving narrow pulses and transforming them to serial bits, which are sent to the sci. the irda physical layer speci?ation de?es a half-duplex infrared communication link for exchange data. the full standard includes data rates up to 16 mbits/s. this design covers only data rates between 2.4 kbits/s and 115.2 kbits/s. the infrared submodule consists of two major blocks: the transmit encoder and the receive decoder. the sci transmits serial bits of data which are encoded by the infrared submodule to transmit a narrow pulse for every zero bit. no pulse is transmitted for every one bit. when receiving data, the ir pulses should be detected using an ir photo diode and transformed to cmos levels by the ir receive decoder (external from the mcu). the narrow pulses are then stretched by the infrared submodule to get back to a serial bit stream to be received by the sci.the polarity of transmitted pulses and expected receive pulses can be inverted so that a direct connection can be made to external irda transceiver modules that uses active low pulses. the infrared submodule receives its clock sources from the sci. one of these two clocks are selected in the infrared submodule in order to generate either 3/16, 1/16, 1/32 or 1/4 narrow pulses during transmission. the infrared block receives two clock sources from the sci, r16xclk and r32xclk, which are con?ured to generate the narrow pulse width during transmission. the r16xclk and r32xclk are internal clocks with frequencies 16 and 32 times the baud rate respectively. both r16xclk and r32xclk clocks are used for transmitting data. the receive decoder uses only the r16xclk clock. 14.4.1.1 infrared transmit encoder the infrared transmit encoder converts serial bits of data from transmit shift register to the txd pin. a narrow pulse is transmitted for a zero bit and no pulse for a one bit. the narrow pulse is sent in the middle of the bit with a duration of 1/32, 1/16, 3/16 or 1/4 of a bit time. a narrow high pulse is transmitted for a zero bit when txpol is cleared, while a narrow low pulse is transmitted for a zero bit when txpol is set. 14.4.1.2 infrared receive decoder the infrared receive block converts data from the rxd pin to the receive shift register. a narrow pulse is expected for each zero received and no pulse is expected for each one received. a narrow high pulse is expected for a zero bit when rxpol is cleared, while a narrow low pulse is expected for a zero bit when rxpol is set. this receive decoder meets the edge jitter requirement as de?ed by the irda serial infrared physical layer speci?ation. 14.4.2 lin support this module provides some basic support for the lin protocol. at ?st this is a break detect circuitry making it easier for the lin software to distinguish a break character from an incoming data stream. as a further addition is supports a collision detection at the bit level as well as cancelling pending transmissions.
serial communication interface (s12sciv5) s12xs family reference manual, rev. 1.10 freescale semiconductor 415 14.4.3 data format the sci uses the standard nrz mark/space data format. when infrared is enabled, the sci uses rzi data format where zeroes are represented by light pulses and ones remain low. see figure 14-15 below. figure 14-15. sci data formats each data character is contained in a frame that includes a start bit, eight or nine data bits, and a stop bit. clearing the m bit in sci control register 1 con?ures the sci for 8-bit data characters. a frame with eight data bits has a total of 10 bits. setting the m bit con?ures the sci for nine-bit data characters. a frame with nine data bits has a total of 11 bits. when the sci is con?ured for 9-bit data characters, the ninth data bit is the t8 bit in sci data register high (scidrh). it remains unchanged after transmission and can be used repeatedly without rewriting it. a frame with nine data bits has a total of 11 bits. table 14-14. example of 8-bit data formats start bit data bits address bits parity bits stop bit 18001 17011 17 1 1 1 the address bit identi?s the frame as an address character. see section 14.4.6.6, ?eceiver wakeup . 01 table 14-15. example of 9-bit data formats start bit data bits address bits parity bits stop bit 19001 18011 18 1 1 01 bit 5 start bit bit 0 bit 1 next stop bit start bit 8-bit data format (bit m in scicr1 clear) start bit bit 0 next stop bit start bit 9-bit data format (bit m in scicr1 set) bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit 8 bit 2 bit 3 bit 4 bit 6 bit 7 possible parity bit possible parity bit standard sci data infrared sci data standard sci data infrared sci data
serial communication interface (s12sciv5) s12xs family reference manual, rev. 1.10 416 freescale semiconductor 14.4.4 baud rate generation a 13-bit modulus counter in the baud rate generator derives the baud rate for both the receiver and the transmitter. the value from 0 to 8191 written to the sbr12:sbr0 bits determines the bus clock divisor. the sbr bits are in the sci baud rate registers (scibdh and scibdl). the baud rate clock is synchronized with the bus clock and drives the receiver. the baud rate clock divided by 16 drives the transmitter. the receiver has an acquisition rate of 16 samples per bit time. baud rate generation is subject to one source of error: integer division of the bus clock may not give the exact target frequency. table 14-16 lists some examples of achieving target baud rates with a bus clock frequency of 25 mhz. when iren = 0 then, sci baud rate = sci bus clock / (16 * scibr[12:0]) 1 the address bit identi?s the frame as an address character. see section 14.4.6.6, ?eceiver wakeup . table 14-16. baud rates (example: bus clock = 25 mhz) bits sbr[12:0] receiver clock (hz) transmitter clock (hz) target baud rate error (%) 41 609,756.1 38,109.8 38,400 .76 81 308,642.0 19,290.1 19,200 .47 163 153,374.2 9585.9 9,600 .16 326 76,687.1 4792.9 4,800 .15 651 38,402.5 2400.2 2,400 .01 1302 19,201.2 1200.1 1,200 .01 2604 9600.6 600.0 600 .00 5208 4800.0 300.0 300 .00
serial communication interface (s12sciv5) s12xs family reference manual, rev. 1.10 freescale semiconductor 417 14.4.5 transmitter figure 14-16. transmitter block diagram 14.4.5.1 transmitter character length the sci transmitter can accommodate either 8-bit or 9-bit data characters. the state of the m bit in sci control register 1 (scicr1) determines the length of data characters. when transmitting 9-bit data, bit t8 in sci data register high (scidrh) is the ninth bit (bit 8). 14.4.5.2 character transmission to transmit data, the mcu writes the data bits to the sci data registers (scidrh/scidrl), which in turn are transferred to the transmitter shift register. the transmit shift register then shifts a frame out through the txd pin, after it has prefaced them with a start bit and appended them with a stop bit. the sci data registers (scidrh and scidrl) are the write-only buffers between the internal data bus and the transmit shift register. pe pt h876543210l 11-bit transmit register stop start t8 tie tdre tcie sbk tc parity generation msb sci data registers load from scidr shift enable preamble (all 1s) break (all 0s) transmitter control m internal bus sbr12:sbr0 baud divider 16 bus clock te sctxd txpol loops loop rsrc control to receiver transmit collision detect tdre irq tc irq sctxd scrxd (from receiver) tcie berrif ber irq berrm[1:0]
serial communication interface (s12sciv5) s12xs family reference manual, rev. 1.10 418 freescale semiconductor the sci also sets a ?g, the transmit data register empty ?g (tdre), every time it transfers data from the buffer (scidrh/l) to the transmitter shift register.the transmit driver routine may respond to this ?g by writing another byte to the transmitter buffer (scidrh/scidrl), while the shift register is still shifting out the ?st byte. to initiate an sci transmission: 1. con?ure the sci: a) select a baud rate. write this value to the sci baud registers (scibdh/l) to begin the baud rate generator. remember that the baud rate generator is disabled when the baud rate is zero. writing to the scibdh has no effect without also writing to scibdl. b) write to scicr1 to con?ure word length, parity, and other con?uration bits (loops,rsrc,m,wake,ilt,pe,pt). c) enable the transmitter, interrupts, receive, and wake up as required, by writing to the scicr2 register bits (tie,tcie,rie,ilie,te,re,rwu,sbk). a preamble or idle character will now be shifted out of the transmitter shift register. 2. transmit procedure for each byte: a) poll the tdre ?g by reading the scisr1 or responding to the tdre interrupt. keep in mind that the tdre bit resets to one. b) if the tdre ?g is set, write the data to be transmitted to scidrh/l, where the ninth bit is written to the t8 bit in scidrh if the sci is in 9-bit data format. a new transmission will not result until the tdre ?g has been cleared. 3. repeat step 2 for each subsequent transmission. note the tdre ?g is set when the shift register is loaded with the next data to be transmitted from scidrh/l, which happens, generally speaking, a little over half-way through the stop bit of the previous frame. speci?ally, this transfer occurs 9/16ths of a bit time after the start of the stop bit of the previous frame. writing the te bit from 0 to a 1 automatically loads the transmit shift register with a preamble of 10 logic 1s (if m = 0) or 11 logic 1s (if m = 1). after the preamble shifts out, control logic transfers the data from the sci data register into the transmit shift register. a logic 0 start bit automatically goes into the least signi?ant bit position of the transmit shift register. a logic 1 stop bit goes into the most signi?ant bit position. hardware supports odd or even parity. when parity is enabled, the most signi?ant bit (msb) of the data character is the parity bit. the transmit data register empty ?g, tdre, in sci status register 1 (scisr1) becomes set when the sci data register transfers a byte to the transmit shift register. the tdre ?g indicates that the sci data register can accept new data from the internal data bus. if the transmit interrupt enable bit, tie, in sci control register 2 (scicr2) is also set, the tdre ?g generates a transmitter interrupt request.
serial communication interface (s12sciv5) s12xs family reference manual, rev. 1.10 freescale semiconductor 419 when the transmit shift register is not transmitting a frame, the txd pin goes to the idle condition, logic 1. if at any time software clears the te bit in sci control register 2 (scicr2), the transmitter enable signal goes low and the transmit signal goes idle. if software clears te while a transmission is in progress (tc = 0), the frame in the transmit shift register continues to shift out. to avoid accidentally cutting off the last frame in a message, always wait for tdre to go high after the last frame before clearing te. to separate messages with preambles with minimum idle line time, use this sequence between messages: 1. write the last byte of the ?st message to scidrh/l. 2. wait for the tdre ?g to go high, indicating the transfer of the last frame to the transmit shift register. 3. queue a preamble by clearing and then setting the te bit. 4. write the ?st byte of the second message to scidrh/l. 14.4.5.3 break characters writing a logic 1 to the send break bit, sbk, in sci control register 2 (scicr2) loads the transmit shift register with a break character. a break character contains all logic 0s and has no start, stop, or parity bit. break character length depends on the m bit in sci control register 1 (scicr1). as long as sbk is at logic 1, transmitter logic continuously loads break characters into the transmit shift register. after software clears the sbk bit, the shift register ?ishes transmitting the last break character and then transmits at least one logic 1. the automatic logic 1 at the end of a break character guarantees the recognition of the start bit of the next frame. the sci recognizes a break character when there are 10 or 11(m = 0 or m = 1) consecutive zero received. depending if the break detect feature is enabled or not receiving a break character has these effects on sci registers. if the break detect feature is disabled (bkdfe = 0): sets the framing error flag, fe sets the receive data register full flag, rdrf clears the sci data registers (scidrh/l) may set the overrun flag, or, noise flag, nf, parity error flag, pe, or the receiver active flag, raf (see 3.4.4 and 3.4.5 sci status register 1 and 2) if the break detect feature is enabled (bkdfe = 1) there are two scenarios 1 the break is detected right from a start bit or is detected during a byte reception. sets the break detect interrupt flag, bldif does not change the data register full flag, rdrf or overrun flag or does not change the framing error flag fe, parity error flag pe. does not clear the sci data registers (scidrh/l) may set noise flag nf, or receiver active flag raf. 1. a break character in this context are either 10 or 11 consecutive zero received bits
serial communication interface (s12sciv5) s12xs family reference manual, rev. 1.10 420 freescale semiconductor figure 14-17 shows two cases of break detect. in trace rxd_1 the break symbol starts with the start bit, while in rxd_2 the break starts in the middle of a transmission. if brkdfe = 1, in rxd_1 case there will be no byte transferred to the receive buffer and the rdrf ?g will not be modi?d. also no framing error or parity error will be ?gged from this transfer. in rxd_2 case, however the break signal starts later during the transmission. at the expected stop bit position the byte received so far will be transferred to the receive buffer, the receive data register full ?g will be set, a framing error and if enabled and appropriate a parity error will be set. once the break is detected the brkdif ?g will be set. figure 14-17. break detection if brkdfe = 1 (m = 0) 14.4.5.4 idle characters an idle character (or preamble) contains all logic 1s and has no start, stop, or parity bit. idle character length depends on the m bit in sci control register 1 (scicr1). the preamble is a synchronizing idle character that begins the ?st transmission initiated after writing the te bit from 0 to 1. if the te bit is cleared during a transmission, the txd pin becomes idle after completion of the transmission in progress. clearing and then setting the te bit during a transmission queues an idle character to be sent after the frame currently being transmitted. note when queueing an idle character, return the te bit to logic 1 before the stop bit of the current frame shifts out through the txd pin. setting te after the stop bit appears on txd causes data previously written to the sci data register to be lost. toggle the te bit for a queued idle character while the tdre ?g is set and immediately before writing the next byte to the sci data register. if the te bit is clear and the transmission is complete, the sci is not the master of the txd pin start bit position stop bit position brkdif = 1 fe = 1 brkdif = 1 rxd_1 rxd_2 1 23 4567 8 910 1 23 4567 8 910 zero bit counter zero bit counter . . . . . .
serial communication interface (s12sciv5) s12xs family reference manual, rev. 1.10 freescale semiconductor 421 14.4.5.5 lin transmit collision detection this module allows to check for collisions on the lin bus. figure 14-18. collision detect principle if the bit error circuit is enabled (berrm[1:0] = 0:1 or = 1:0]), the error detect circuit will compare the transmitted and the received data stream at a point in time and ?g any mismatch. the timing checks run when transmitter is active (not idle). as soon as a mismatch between the transmitted data and the received data is detected the following happens: the next bit transmitted will have a high level (txpol = 0) or low level (txpol = 1) the transmission is aborted and the byte in transmit buffer is discarded. the transmit data register empty and the transmission complete flag will be set the bit error interrupt flag, berrif, will be set. no further transmissions will take place until the berrif is cleared. figure 14-19. timing diagram bit error detection if the bit error detect feature is disabled, the bit error interrupt ?g is cleared. note the rxpol and txpol bit should be set the same when transmission collision detect feature is enabled, otherwise the bit error interrupt ?g may be set incorrectly. txd pin rxd pin lin physical interface synchronizer stage bus clock receive shift register transmit shift register lin bus compare sample bit error point output transmit shift register 01234567891011121314150 input receive shift register berrm[1:0] = 0:1 berrm[1:0] = 1:1 compare sample points sampling begin sampling begin sampling end sampling end
serial communication interface (s12sciv5) s12xs family reference manual, rev. 1.10 422 freescale semiconductor 14.4.6 receiver figure 14-20. sci receiver block diagram 14.4.6.1 receiver character length the sci receiver can accommodate either 8-bit or 9-bit data characters. the state of the m bit in sci control register 1 (scicr1) determines the length of data characters. when receiving 9-bit data, bit r8 in sci data register high (scidrh) is the ninth bit (bit 8). 14.4.6.2 character reception during an sci reception, the receive shift register shifts a frame in from the rxd pin. the sci data register is the read-only buffer between the internal data bus and the receive shift register. after a complete frame shifts into the receive shift register, the data portion of the frame transfers to the sci data register. the receive data register full ?g, rdrf, in sci status register 1 (scisr1) becomes set, all 1s m wake ilt pe pt re h876543210l 11-bit receive shift register stop start data wakeup parity checking msb sci data register r8 ilie rwu rdrf or nf fe pe internal bus bus sbr12:sbr0 baud divider clock idle raf recovery logic rxpol loops loop rsrc control scrxd from txd pin or transmitter idle irq rdrf/or irq break detect logic active edge detect logic brkdfe brkdie brkdif rxedgie rxedgif break irq rx active edge irq rie
serial communication interface (s12sciv5) s12xs family reference manual, rev. 1.10 freescale semiconductor 423 indicating that the received byte can be read. if the receive interrupt enable bit, rie, in sci control register 2 (scicr2) is also set, the rdrf ?g generates an rdrf interrupt request. 14.4.6.3 data sampling the rt clock rate. the rt clock is an internal signal with a frequency 16 times the baud rate. to adjust for baud rate mismatch, the rt clock (see figure 14-21 ) is re-synchronized: after every start bit after the receiver detects a data bit change from logic 1 to logic 0 (after the majority of data bit samples at rt8, rt9, and rt10 returns a valid logic 1 and the majority of the next rt8, rt9, and rt10 samples returns a valid logic 0) to locate the start bit, data recovery logic does an asynchronous search for a logic 0 preceded by three logic 1s.when the falling edge of a possible start bit occurs, the rt clock begins to count to 16. figure 14-21. receiver data sampling to verify the start bit and to detect noise, data recovery logic takes samples at rt3, rt5, and rt7. figure 14-17 summarizes the results of the start bit veri?ation samples. if start bit veri?ation is not successful, the rt clock is reset and a new search for a start bit begins. table 14-17. start bit veri?ation rt3, rt5, and rt7 samples start bit veri?ation noise flag 000 yes 0 001 yes 1 010 yes 1 011 no 0 100 yes 1 101 no 0 110 no 0 111 no 0 reset rt clock rt1 rt1 rt1 rt1 rt1 rt1 rt1 rt1 rt1 rt2 rt3 rt4 rt5 rt8 rt7 rt6 rt11 rt10 rt9 rt15 rt14 rt13 rt12 rt16 rt1 rt2 rt3 rt4 samples rt clock rt clock count start bit rxd start bit quali?ation start bit data sampling 11 1 1 1 1 110000 0 00 lsb veri?ation
serial communication interface (s12sciv5) s12xs family reference manual, rev. 1.10 424 freescale semiconductor to determine the value of a data bit and to detect noise, recovery logic takes samples at rt8, rt9, and rt10. table 14-18 summarizes the results of the data bit samples. note the rt8, rt9, and rt10 samples do not affect start bit veri?ation. if any or all of the rt8, rt9, and rt10 start bit samples are logic 1s following a successful start bit veri?ation, the noise ?g (nf) is set and the receiver assumes that the bit is a start bit (logic 0). to verify a stop bit and to detect noise, recovery logic takes samples at rt8, rt9, and rt10. table 14-19 summarizes the results of the stop bit samples. table 14-18. data bit recovery rt8, rt9, and rt10 samples data bit determination noise flag 000 0 0 001 0 1 010 0 1 011 1 1 100 0 1 101 1 1 110 1 1 111 1 0 table 14-19. stop bit recovery rt8, rt9, and rt10 samples framing error flag noise flag 000 1 0 001 1 1 010 1 1 011 0 1 100 1 1 101 0 1 110 0 1 111 0 0
serial communication interface (s12sciv5) s12xs family reference manual, rev. 1.10 freescale semiconductor 425 in figure 14-22 the veri?ation samples rt3 and rt5 determine that the ?st low detected was noise and not the beginning of a start bit. the rt clock is reset and the start bit search begins again. the noise ?g is not set because the noise occurred before the start bit was found. figure 14-22. start bit search example 1 in figure 14-23 , veri?ation sample at rt3 is high. the rt3 sample sets the noise ?g. although the perceived bit time is misaligned, the data samples rt8, rt9, and rt10 are within the bit time and data recovery is successful. figure 14-23. start bit search example 2 reset rt clock rt1 rt1 rt1 rt1 rt2 rt3 rt4 rt5 rt1 rt1 rt2 rt3 rt4 rt7 rt6 rt5 rt10 rt9 rt8 rt14 rt13 rt12 rt11 rt15 rt16 rt1 rt2 rt3 samples rt clock rt clock count start bit rxd 11 0 1 111000 00 lsb 0 0 reset rt clock rt1 rt1 rt1 rt1 rt1 rt1 rt2 rt3 rt4 rt5 rt6 rt7 rt8 rt11 rt10 rt9 rt14 rt13 rt12 rt2 rt1 rt16 rt15 rt3 rt4 rt5 rt6 rt7 samples rt clock rt clock count actual start bit rxd 11 1 1 11000 0 lsb 0 0 perceived start bit
serial communication interface (s12sciv5) s12xs family reference manual, rev. 1.10 426 freescale semiconductor in figure 14-24 , a large burst of noise is perceived as the beginning of a start bit, although the test sample at rt5 is high. the rt5 sample sets the noise ?g. although this is a worst-case misalignment of perceived bit time, the data samples rt8, rt9, and rt10 are within the bit time and data recovery is successful. figure 14-24. start bit search example 3 figure 14-25 shows the effect of noise early in the start bit time. although this noise does not affect proper synchronization with the start bit time, it does set the noise ?g. figure 14-25. start bit search example 4 reset rt clock rt1 rt1 rt1 rt1 rt2 rt3 rt4 rt5 rt6 rt7 rt8 rt9 rt10 rt13 rt12 rt11 rt16 rt15 rt14 rt4 rt3 rt2 rt1 rt5 rt6 rt7 rt8 rt9 samples rt clock rt clock count actual start bit rxd 10 1 11000 0 lsb 0 perceived start bit reset rt clock rt1 rt1 rt1 rt1 rt1 rt1 rt1 rt1 rt1 rt1 rt2 rt3 rt4 rt7 rt6 rt5 rt10 rt9 rt8 rt14 rt13 rt12 rt11 rt15 rt16 rt1 rt2 rt3 samples rt clock rt clock count perceived and actual start bit rxd 11 1 1100 1 lsb 1 1 1 1
serial communication interface (s12sciv5) s12xs family reference manual, rev. 1.10 freescale semiconductor 427 figure 14-26 shows a burst of noise near the beginning of the start bit that resets the rt clock. the sample after the reset is low but is not preceded by three high samples that would qualify as a falling edge. depending on the timing of the start bit search and on the data, the frame may be missed entirely or it may set the framing error ?g. figure 14-26. start bit search example 5 in figure 14-27 , a noise burst makes the majority of data samples rt8, rt9, and rt10 high. this sets the noise ?g but does not reset the rt clock. in start bits only, the rt8, rt9, and rt10 data samples are ignored. figure 14-27. start bit search example 6 14.4.6.4 framing errors if the data recovery logic does not detect a logic 1 where the stop bit should be in an incoming frame, it sets the framing error ?g, fe, in sci status register 1 (scisr1). a break character also sets the fe ?g because a break character has no stop bit. the fe ?g is set at the same time that the rdrf ?g is set. reset rt clock rt1 rt1 rt1 rt1 rt1 rt1 rt1 rt1 rt1 rt1 rt2 rt3 rt4 rt7 rt6 rt5 rt1 rt1 rt1 rt1 rt1 rt1 rt1 rt1 rt1 rt1 rt1 rt1 samples rt clock rt clock count start bit rxd 11 1 1101 0 lsb 1 1 1 1 1 00 0 00 0 0 0 no start bit found reset rt clock rt1 rt1 rt1 rt1 rt1 rt1 rt1 rt1 rt1 rt1 rt2 rt3 rt4 rt7 rt6 rt5 rt10 rt9 rt8 rt14 rt13 rt12 rt11 rt15 rt16 rt1 rt2 rt3 samples rt clock rt clock count start bit rxd 11 1 1100 0 lsb 1 1 1 1 0 11 0
serial communication interface (s12sciv5) s12xs family reference manual, rev. 1.10 428 freescale semiconductor 14.4.6.5 baud rate tolerance a transmitting device may be operating at a baud rate below or above the receiver baud rate. accumulated bit time misalignment can cause one of the three stop bit data samples (rt8, rt9, and rt10) to fall outside the actual stop bit. a noise error will occur if the rt8, rt9, and rt10 samples are not all the same logical values. a framing error will occur if the receiver clock is misaligned in such a way that the majority of the rt8, rt9, and rt10 stop bit samples are a logic zero. as the receiver samples an incoming frame, it re-synchronizes the rt clock on any valid falling edge within the frame. re synchronization within frames will correct a misalignment between transmitter bit times and receiver bit times. 14.4.6.5.1 slow data tolerance figure 14-28 shows how much a slow received frame can be misaligned without causing a noise error or a framing error. the slow stop bit begins at rt8 instead of rt1 but arrives in time for the stop bit data samples at rt8, rt9, and rt10. figure 14-28. slow data lets take rtr as receiver rt clock and rtt as transmitter rt clock. for an 8-bit data character, it takes the receiver 9 bit times x 16 rtr cycles +7 rtr cycles = 151 rtr cycles to start data sampling of the stop bit. with the misaligned character shown in figure 14-28 , the receiver counts 151 rtr cycles at the point when the count of the transmitting device is 9 bit times x 16 rtt cycles = 144 rtt cycles. the maximum percent difference between the receiver count and the transmitter count of a slow 8-bit data character with no errors is: ((151 ?144) / 151) x 100 = 4.63% for a 9-bit data character, it takes the receiver 10 bit times x 16 rtr cycles + 7 rtr cycles = 167 rtr cycles to start data sampling of the stop bit. with the misaligned character shown in figure 14-28 , the receiver counts 167 rtr cycles at the point when the count of the transmitting device is 10 bit times x 16 rtt cycles = 160 rtt cycles. the maximum percent difference between the receiver count and the transmitter count of a slow 9-bit character with no errors is: ((167 ?160) / 167) x 100 = 4.19% msb stop rt1 rt2 rt3 rt4 rt5 rt6 rt7 rt8 rt9 rt10 rt11 rt12 rt13 rt14 rt15 rt16 data samples receiver rt clock
serial communication interface (s12sciv5) s12xs family reference manual, rev. 1.10 freescale semiconductor 429 14.4.6.5.2 fast data tolerance figure 14-29 shows how much a fast received frame can be misaligned. the fast stop bit ends at rt10 instead of rt16 but is still sampled at rt8, rt9, and rt10. figure 14-29. fast data for an 8-bit data character, it takes the receiver 9 bit times x 16 rtr cycles + 10 rtr cycles = 154 rtr cycles to ?ish data sampling of the stop bit. with the misaligned character shown in figure 14-29 , the receiver counts 154 rtr cycles at the point when the count of the transmitting device is 10 bit times x 16 rtt cycles = 160 rtt cycles. the maximum percent difference between the receiver count and the transmitter count of a fast 8-bit character with no errors is: ((160 ?154) / 160) x 100 = 3.75% for a 9-bit data character, it takes the receiver 10 bit times x 16 rtr cycles + 10 rtr cycles = 170 rtr cycles to ?ish data sampling of the stop bit. with the misaligned character shown in figure 14-29 , the receiver counts 170 rtr cycles at the point when the count of the transmitting device is 11 bit times x 16 rtt cycles = 176 rtt cycles. the maximum percent difference between the receiver count and the transmitter count of a fast 9-bit character with no errors is: ((176 ?170) /176) x 100 = 3.40% 14.4.6.6 receiver wakeup to enable the sci to ignore transmissions intended only for other receivers in multiple-receiver systems, the receiver can be put into a standby state. setting the receiver wakeup bit, rwu, in sci control register 2 (scicr2) puts the receiver into standby state during which receiver interrupts are disabled.the sci will still load the receive data into the scidrh/l registers, but it will not set the rdrf ?g. the transmitting device can address messages to selected receivers by including addressing information in the initial frame or frames of each message. the wake bit in sci control register 1 (scicr1) determines how the sci is brought out of the standby state to process an incoming message. the wake bit enables either idle line wakeup or address mark wakeup. idle or next frame stop rt1 rt2 rt3 rt4 rt5 rt6 rt7 rt8 rt9 rt10 rt11 rt12 rt13 rt14 rt15 rt16 data samples receiver rt clock
serial communication interface (s12sciv5) s12xs family reference manual, rev. 1.10 430 freescale semiconductor 14.4.6.6.1 idle input line wakeup (wake = 0) in this wakeup method, an idle condition on the rxd pin clears the rwu bit and wakes up the sci. the initial frame or frames of every message contain addressing information. all receivers evaluate the addressing information, and receivers for which the message is addressed process the frames that follow. any receiver for which a message is not addressed can set its rwu bit and return to the standby state. the rwu bit remains set and the receiver remains on standby until another idle character appears on the rxd pin. idle line wakeup requires that messages be separated by at least one idle character and that no message contains idle characters. the idle character that wakes a receiver does not set the receiver idle bit, idle, or the receive data register full ?g, rdrf. the idle line type bit, ilt, determines whether the receiver begins counting logic 1s as idle character bits after the start bit or after the stop bit. ilt is in sci control register 1 (scicr1). 14.4.6.6.2 address mark wakeup (wake = 1) in this wakeup method, a logic 1 in the most signi?ant bit (msb) position of a frame clears the rwu bit and wakes up the sci. the logic 1 in the msb position marks a frame as an address frame that contains addressing information. all receivers evaluate the addressing information, and the receivers for which the message is addressed process the frames that follow.any receiver for which a message is not addressed can set its rwu bit and return to the standby state. the rwu bit remains set and the receiver remains on standby until another address frame appears on the rxd pin. the logic 1 msb of an address frame clears the receivers rwu bit before the stop bit is received and sets the rdrf ?g. address mark wakeup allows messages to contain idle characters but requires that the msb be reserved for use in address frames. note with the wake bit clear, setting the rwu bit after the rxd pin has been idle can cause the receiver to wake up immediately. 14.4.7 single-wire operation normally, the sci uses two pins for transmitting and receiving. in single-wire operation, the rxd pin is disconnected from the sci. the sci uses the txd pin for both receiving and transmitting. figure 14-30. single-wire operation (loops = 1, rsrc = 1) rxd transmitter receiver txd
serial communication interface (s12sciv5) s12xs family reference manual, rev. 1.10 freescale semiconductor 431 enable single-wire operation by setting the loops bit and the receiver source bit, rsrc, in sci control register 1 (scicr1). setting the loops bit disables the path from the rxd pin to the receiver. setting the rsrc bit connects the txd pin to the receiver. both the transmitter and receiver must be enabled (te = 1 and re = 1).the txdir bit (scisr2[1]) determines whether the txd pin is going to be used as an input (txdir = 0) or an output (txdir = 1) in this mode of operation. note in single-wire operation data from the txd pin is inverted if rxpol is set. 14.4.8 loop operation in loop operation the transmitter output goes to the receiver input. the rxd pin is disconnected from the sci. figure 14-31. loop operation (loops = 1, rsrc = 0) enable loop operation by setting the loops bit and clearing the rsrc bit in sci control register 1 (scicr1). setting the loops bit disables the path from the rxd pin to the receiver. clearing the rsrc bit connects the transmitter output to the receiver input. both the transmitter and receiver must be enabled (te = 1 and re = 1). note in loop operation data from the transmitter is not recognized by the receiver if rxpol and txpol are not the same. 14.5 initialization/application information 14.5.1 reset initialization see section 14.3.2, ?egister descriptions . 14.5.2 modes of operation 14.5.2.1 run mode normal mode of operation. to initialize a sci transmission, see section 14.4.5.2, ?haracter transmission . rxd transmitter receiver txd
serial communication interface (s12sciv5) s12xs family reference manual, rev. 1.10 432 freescale semiconductor 14.5.2.2 wait mode sci operation in wait mode depends on the state of the sciswai bit in the sci control register 1 (scicr1). if sciswai is clear, the sci operates normally when the cpu is in wait mode. if sciswai is set, sci clock generation ceases and the sci module enters a power-conservation state when the cpu is in wait mode. setting sciswai does not affect the state of the receiver enable bit, re, or the transmitter enable bit, te. if sciswai is set, any transmission or reception in progress stops at wait mode entry. the transmission or reception resumes when either an internal or external interrupt brings the cpu out of wait mode. exiting wait mode by reset aborts any transmission or reception in progress and resets the sci. 14.5.2.3 stop mode the sci is inactive during stop mode for reduced power consumption. the stop instruction does not affect the sci register states, but the sci bus clock will be disabled. the sci operation resumes from where it left off after an external interrupt brings the cpu out of stop mode. exiting stop mode by reset aborts any transmission or reception in progress and resets the sci. the receive input active edge detect circuit is still active in stop mode. an active edge on the receive input can be used to bring the cpu out of stop mode. 14.5.3 interrupt operation this section describes the interrupt originated by the sci block.the mcu must service the interrupt requests. table 14-20 lists the eight interrupt sources of the sci. table 14-20. sci interrupt sources interrupt source local enable description tdre scisr1[7] tie active high level. indicates that a byte was transferred from scidrh/l to the transmit shift register. tc scisr1[6] tcie active high level. indicates that a transmit is complete. rdrf scisr1[5] rie active high level. the rdrf interrupt indicates that received data is available in the sci data register. or scisr1[3] active high level. this interrupt indicates that an overrun condition has occurred. idle scisr1[4] ilie active high level. indicates that receiver input has become idle. rxedgif sciasr1[7] rxedgie active high level. indicates that an active edge (falling for rxpol = 0, rising for rxpol = 1) was detected. berrif sciasr1[1] berrie active high level. indicates that a mismatch between transmitted and received data in a single wire application has happened. bkdif sciasr1[0] brkdie active high level. indicates that a break character has been received.
serial communication interface (s12sciv5) s12xs family reference manual, rev. 1.10 freescale semiconductor 433 14.5.3.1 description of interrupt operation the sci only originates interrupt requests. the following is a description of how the sci makes a request and how the mcu should acknowledge that request. the interrupt vector offset and interrupt number are chip dependent. the sci only has a single interrupt line (sci interrupt signal, active high operation) and all the following interrupts, when generated, are ored together and issued through that port. 14.5.3.1.1 tdre description the tdre interrupt is set high by the sci when the transmit shift register receives a byte from the sci data register. a tdre interrupt indicates that the transmit data register (scidrh/l) is empty and that a new byte can be written to the scidrh/l for transmission.clear tdre by reading sci status register 1 with tdre set and then writing to sci data register low (scidrl). 14.5.3.1.2 tc description the tc interrupt is set by the sci when a transmission has been completed. transmission is completed when all bits including the stop bit (if transmitted) have been shifted out and no data is queued to be transmitted. no stop bit is transmitted when sending a break character and the tc ?g is set (providing there is no more data queued for transmission) when the break character has been shifted out. a tc interrupt indicates that there is no transmission in progress. tc is set high when the tdre ?g is set and no data, preamble, or break character is being transmitted. when tc is set, the txd pin becomes idle (logic 1). clear tc by reading sci status register 1 (scisr1) with tc set and then writing to sci data register low (scidrl).tc is cleared automatically when data, preamble, or break is queued and ready to be sent. 14.5.3.1.3 rdrf description the rdrf interrupt is set when the data in the receive shift register transfers to the sci data register. a rdrf interrupt indicates that the received data has been transferred to the sci data register and that the byte can now be read by the mcu. the rdrf interrupt is cleared by reading the sci status register one (scisr1) and then reading sci data register low (scidrl). 14.5.3.1.4 or description the or interrupt is set when software fails to read the sci data register before the receive shift register receives the next frame. the newly acquired data in the shift register will be lost in this case, but the data already in the sci data registers is not affected. the or interrupt is cleared by reading the sci status register one (scisr1) and then reading sci data register low (scidrl). 14.5.3.1.5 idle description the idle interrupt is set when 10 consecutive logic 1s (if m = 0) or 11 consecutive logic 1s (if m = 1) appear on the receiver input. once the idle is cleared, a valid frame must again set the rdrf ?g before an idle condition can set the idle ?g. clear idle by reading sci status register 1 (scisr1) with idle set and then reading sci data register low (scidrl).
serial communication interface (s12sciv5) s12xs family reference manual, rev. 1.10 434 freescale semiconductor 14.5.3.1.6 rxedgif description the rxedgif interrupt is set when an active edge (falling if rxpol = 0, rising if rxpol = 1) on the rxd pin is detected. clear rxedgif by writing a ??to the sciasr1 sci alternative status register 1. 14.5.3.1.7 berrif description the berrif interrupt is set when a mismatch between the transmitted and the received data in a single wire application like lin was detected. clear berrif by writing a ??to the sciasr1 sci alternative status register 1. this ?g is also cleared if the bit error detect feature is disabled. 14.5.3.1.8 bkdif description the bkdif interrupt is set when a break signal was received. clear bkdif by writing a ??to the sciasr1 sci alternative status register 1. this ?g is also cleared if break detect feature is disabled. 14.5.4 recovery from wait mode the sci interrupt request can be used to bring the cpu out of wait mode. 14.5.5 recovery from stop mode an active edge on the receive input can be used to bring the cpu out of stop mode.
s12xs family reference manual, rev. 1.10 freescale semiconductor 435 chapter 15 serial peripheral interface (s12spiv5) 15.1 introduction the spi module allows a duplex, synchronous, serial communication between the mcu and peripheral devices. software can poll the spi status ?gs or the spi operation can be interrupt driven. 15.1.1 glossary of terms 15.1.2 features the spi includes these distinctive features: master mode and slave mode selectable 8 or 16-bit transfer width bidirectional mode slave select output mode fault error ?g with cpu interrupt capability double-buffered data register serial clock with programmable polarity and phase control of spi operation during wait mode 15.1.3 modes of operation the spi functions in three modes: run, wait, and stop. table 15-1. revision history revision number revision date sections affected description of changes v05.00 24 mar 2005 15.3.2/15-439 - added 16-bit transfer width feature. spi serial peripheral interface ss slave select sck serial clock mosi master output, slave input miso master input, slave output momi master output, master input siso slave input, slave output
serial peripheral interface (s12spiv5) s12xs family reference manual, rev. 1.10 436 freescale semiconductor run mode this is the basic mode of operation. wait mode spi operation in wait mode is a con?urable low power mode, controlled by the spiswai bit located in the spicr2 register. in wait mode, if the spiswai bit is clear, the spi operates like in run mode. if the spiswai bit is set, the spi goes into a power conservative state, with the spi clock generation turned off. if the spi is con?ured as a master, any transmission in progress stops, but is resumed after cpu goes into run mode. if the spi is con?ured as a slave, reception and transmission of data continues, so that the slave stays synchronized to the master. stop mode the spi is inactive in stop mode for reduced power consumption. if the spi is con?ured as a master, any transmission in progress stops, but is resumed after cpu goes into run mode. if the spi is con?ured as a slave, reception and transmission of data continues, so that the slave stays synchronized to the master. for a detailed description of operating modes, please refer to section 15.4.7, ?ow power mode options . 15.1.4 block diagram figure 15-1 gives an overview on the spi architecture. the main parts of the spi are status, control and data registers, shifter logic, baud rate generator, master/slave control logic, and port control logic.
serial peripheral interface (s12spiv5) s12xs family reference manual, rev. 1.10 freescale semiconductor 437 figure 15-1. spi block diagram 15.2 external signal description this section lists the name and description of all ports including inputs and outputs that do, or may, connect off chip. the spi module has a total of four external pins. 15.2.1 mosi ?master out/slave in pin this pin is used to transmit data out of the spi module when it is con?ured as a master and receive data when it is con?ured as slave. 15.2.2 miso ?master in/slave out pin this pin is used to transmit data out of the spi module when it is con?ured as a slave and receive data when it is con?ured as master. spi control register 1 spi control register 2 spi baud rate register spi status register spi data register shifter port control logic mosi sck interrupt control spi msb lsb lsbfe=1 lsbfe=0 lsbfe=0 lsbfe=1 data in lsbfe=1 lsbfe=0 data out baud rate generator prescaler bus clock counter clock select sppr 3 3 spr baud rate phase + polarity control master slave sck in sck out master baud rate slave baud rate phase + polarity control control control cpol cpha 2 bidiroe spc0 2 shift sample clock clock modf spif sptef spi request interrupt ss
serial peripheral interface (s12spiv5) s12xs family reference manual, rev. 1.10 438 freescale semiconductor 15.2.3 ss ?slave select pin this pin is used to output the select signal from the spi module to another peripheral with which a data transfer is to take place when it is con?ured as a master and it is used as an input to receive the slave select signal when the spi is con?ured as slave. 15.2.4 sck ?serial clock pin in master mode, this is the synchronous output clock. in slave mode, this is the synchronous input clock. 15.3 memory map and register de?ition this section provides a detailed description of address space and registers used by the spi. 15.3.1 module memory map the memory map for the spi is given in figure 15-2 . the address listed for each register is the sum of a base address and an address offset. the base address is de?ed at the soc level and the address offset is de?ed at the module level. reads from the reserved bits return zeros and writes to the reserved bits have no effect. register name bit 7 6 5 4 3 2 1 bit 0 0x0000 spicr1 r spie spe sptie mstr cpol cpha ssoe lsbfe w 0x0001 spicr2 r0 xfrw 0 modfen bidiroe 0 spiswai spc0 w 0x0002 spibr r0 sppr2 sppr1 sppr0 0 spr2 spr1 spr0 w 0x0003 spisr r spif 0 sptef modf 0 0 0 0 w 0x0004 spidrh r r15 r14 r13 r12 r11 r10 r9 r8 t15 t14 t13 t12 t11 t10 t9 t8 w 0x0005 spidrl rr7r6r5r4r3r2r1r0 t7 t6 t5 t4 t3 t2 t1 t0 w 0x0006 reserved r w 0x0007 reserved r w = unimplemented or reserved figure 15-2. spi register summary
serial peripheral interface (s12spiv5) s12xs family reference manual, rev. 1.10 freescale semiconductor 439 15.3.2 register descriptions this section consists of register descriptions in address order. each description includes a standard register diagram with an associated ?ure number. details of register bit and ?ld function follow the register diagrams, in bit order. 15.3.2.1 spi control register 1 (spicr1) read: anytime write: anytime module base +0x0000 76543210 r spie spe sptie mstr cpol cpha ssoe lsbfe w reset 0 0 0 00100 figure 15-3. spi control register 1 (spicr1) table 15-2. spicr1 field descriptions field description 7 spie spi interrupt enable bit ?this bit enables spi interrupt requests, if spif or modf status ?g is set. 0 spi interrupts disabled. 1 spi interrupts enabled. 6 spe spi system enable bit ?this bit enables the spi system and dedicates the spi port pins to spi system functions. if spe is cleared, spi is disabled and forced into idle state, status bits in spisr register are reset. 0 spi disabled (lower power consumption). 1 spi enabled, port pins are dedicated to spi functions. 5 sptie spi transmit interrupt enable ?this bit enables spi interrupt requests, if sptef ?g is set. 0 sptef interrupt disabled. 1 sptef interrupt enabled. 4 mstr spi master/slave mode select bit ?this bit selects whether the spi operates in master or slave mode. switching the spi from master to slave or vice versa forces the spi system into idle state. 0 spi is in slave mode. 1 spi is in master mode. 3 cpol spi clock polarity bit this bit selects an inverted or non-inverted spi clock. to transmit data between spi modules, the spi modules must have identical cpol values. in master mode, a change of this bit will abort a transmission in progress and force the spi system into idle state. 0 active-high clocks selected. in idle state sck is low. 1 active-low clocks selected. in idle state sck is high. 2 cpha spi clock phase bit this bit is used to select the spi clock format. in master mode, a change of this bit will abort a transmission in progress and force the spi system into idle state. 0 sampling of data occurs at odd edges (1,3,5,...) of the sck clock. 1 sampling of data occurs at even edges (2,4,6,...) of the sck clock.
serial peripheral interface (s12spiv5) s12xs family reference manual, rev. 1.10 440 freescale semiconductor 15.3.2.2 spi control register 2 (spicr2) read: anytime write: anytime; writes to the reserved bits have no effect 1 ssoe slave select output enable ?the ss output feature is enabled only in master mode, if modfen is set, by asserting the ssoe as shown in table 15-3 . in master mode, a change of this bit will abort a transmission in progress and force the spi system into idle state. 0 lsbfe lsb-first enable ?this bit does not affect the position of the msb and lsb in the data register. reads and writes of the data register always have the msb in the highest bit position. in master mode, a change of this bit will abort a transmission in progress and force the spi system into idle state. 0 data is transferred most signi?ant bit ?st. 1 data is transferred least signi?ant bit ?st. table 15-3. ss input / output selection modfen ssoe master mode slave mode 00 ss not used by spi ss input 01 ss not used by spi ss input 10 ss input with modf feature ss input 11 ss is slave select output ss input module base +0x0001 76543210 r0 xfrw 0 modfen bidiroe 0 spiswai spc0 w reset 0 0 0 00000 = unimplemented or reserved figure 15-4. spi control register 2 (spicr2) table 15-2. spicr1 field descriptions (continued) field description
serial peripheral interface (s12spiv5) s12xs family reference manual, rev. 1.10 freescale semiconductor 441 table 15-4. spicr2 field descriptions field description 6 xfrw transfer width this bit is used for selecting the data transfer width. if 8-bit transfer width is selected, spidrl becomes the dedicated data register and spidrh is unused. if 16-bit transfer width is selected, spidrh and spidrl form a 16-bit data register. please refer to section 15.3.2.4, ?pi status register (spisr) for information about transmit/receive data handling and the interrupt ?g clearing mechanism. in master mode, a change of this bit will abort a transmission in progress and force the spi system into idle state. 0 8-bit transfer width (n = 8) 1 1 16-bit transfer width (n = 16) 1 1 n is used later in this document as a placeholder for the selected transfer width. 4 modfen mode fault enable bit ?this bit allows the modf failure to be detected. if the spi is in master mode and modfen is cleared, then the ss port pin is not used by the spi. in slave mode, the ss is available only as an input regardless of the value of modfen. for an overview on the impact of the modfen bit on the ss port pin con?uration, refer to table 15-3 . in master mode, a change of this bit will abort a transmission in progress and force the spi system into idle state. 0 ss port pin is not used by the spi. 1 ss port pin with modf feature. 3 bidiroe output enable in the bidirectional mode of operation this bit controls the mosi and miso output buffer of the spi, when in bidirectional mode of operation (spc0 is set). in master mode, this bit controls the output buffer of the mosi port, in slave mode it controls the output buffer of the miso port. in master mode, with spc0 set, a change of this bit will abort a transmission in progress and force the spi into idle state. 0 output buffer disabled. 1 output buffer enabled. 1 spiswai spi stop in wait mode bit ?this bit is used for power conservation while in wait mode. 0 spi clock operates normally in wait mode. 1 stop spi clock generation when in wait mode. 0 spc0 serial pin control bit 0 ?this bit enables bidirectional pin con?urations as shown in table 15-5 . in master mode, a change of this bit will abort a transmission in progress and force the spi system into idle state. table 15-5. bidirectional pin con?urations pin mode spc0 bidiroe miso mosi master mode of operation normal 0 x master in master out bidirectional 1 0 miso not used by spi master in 1 master i/o slave mode of operation normal 0 x slave out slave in bidirectional 1 0 slave in mosi not used by spi 1 slave i/o
serial peripheral interface (s12spiv5) s12xs family reference manual, rev. 1.10 442 freescale semiconductor 15.3.2.3 spi baud rate register (spibr) read: anytime write: anytime; writes to the reserved bits have no effect the baud rate divisor equation is as follows: baudratedivisor = (sppr + 1) ? 2 (spr + 1) eqn. 15-1 the baud rate can be calculated with the following equation: baud rate = busclock / baudratedivisor eqn. 15-2 note for maximum allowed baud rates, please refer to the spi electrical speci?ation in the electricals chapter of this data sheet. module base +0x0002 76543210 r0 sppr2 sppr1 sppr0 0 spr2 spr1 spr0 w reset 0 0 0 00000 = unimplemented or reserved figure 15-5. spi baud rate register (spibr) table 15-6. spibr field descriptions field description 6? sppr[2:0] spi baud rate preselection bits these bits specify the spi baud rates as shown in table 15-7 . in master mode, a change of these bits will abort a transmission in progress and force the spi system into idle state. 2? spr[2:0] spi baud rate selection bits these bits specify the spi baud rates as shown in table 15-7 . in master mode, a change of these bits will abort a transmission in progress and force the spi system into idle state. table 15-7. example spi baud rate selection (25 mhz bus clock) (sheet 1 of 3) sppr2 sppr1 sppr0 spr2 spr1 spr0 baud rate divisor baud rate 0 0 0 0 0 0 2 12.5 mbit/s 0 0 0 0 0 1 4 6.25 mbit/s 0 0 0 0 1 0 8 3.125 mbit/s 0 0 0 0 1 1 16 1.5625 mbit/s 0 0 0 1 0 0 32 781.25 kbit/s 0 0 0 1 0 1 64 390.63 kbit/s 0 0 0 1 1 0 128 195.31 kbit/s 0 0 0 1 1 1 256 97.66 kbit/s 0 0 1 0 0 0 4 6.25 mbit/s 0 0 1 0 0 1 8 3.125 mbit/s 0 0 1 0 1 0 16 1.5625 mbit/s 0 0 1 0 1 1 32 781.25 kbit/s
serial peripheral interface (s12spiv5) s12xs family reference manual, rev. 1.10 freescale semiconductor 443 0 0 1 1 0 0 64 390.63 kbit/s 0 0 1 1 0 1 128 195.31 kbit/s 0 0 1 1 1 0 256 97.66 kbit/s 0 0 1 1 1 1 512 48.83 kbit/s 0 1 0 0 0 0 6 4.16667 mbit/s 0 1 0 0 0 1 12 2.08333 mbit/s 0 1 0 0 1 0 24 1.04167 mbit/s 0 1 0 0 1 1 48 520.83 kbit/s 0 1 0 1 0 0 96 260.42 kbit/s 0 1 0 1 0 1 192 130.21 kbit/s 0 1 0 1 1 0 384 65.10 kbit/s 0 1 0 1 1 1 768 32.55 kbit/s 0 1 1 0 0 0 8 3.125 mbit/s 0 1 1 0 0 1 16 1.5625 mbit/s 0 1 1 0 1 0 32 781.25 kbit/s 0 1 1 0 1 1 64 390.63 kbit/s 0 1 1 1 0 0 128 195.31 kbit/s 0 1 1 1 0 1 256 97.66 kbit/s 0 1 1 1 1 0 512 48.83 kbit/s 0 1 1 1 1 1 1024 24.41 kbit/s 1 0 0 0 0 0 10 2.5 mbit/s 1 0 0 0 0 1 20 1.25 mbit/s 1 0 0 0 1 0 40 625 kbit/s 1 0 0 0 1 1 80 312.5 kbit/s 1 0 0 1 0 0 160 156.25 kbit/s 1 0 0 1 0 1 320 78.13 kbit/s 1 0 0 1 1 0 640 39.06 kbit/s 1 0 0 1 1 1 1280 19.53 kbit/s 1 0 1 0 0 0 12 2.08333 mbit/s 1 0 1 0 0 1 24 1.04167 mbit/s 1 0 1 0 1 0 48 520.83 kbit/s 1 0 1 0 1 1 96 260.42 kbit/s 1 0 1 1 0 0 192 130.21 kbit/s 1 0 1 1 0 1 384 65.10 kbit/s 1 0 1 1 1 0 768 32.55 kbit/s 1 0 1 1 1 1 1536 16.28 kbit/s 1 1 0 0 0 0 14 1.78571 mbit/s 1 1 0 0 0 1 28 892.86 kbit/s 1 1 0 0 1 0 56 446.43 kbit/s 1 1 0 0 1 1 112 223.21 kbit/s 1 1 0 1 0 0 224 111.61 kbit/s 1 1 0 1 0 1 448 55.80 kbit/s table 15-7. example spi baud rate selection (25 mhz bus clock) (sheet 2 of 3) sppr2 sppr1 sppr0 spr2 spr1 spr0 baud rate divisor baud rate
serial peripheral interface (s12spiv5) s12xs family reference manual, rev. 1.10 444 freescale semiconductor 15.3.2.4 spi status register (spisr) read: anytime write: has no effect 1 1 0 1 1 0 896 27.90 kbit/s 1 1 0 1 1 1 1792 13.95 kbit/s 1 1 1 0 0 0 16 1.5625 mbit/s 1 1 1 0 0 1 32 781.25 kbit/s 1 1 1 0 1 0 64 390.63 kbit/s 1 1 1 0 1 1 128 195.31 kbit/s 1 1 1 1 0 0 256 97.66 kbit/s 1 1 1 1 0 1 512 48.83 kbit/s 1 1 1 1 1 0 1024 24.41 kbit/s 1 1 1 1 1 1 2048 12.21 kbit/s module base +0x0003 76543210 r spif 0 sptef modf 0000 w reset 0 0 1 00000 = unimplemented or reserved figure 15-6. spi status register (spisr) table 15-8. spisr field descriptions field description 7 spif spif interrupt flag ?this bit is set after received data has been transferred into the spi data register. for information about clearing spif flag, please refer to table 15-9 . 0 transfer not yet complete. 1 new data copied to spidr. 5 sptef spi transmit empty interrupt flag ?if set, this bit indicates that the transmit data register is empty. for information about clearing this bit and placing data into the transmit data register, please refer to table 15-10 . 0 spi data register not empty. 1 spi data register empty. 4 modf mode fault flag this bit is set if the ss input becomes low while the spi is con?ured as a master and mode fault detection is enabled, modfen bit of spicr2 register is set. refer to modfen bit description in section 15.3.2.2, ?pi control register 2 (spicr2) . the ?g is cleared automatically by a read of the spi status register (with modf set) followed by a write to the spi control register 1. 0 mode fault has not occurred. 1 mode fault has occurred. table 15-7. example spi baud rate selection (25 mhz bus clock) (sheet 3 of 3) sppr2 sppr1 sppr0 spr2 spr1 spr0 baud rate divisor baud rate
serial peripheral interface (s12spiv5) s12xs family reference manual, rev. 1.10 freescale semiconductor 445 table 15-9. spif interrupt flag clearing sequence table 15-10. sptef interrupt flag clearing sequence xfrw bit spif interrupt flag clearing sequence 0 read spisr with spif == 1 then read spidrl 1 read spisr with spif == 1 then byte read spidrl 1 1 data in spidrh is lost in this case. or byte read spidrh 2 2 spidrh can be read repeatedly without any effect on spif. spif flag is cleared only by the read of spidrl after reading spisr with spif == 1. byte read spidrl or word read (spidrh:spidrl) xfrw bit sptef interrupt flag clearing sequence 0 read spisr with sptef == 1 then write to spidrl 1 1 any write to spidrh or spidrl with sptef == 0 is effectively ignored. 1 read spisr with sptef == 1 then byte write to spidrl 12 2 data in spidrh is unde?ed in this case. or byte write to spidrh 13 3 spidrh can be written repeatedly without any effect on sptef. sptef flag is cleared only by writing to spidrl after reading spisr with sptef == 1. byte write to spidrl 1 or word write to (spidrh:spidrl) 1
serial peripheral interface (s12spiv5) s12xs family reference manual, rev. 1.10 446 freescale semiconductor 15.3.2.5 spi data register (spidr = spidrh:spidrl) read: anytime; read data only valid when spif is set write: anytime the spi data register is both the input and output register for spi data. a write to this register allows data to be queued and transmitted. for an spi con?ured as a master, queued data is transmitted immediately after the previous transmission has completed. the spi transmitter empty ?g sptef in the spisr register indicates when the spi data register is ready to accept new data. received data in the spidr is valid when spif is set. if spif is cleared and data has been received, the received data is transferred from the receive shift register to the spidr and spif is set. if spif is set and not serviced, and a second data value has been received, the second received data is kept as valid data in the receive shift register until the start of another transmission. the data in the spidr does not change. if spif is set and valid data is in the receive shift register, and spif is serviced before the start of a third transmission, the data in the receive shift register is transferred into the spidr and spif remains set (see figure 15-9 ). if spif is set and valid data is in the receive shift register, and spif is serviced after the start of a third transmission, the data in the receive shift register has become invalid and is not transferred into the spidr (see figure 15-10 ). module base +0x0004 76543210 r r15 r14 r13 r12 r11 r10 r9 r8 w t15 t14 t13 t12 t11 t10 t9 t8 reset 0 0 0 00000 figure 15-7. spi data register high (spidrh) module base +0x0005 76543210 r r7 r6 r5 r4 r3 r2 r1 r0 w t7 t6 t5 t4 t3 t2 t1 t0 reset 0 0 0 00000 figure 15-8. spi data register low (spidrl)
serial peripheral interface (s12spiv5) s12xs family reference manual, rev. 1.10 freescale semiconductor 447 figure 15-9. reception with spif serviced in time figure 15-10. reception with spif serviced too late 15.4 functional description the spi module allows a duplex, synchronous, serial communication between the mcu and peripheral devices. software can poll the spi status ?gs or spi operation can be interrupt driven. the spi system is enabled by setting the spi enable (spe) bit in spi control register 1. while spe is set, the four associated spi port pins are dedicated to the spi function as: slave select ( ss) serial clock (sck) master out/slave in (mosi) master in/slave out (miso) receive shift register spif spi data register data a data b data a data a received data b received data c data c spif serviced data c received data b = unspeci?d = reception in progress receive shift register spif spi data register data a data b data a data a received data b received data c data c spif serviced data c received data b lost = unspeci?d = reception in progress
serial peripheral interface (s12spiv5) s12xs family reference manual, rev. 1.10 448 freescale semiconductor the main element of the spi system is the spi data register. the n-bit 1 data register in the master and the n-bit 1 data register in the slave are linked by the mosi and miso pins to form a distributed 2n-bit 1 register. when a data transfer operation is performed, this 2n-bit 1 register is serially shifted n 1 bit positions by the s-clock from the master, so data is exchanged between the master and the slave. data written to the master spi data register becomes the output data for the slave, and data read from the master spi data register after a transfer operation is the input data from the slave. a read of spisr with sptef = 1 followed by a write to spidr puts data into the transmit data register. when a transfer is complete and spif is cleared, received data is moved into the receive data register. this data register acts as the spi receive data register for reads and as the spi transmit data register for writes. a common spi data register address is shared for reading data from the read data buffer and for writing data to the transmit data register. the clock phase control bit (cpha) and a clock polarity control bit (cpol) in the spi control register 1 (spicr1) select one of four possible clock formats to be used by the spi system. the cpol bit simply selects a non-inverted or inverted clock. the cpha bit is used to accommodate two fundamentally different protocols by sampling data on odd numbered sck edges or on even numbered sck edges (see section 15.4.3, ?ransmission formats ). the spi can be con?ured to operate as a master or as a slave. when the mstr bit in spi control register1 is set, master mode is selected, when the mstr bit is clear, slave mode is selected. note a change of cpol or mstr bit while there is a received byte pending in the receive shift register will destroy the received byte and must be avoided. 15.4.1 master mode the spi operates in master mode when the mstr bit is set. only a master spi module can initiate transmissions. a transmission begins by writing to the master spi data register. if the shift register is empty, data immediately transfers to the shift register. data begins shifting out on the mosi pin under the control of the serial clock. serial clock the spr2, spr1, and spr0 baud rate selection bits, in conjunction with the sppr2, sppr1, and sppr0 baud rate preselection bits in the spi baud rate register, control the baud rate generator and determine the speed of the transmission. the sck pin is the spi clock output. through the sck pin, the baud rate generator of the master controls the shift register of the slave peripheral. mosi, miso pin in master mode, the function of the serial data output pin (mosi) and the serial data input pin (miso) is determined by the spc0 and bidiroe control bits. ss pin if modfen and ssoe are set, the ss pin is con?ured as slave select output. the ss output becomes low during each transmission and is high when the spi is in idle state. if modfen is set and ssoe is cleared, the ss pin is con?ured as input for detecting mode fault error. if the ss input becomes low this indicates a mode fault error where another master tries to 1. n depends on the selected transfer width, please refer to section 15.3.2.2, ?pi control register 2 (spicr2)
serial peripheral interface (s12spiv5) s12xs family reference manual, rev. 1.10 freescale semiconductor 449 drive the mosi and sck lines. in this case, the spi immediately switches to slave mode, by clearing the mstr bit and also disables the slave output buffer miso (or siso in bidirectional mode). so the result is that all outputs are disabled and sck, mosi, and miso are inputs. if a transmission is in progress when the mode fault occurs, the transmission is aborted and the spi is forced into idle state. this mode fault error also sets the mode fault (modf) ?g in the spi status register (spisr). if the spi interrupt enable bit (spie) is set when the modf ?g becomes set, then an spi interrupt sequence is also requested. when a write to the spi data register in the master occurs, there is a half sck-cycle delay. after the delay, sck is started within the master. the rest of the transfer operation differs slightly, depending on the clock format speci?d by the spi clock phase bit, cpha, in spi control register 1 (see section 15.4.3, ?ransmission formats? . note a change of the bits cpol, cpha, ssoe, lsbfe, xfrw, modfen, spc0, or bidiroe with spc0 set, sppr2-sppr0 and spr2-spr0 in master mode will abort a transmission in progress and force the spi into idle state. the remote slave cannot detect this, therefore the master must ensure that the remote slave is returned to idle state. 15.4.2 slave mode the spi operates in slave mode when the mstr bit in spi control register 1 is clear. serial clock in slave mode, sck is the spi clock input from the master. miso, mosi pin in slave mode, the function of the serial data output pin (miso) and serial data input pin (mosi) is determined by the spc0 bit and bidiroe bit in spi control register 2. ss pin the ss pin is the slave select input. before a data transmission occurs, the ss pin of the slave spi must be low. ss must remain low until the transmission is complete. if ss goes high, the spi is forced into idle state. the ss input also controls the serial data output pin, if ss is high (not selected), the serial data output pin is high impedance, and, if ss is low, the ?st bit in the spi data register is driven out of the serial data output pin. also, if the slave is not selected ( ss is high), then the sck input is ignored and no internal shifting of the spi shift register occurs. although the spi is capable of duplex operation, some spi peripherals are capable of only receiving spi data in a slave mode. for these simpler devices, there is no serial data out pin. note when peripherals with duplex capability are used, take care not to simultaneously enable two receivers whose serial outputs drive the same system slaves serial data output line.
serial peripheral interface (s12spiv5) s12xs family reference manual, rev. 1.10 450 freescale semiconductor as long as no more than one slave device drives the system slaves serial data output line, it is possible for several slaves to receive the same transmission from a master, although the master would not receive return information from all of the receiving slaves. if the cpha bit in spi control register 1 is clear, odd numbered edges on the sck input cause the data at the serial data input pin to be latched. even numbered edges cause the value previously latched from the serial data input pin to shift into the lsb or msb of the spi shift register, depending on the lsbfe bit. if the cpha bit is set, even numbered edges on the sck input cause the data at the serial data input pin to be latched. odd numbered edges cause the value previously latched from the serial data input pin to shift into the lsb or msb of the spi shift register, depending on the lsbfe bit. when cpha is set, the ?st edge is used to get the ?st data bit onto the serial data output pin. when cpha is clear and the ss input is low (slave selected), the ?st bit of the spi data is driven out of the serial data output pin. after the nth 1 shift, the transfer is considered complete and the received data is transferred into the spi data register. to indicate transfer is complete, the spif ?g in the spi status register is set. note a change of the bits cpol, cpha, ssoe, lsbfe, modfen, spc0, or bidiroe with spc0 set in slave mode will corrupt a transmission in progress and must be avoided. 15.4.3 transmission formats during an spi transmission, data is transmitted (shifted out serially) and received (shifted in serially) simultaneously. the serial clock (sck) synchronizes shifting and sampling of the information on the two serial data lines. a slave select line allows selection of an individual slave spi device; slave devices that are not selected do not interfere with spi bus activities. optionally, on a master spi device, the slave select line can be used to indicate multiple-master bus contention. figure 15-11. master/slave transfer block diagram 15.4.3.1 clock phase and polarity controls using two bits in the spi control register 1, software selects one of four combinations of serial clock phase and polarity. 1. n depends on the selected transfer width, please refer to section 15.3.2.2, ?pi control register 2 (spicr2) shift register shift register baud rate generator master spi slave spi mosi mosi miso miso sck sck ss ss v dd
serial peripheral interface (s12spiv5) s12xs family reference manual, rev. 1.10 freescale semiconductor 451 the cpol clock polarity control bit speci?s an active high or low clock and has no signi?ant effect on the transmission format. the cpha clock phase control bit selects one of two fundamentally different transmission formats. clock phase and polarity should be identical for the master spi device and the communicating slave device. in some cases, the phase and polarity are changed between transmissions to allow a master device to communicate with peripheral slaves having different requirements. 15.4.3.2 cpha = 0 transfer format the ?st edge on the sck line is used to clock the ?st data bit of the slave into the master and the ?st data bit of the master into the slave. in some peripherals, the ?st bit of the slaves data is available at the slaves data out pin as soon as the slave is selected. in this format, the ?st sck edge is issued a half cycle after ss has become low. a half sck cycle later, the second edge appears on the sck line. when this second edge occurs, the value previously latched from the serial data input pin is shifted into the lsb or msb of the shift register, depending on lsbfe bit. after this second edge, the next bit of the spi master data is transmitted out of the serial data output pin of the master to the serial input pin on the slave. this process continues for a total of 16 edges on the sck line, with data being latched on odd numbered edges and shifted on even numbered edges. data reception is double buffered. data is shifted serially into the spi shift register during the transfer and is transferred to the parallel spi data register after the last bit is shifted in. after 2n 1 (last) sck edges: data that was previously in the master spi data register should now be in the slave data register and the data that was in the slave data register should be in the master. the spif ?g in the spi status register is set, indicating that the transfer is complete. figure 15-12 is a timing diagram of an spi transfer where cpha = 0. sck waveforms are shown for cpol = 0 and cpol = 1. the diagram may be interpreted as a master or slave timing diagram because the sck, miso, and mosi pins are connected directly between the master and the slave. the miso signal is the output from the slave and the mosi signal is the output from the master. the ss pin of the master must be either high or recon?ured as a general-purpose output not affecting the spi. 1. n depends on the selected transfer width, please refer to section 15.3.2.2, ?pi control register 2 (spicr2)
serial peripheral interface (s12spiv5) s12xs family reference manual, rev. 1.10 452 freescale semiconductor figure 15-12. spi clock format 0 (cpha = 0), with 8-bit transfer width selected (xfrw = 0) t l begin end sck (cpol = 0) sample i change o sel ss (o) transfer sck (cpol = 1) msb ?st (lsbfe = 0): lsb ?st (lsbfe = 1): msb lsb lsb msb bit 5 bit 2 bit 6 bit 1 bit 4 bit 3 bit 3 bit 4 bit 2 bit 5 bit 1 bit 6 change o sel ss (i) mosi pin miso pin master only mosi/miso t t if next transfer begins here for t t , t l , t l minimum 1/2 sck t i t l t l = minimum leading time before the ?st sck edge t t = minimum trailing time after the last sck edge t i = minimum idling time between transfers (minimum ss high time) t l , t t , and t i are guaranteed for the master mode and required for the slave mode. 1 2 34 56 78910111213141516 sck edge number end of idle state begin of idle state
serial peripheral interface (s12spiv5) s12xs family reference manual, rev. 1.10 freescale semiconductor 453 figure 15-13. spi clock format 0 (cpha = 0), with 16-bit transfer width selected (xfrw = 1) in slave mode, if the ss line is not deasserted between the successive transmissions then the content of the spi data register is not transmitted; instead the last received data is transmitted. if the ss line is deasserted for at least minimum idle time (half sck cycle) between successive transmissions, then the content of the spi data register is transmitted. in master mode, with slave select output enabled the ss line is always deasserted and reasserted between successive transfers for at least minimum idle time. 15.4.3.3 cpha = 1 transfer format some peripherals require the ?st sck edge before the ?st data bit becomes available at the data out pin, the second edge clocks data into the system. in this format, the ?st sck edge is issued by setting the cpha bit at the beginning of the n 1 -cycle transfer operation. the ?st edge of sck occurs immediately after the half sck clock cycle synchronization delay. this ?st edge commands the slave to transfer its ?st data bit to the serial data input pin of the master. a half sck cycle later, the second edge appears on the sck pin. this is the latching edge for both the master and slave. 1. n depends on the selected transfer width, please refer to section 15.3.2.2, ?pi control register 2 (spicr2) t l begin end sck (cpol = 0) sample i change o sel ss (o) transfer sck (cpol = 1) msb ?st (lsbfe = 0) lsb ?st (lsbfe = 1) msb lsb lsb msb bit 13 bit 2 bit 14 bit 1 bit 12 bit 3 bit 11 bit 4 bit 5 change o sel ss (i) mosi pin miso pin master only mosi/miso t t if next transfer begins here for t t , t l , t l minimum 1/2 sck t i t l t l = minimum leading time before the ?st sck edge t t = minimum trailing time after the last sck edge t i = minimum idling time between transfers (minimum ss high time) t l , t t , and t i are guaranteed for the master mode and required for the slave mode. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 sck edge number end of idle state begin of idle state 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 bit 10 bit 9 bit 8 bit 7 bit 6 bit 4 bit 3 bit 2 bit 1 bit 6 bit 5 bit 7 bit 8 bit 9 bit 10bit 11 bit 12bit 13 bit 14
serial peripheral interface (s12spiv5) s12xs family reference manual, rev. 1.10 454 freescale semiconductor when the third edge occurs, the value previously latched from the serial data input pin is shifted into the lsb or msb of the spi shift register, depending on lsbfe bit. after this edge, the next bit of the master data is coupled out of the serial data output pin of the master to the serial input pin on the slave. this process continues for a total of n 1 edges on the sck line with data being latched on even numbered edges and shifting taking place on odd numbered edges. data reception is double buffered, data is serially shifted into the spi shift register during the transfer and is transferred to the parallel spi data register after the last bit is shifted in. after 2n 1 sck edges: data that was previously in the spi data register of the master is now in the data register of the slave, and data that was in the data register of the slave is in the master. the spif ?g bit in spisr is set indicating that the transfer is complete. figure 15-14 shows two clocking variations for cpha = 1. the diagram may be interpreted as a master or slave timing diagram because the sck, miso, and mosi pins are connected directly between the master and the slave. the miso signal is the output from the slave, and the mosi signal is the output from the master. the ss line is the slave select input to the slave. the ss pin of the master must be either high or recon?ured as a general-purpose output not affecting the spi. figure 15-14. spi clock format 1 (cpha = 1), with 8-bit transfer width selected (xfrw = 0) t l t t for t t , t l , t l minimum 1/2 sck t i t l if next transfer begins here begin end sck (cpol = 0) sample i change o sel ss (o) transfer sck (cpol = 1) msb ?st (lsbfe = 0): lsb ?st (lsbfe = 1): msb lsb lsb msb bit 5 bit 2 bit 6 bit 1 bit 4 bit 3 bit 3 bit 4 bit 2 bit 5 bit 1 bit 6 change o sel ss (i) mosi pin miso pin master only mosi/miso t l = minimum leading time before the ?st sck edge, not required for back-to-back transfers t t = minimum trailing time after the last sck edge t i = minimum idling time between transfers (minimum ss high time), not required for back-to-back transfers 1 2 34 56 78910111213141516 sck edge number end of idle state begin of idle state
serial peripheral interface (s12spiv5) s12xs family reference manual, rev. 1.10 freescale semiconductor 455 figure 15-15. spi clock format 1 (cpha = 1), with 16-bit transfer width selected (xfrw = 1) the ss line can remain active low between successive transfers (can be tied low at all times). this format is sometimes preferred in systems having a single ?ed master and a single slave that drive the miso data line. back-to-back transfers in master mode in master mode, if a transmission has completed and new data is available in the spi data register, this data is sent out immediately without a trailing and minimum idle time. the spi interrupt request ?g (spif) is common to both the master and slave modes. spif gets set one half sck cycle after the last sck edge. 15.4.4 spi baud rate generation baud rate generation consists of a series of divider stages. six bits in the spi baud rate register (sppr2, sppr1, sppr0, spr2, spr1, and spr0) determine the divisor to the spi module clock which results in the spi baud rate. the spi clock rate is determined by the product of the value in the baud rate preselection bits (sppr2?ppr0) and the value in the baud rate selection bits (spr2?pr0). the module clock divisor equation is shown in equation 15-3 . baudratedivisor = (sppr + 1) ? 2 (spr + 1) eqn. 15-3 t l begin end sck (cpol = 0) sample i change o sel ss (o) transfer sck (cpol = 1) msb ?st (lsbfe = 0) lsb ?st (lsbfe = 1) msb lsb lsb msb bit 13 bit 2 bit 14 bit 1 bit 12 bit 3 bit 11 bit 4 bit 5 change o sel ss (i) mosi pin miso pin master only mosi/miso t t if next transfer begins here for t t , t l , t l minimum 1/2 sck t i t l t l = minimum leading time before the ?st sck edge, not required for back-to-back transfers t t = minimum trailing time after the last sck edge t i = minimum idling time between transfers (minimum ss high time), not required for back-to-back transfers 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 sck edge number end of idle state begin of idle state 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 bit 10 bit 9 bit 8 bit 7 bit 6 bit 4 bit 3 bit 2 bit 1 bit 6 bit 5 bit 7 bit 8 bit 9 bit 10bit 11 bit 12bit 13 bit 14
serial peripheral interface (s12spiv5) s12xs family reference manual, rev. 1.10 456 freescale semiconductor when all bits are clear (the default condition), the spi module clock is divided by 2. when the selection bits (spr2?pr0) are 001 and the preselection bits (sppr2?ppr0) are 000, the module clock divisor becomes 4. when the selection bits are 010, the module clock divisor becomes 8, etc. when the preselection bits are 001, the divisor determined by the selection bits is multiplied by 2. when the preselection bits are 010, the divisor is multiplied by 3, etc. see table 15-7 for baud rate calculations for all bit conditions, based on a 25 mhz bus clock. the two sets of selects allows the clock to be divided by a non-power of two to achieve other baud rates such as divide by 6, divide by 10, etc. the baud rate generator is activated only when the spi is in master mode and a serial transfer is taking place. in the other cases, the divider is disabled to decrease i dd current. note for maximum allowed baud rates, please refer to the spi electrical speci?ation in the electricals chapter of this data sheet. 15.4.5 special features 15.4.5.1 ss output the ss output feature automatically drives the ss pin low during transmission to select external devices and drives it high during idle to deselect external devices. when ss output is selected, the ss output pin is connected to the ss input pin of the external device. the ss output is available only in master mode during normal spi operation by asserting ssoe and modfen bit as shown in table 15-3 . the mode fault feature is disabled while ss output is enabled. note care must be taken when using the ss output feature in a multimaster system because the mode fault feature is not available for detecting system errors between masters. 15.4.5.2 bidirectional mode (momi or siso) the bidirectional mode is selected when the spc0 bit is set in spi control register 2 (see table 15-11 ). in this mode, the spi uses only one serial data pin for the interface with external device(s). the mstr bit decides which pin to use. the mosi pin becomes the serial data i/o (momi) pin for the master mode, and the miso pin becomes serial data i/o (siso) pin for the slave mode. the miso pin in master mode and mosi pin in slave mode are not used by the spi.
serial peripheral interface (s12spiv5) s12xs family reference manual, rev. 1.10 freescale semiconductor 457 the direction of each serial i/o pin depends on the bidiroe bit. if the pin is con?ured as an output, serial data from the shift register is driven out on the pin. the same pin is also the serial input to the shift register. the sck is output for the master mode and input for the slave mode. the ss is the input or output for the master mode, and it is always the input for the slave mode. the bidirectional mode does not affect sck and ss functions. note in bidirectional master mode, with mode fault enabled, both data pins miso and mosi can be occupied by the spi, though mosi is normally used for transmissions in bidirectional mode and miso is not used by the spi. if a mode fault occurs, the spi is automatically switched to slave mode. in this case miso becomes occupied by the spi and mosi is not used. this must be considered, if the miso pin is used for another purpose. 15.4.6 error conditions the spi has one error condition: mode fault error 15.4.6.1 mode fault error if the ss input becomes low while the spi is con?ured as a master, it indicates a system error where more than one master may be trying to drive the mosi and sck lines simultaneously. this condition is not permitted in normal operation, the modf bit in the spi status register is set automatically, provided the modfen bit is set. in the special case where the spi is in master mode and modfen bit is cleared, the ss pin is not used by the spi. in this special case, the mode fault error function is inhibited and modf remains cleared. in case table 15-11. normal mode and bidirectional mode when spe = 1 master mode mstr = 1 slave mode mstr = 0 normal mode spc0 = 0 bidirectional mode spc0 = 1 spi mosi miso serial out serial in spi mosi miso serial in serial out spi momi serial out serial in bidiroe spi siso serial in serial out bidiroe
serial peripheral interface (s12spiv5) s12xs family reference manual, rev. 1.10 458 freescale semiconductor the spi system is con?ured as a slave, the ss pin is a dedicated input pin. mode fault error doesnt occur in slave mode. if a mode fault error occurs, the spi is switched to slave mode, with the exception that the slave output buffer is disabled. so sck, miso, and mosi pins are forced to be high impedance inputs to avoid any possibility of con?ct with another output driver. a transmission in progress is aborted and the spi is forced into idle state. if the mode fault error occurs in the bidirectional mode for a spi system con?ured in master mode, output enable of the momi (mosi in bidirectional mode) is cleared if it was set. no mode fault error occurs in the bidirectional mode for spi system con?ured in slave mode. the mode fault ?g is cleared automatically by a read of the spi status register (with modf set) followed by a write to spi control register 1. if the mode fault ?g is cleared, the spi becomes a normal master or slave again. note if a mode fault error occurs and a received data byte is pending in the receive shift register, this data byte will be lost. 15.4.7 low power mode options 15.4.7.1 spi in run mode in run mode with the spi system enable (spe) bit in the spi control register clear, the spi system is in a low-power, disabled state. spi registers remain accessible, but clocks to the core of this module are disabled. 15.4.7.2 spi in wait mode spi operation in wait mode depends upon the state of the spiswai bit in spi control register 2. if spiswai is clear, the spi operates normally when the cpu is in wait mode if spiswai is set, spi clock generation ceases and the spi module enters a power conservation state when the cpu is in wait mode. if spiswai is set and the spi is configured for master, any transmission and reception in progress stops at wait mode entry. the transmission and reception resumes when the spi exits wait mode. if spiswai is set and the spi is configured as a slave, any transmission and reception in progress continues if the sck continues to be driven from the master. this keeps the slave synchronized to the master and the sck. if the master transmits several bytes while the slave is in wait mode, the slave will continue to send out bytes consistent with the operation mode at the start of wait mode (i.e., if the slave is currently sending its spidr to the master, it will continue to send the same byte. else if the slave is currently sending the last received byte from the master, it will continue to send each previous master byte).
serial peripheral interface (s12spiv5) s12xs family reference manual, rev. 1.10 freescale semiconductor 459 note care must be taken when expecting data from a master while the slave is in wait or stop mode. even though the shift register will continue to operate, the rest of the spi is shut down (i.e., a spif interrupt will not be generated until exiting stop or wait mode). also, the byte from the shift register will not be copied into the spidr register until after the slave spi has exited wait or stop mode. in slave mode, a received byte pending in the receive shift register will be lost when entering wait or stop mode. an spif ?g and spidr copy is generated only if wait mode is entered or exited during a tranmission. if the slave enters wait mode in idle mode and exits wait mode in idle mode, neither a spif nor a spidr copy will occur. 15.4.7.3 spi in stop mode stop mode is dependent on the system. the spi enters stop mode when the module clock is disabled (held high or low). if the spi is in master mode and exchanging data when the cpu enters stop mode, the transmission is frozen until the cpu exits stop mode. after stop, data to and from the external spi is exchanged correctly. in slave mode, the spi will stay synchronized with the master. the stop mode is not dependent on the spiswai bit. 15.4.7.4 reset the reset values of registers and signals are described in section 15.3, ?emory map and register de?ition , which details the registers and their bit ?lds. if a data transmission occurs in slave mode after reset without a write to spidr, it will transmit garbage, or the data last received from the master before the reset. reading from the spidr after reset will always read zeros. 15.4.7.5 interrupts the spi only originates interrupt requests when spi is enabled (spe bit in spicr1 set). the following is a description of how the spi makes a request and how the mcu should acknowledge that request. the interrupt vector offset and interrupt priority are chip dependent. the interrupt ?gs modf, spif, and sptef are logically ored to generate an interrupt request. 15.4.7.5.1 modf modf occurs when the master detects an error on the ss pin. the master spi must be con?ured for the modf feature (see table 15-3 ). after modf is set, the current transfer is aborted and the following bit is changed: mstr = 0, the master bit in spicr1 resets. the modf interrupt is re?cted in the status register modf ?g. clearing the ?g will also clear the interrupt. this interrupt will stay active while the modf ?g is set. modf has an automatic clearing process which is described in section 15.3.2.4, ?pi status register (spisr) .
serial peripheral interface (s12spiv5) s12xs family reference manual, rev. 1.10 460 freescale semiconductor 15.4.7.5.2 spif spif occurs when new data has been received and copied to the spi data register. after spif is set, it does not clear until it is serviced. spif has an automatic clearing process, which is described in section 15.3.2.4, ?pi status register (spisr) . 15.4.7.5.3 sptef sptef occurs when the spi data register is ready to accept new data. after sptef is set, it does not clear until it is serviced. sptef has an automatic clearing process, which is described in section 15.3.2.4, ?pi status register (spisr) .
s12xs family reference manual, rev. 1.10 freescale semiconductor 461 chapter 16 timer module (tim16b8cv2) 16.1 introduction the basic timer consists of a 16-bit, software-programmable counter driven by a enhanced programmable prescaler. this timer can be used for many purposes, including input waveform measurements while simultaneously generating an output waveform. pulse widths can vary from microseconds to many seconds. this timer contains 8 complete input capture/output compare channels and one pulse accumulator. the input capture function is used to detect a selected transition edge and record the time. the output compare function is used for generating output signals or for timer software delays. the 16-bit pulse accumulator is used to operate as a simple event counter or a gated time accumulator. the pulse accumulator shares timer channel 7 when in event mode. a full access for the counter registers or the input capture/output compare registers should take place in one clock cycle. accessing high byte and low byte separately for all of these registers may not yield the same result as accessing them in one word. 16.1.1 features the tim16b8cv2 includes these distinctive features: table 16-1. revision history revision number revision date sections affected description of changes v02.05 9 jul 2009 16.3.2.12/16-477 16.3.2.13/16-477 16.3.2.15/16-479 16.3.2.16/16-480 16.3.2.19/16-482 16.4.2/16-485 16.4.3/16-485 - revised ?g clearing procedure, whereby ten or paen bit must be set when clearing ?gs. - add fomula to describe prescaler v02.06 26 aug 2009 16.1.2/16-462 16.3.2.15/16-479 16.3.2.2/16-468 16.3.2.3/16-469 16.3.2.4/16-470 16.4.3/16-485 - correct typo: tscr ->tscr1 - correct reference: figure 1-25 -> figure 1-31 - add description, ? counter over?w when ttov[7] is set? to be the condition of channel 7 override event. - phrase the description of oc7m to make it more explicit v02.07 04 may 2010 16.3.2.8/16-473 16.3.2.11/16-476 16.4.3/16-485 - add table 16-10 - in tcre bit description part,add note - add figure 16-31
timer module (tim16b8cv2) s12xs family reference manual, rev. 1.10 462 freescale semiconductor eight input capture/output compare channels. clock prescaling. 16-bit counter. 16-bit pulse accumulator. 16.1.2 modes of operation stop: timer is off because clocks are stopped. freeze: timer counter keep on running, unless tsfrz in tscr1 (0x0006) is set to 1. wait: counters keep on running, unless tswai in tscr1 (0x0006) is set to 1. normal: timer counter keep on running, unless ten in tscr1 (0x0006) is cleared to 0.
timer module (tim16b8cv2) s12xs family reference manual rev. 1.10 freescale semiconductor 463 16.1.3 block diagrams figure 16-1. tim16b8cv2 block diagram prescaler 16-bit counter input capture output compare 16-bit pulse accumulator ioc0 ioc2 ioc1 ioc5 ioc3 ioc4 ioc6 ioc7 pa input interrupt pa overflow interrupt timer overflow interrupt timer channel 0 interrupt timer channel 7 interrupt registers bus clock input capture output compare input capture output compare input capture output compare input capture output compare input capture output compare input capture output compare input capture output compare channel 0 channel 1 channel 2 channel 3 channel 4 channel 5 channel 6 channel 7
timer module (tim16b8cv2) s12xs family reference manual, rev. 1.10 464 freescale semiconductor figure 16-2. 16-bit pulse accumulator block diagram figure 16-3. interrupt flag setting edge detector intermodule bus pt7 m clock divide by 64 clock select clk0 clk1 4:1 mux timclk paclk paclk / 256 paclk / 65536 prescaled clock (pclk) (timer clock) interrupt mux (pamod) pacnt ptn edge detector 16-bit main timer tcn input capture reg. set cnf interrupt
timer module (tim16b8cv2) s12xs family reference manual rev. 1.10 freescale semiconductor 465 figure 16-4. channel 7 output compare/pulse accumulator logic 16.2 external signal description the tim16b8cv2 module has a total of eight external pins. 16.2.1 ioc7 ?input capture and output compare channel 7 pin this pin serves as input capture or output compare for channel 7. this can also be con?ured as pulse accumulator input. 16.2.2 ioc6 ?input capture and output compare channel 6 pin this pin serves as input capture or output compare for channel 6. 16.2.3 ioc5 ?input capture and output compare channel 5 pin this pin serves as input capture or output compare for channel 5. 16.2.4 ioc4 ?input capture and output compare channel 4 pin this pin serves as input capture or output compare for channel 4. pin 16.2.5 ioc3 ?input capture and output compare channel 3 pin this pin serves as input capture or output compare for channel 3. 16.2.6 ioc2 ?input capture and output compare channel 2 pin this pin serves as input capture or output compare for channel 2. pulse accumulator pa d ten channel 7 output compare ocpd tios7
timer module (tim16b8cv2) s12xs family reference manual, rev. 1.10 466 freescale semiconductor 16.2.7 ioc1 ?input capture and output compare channel 1 pin this pin serves as input capture or output compare for channel 1. 16.2.8 ioc0 ?input capture and output compare channel 0 pin this pin serves as input capture or output compare for channel 0. note for the description of interrupts see section 16.6, ?nterrupts . 16.3 memory map and register de?ition this section provides a detailed description of all memory and registers. 16.3.1 module memory map the memory map for the tim16b8cv2 module is given below in figure 16-5 . the address listed for each register is the address offset. the total address for each register is the sum of the base address for the tim16b8cv2 module and the address offset for each register. 16.3.2 register descriptions this section consists of register descriptions in address order. each description includes a standard register diagram with an associated ?ure number. details of register bit and ?ld function follow the register diagrams, in bit order. register name bit 7 654321 bit 0 0x0000 tios r ios7 ios6 ios5 ios4 ios3 ios2 ios1 ios0 w 0x0001 cforc r00000000 w foc7 foc6 foc5 foc4 foc3 foc2 foc1 foc0 0x0002 oc7m r oc7m7 oc7m6 oc7m5 oc7m4 oc7m3 oc7m2 oc7m1 oc7m0 w 0x0003 oc7d r oc7d7 oc7d6 oc7d5 oc7d4 oc7d3 oc7d2 oc7d1 oc7d0 w 0x0004 tcnth r tcnt15 tcnt14 tcnt13 tcnt12 tcnt11 tcnt10 tcnt9 tcnt8 w 0x0005 tcntl r tcnt7 tcnt6 tcnt5 tcnt4 tcnt3 tcnt2 tcnt1 tcnt0 w = unimplemented or reserved figure 16-5. tim16b8cv2 register summary (sheet 1 of 3)
timer module (tim16b8cv2) s12xs family reference manual rev. 1.10 freescale semiconductor 467 0x0006 tscr1 r ten tswai tsfrz tffca prnt 000 w 0x0007 ttov r tov7 tov6 tov5 tov4 tov3 tov2 tov1 tov0 w 0x0008 tctl1 r om7 ol7 om6 ol6 om5 ol5 om4 ol4 w 0x0009 tctl2 r om3 ol3 om2 ol2 om1 ol1 om0 ol0 w 0x000a tctl3 r edg7b edg7a edg6b edg6a edg5b edg5a edg4b edg4a w 0x000b tctl4 r edg3b edg3a edg2b edg2a edg1b edg1a edg0b edg0a w 0x000c tie r c7i c6i c5i c4i c3i c2i c1i c0i w 0x000d tscr2 r toi 000 tcre pr2 pr1 pr0 w 0x000e tflg1 r c7f c6f c5f c4f c3f c2f c1f c0f w 0x000f tflg2 r tof 0000000 w 0x0010?x001f tcxh?cxl r bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 w r bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 w 0x0020 pactl r0 paen pamod pedge clk1 clk0 paovi pai w 0x0021 paflg r000000 paovf paif w 0x0022 pacnth r pacnt15 pacnt14 pacnt13 pacnt12 pacnt11 pacnt10 pacnt9 pacnt8 w 0x0023 pacntl r pacnt7 pacnt6 pacnt5 pacnt4 pacnt3 pacnt2 pacnt1 pacnt0 w 0x0024?x002b reserved r w register name bit 7 654321 bit 0 = unimplemented or reserved figure 16-5. tim16b8cv2 register summary (sheet 2 of 3)
timer module (tim16b8cv2) s12xs family reference manual, rev. 1.10 468 freescale semiconductor 16.3.2.1 timer input capture/output compare select (tios) read: anytime write: anytime 16.3.2.2 timer compare force register (cforc) 0x002c ocpd r ocpd7 ocpd6 ocpd5 ocpd4 ocpd3 ocpd2 ocpd1 ocpd0 w 0x002d r 0x002e ptpsr r ptps7 ptps6 ptps5 ptps4 ptps3 ptps2 ptps1 ptps0 w 0x002f reserved r w module base + 0x0000 76543210 r ios7 ios6 ios5 ios4 ios3 ios2 ios1 ios0 w reset 00000000 figure 16-6. timer input capture/output compare select (tios) table 16-2. tios field descriptions field description 7:0 ios[7:0] input capture or output compare channel con?uration 0 the corresponding channel acts as an input capture. 1 the corresponding channel acts as an output compare. module base + 0x0001 76543210 r00000000 w foc7 foc6 foc5 foc4 foc3 foc2 foc1 foc0 reset 00000000 figure 16-7. timer compare force register (cforc) register name bit 7 654321 bit 0 = unimplemented or reserved figure 16-5. tim16b8cv2 register summary (sheet 3 of 3)
timer module (tim16b8cv2) s12xs family reference manual rev. 1.10 freescale semiconductor 469 read: anytime but will always return 0x0000 (1 state is transient) write: anytime 16.3.2.3 output compare 7 mask register (oc7m) read: anytime write: anytime table 16-3. cforc field descriptions field description 7:0 foc[7:0] force output compare action for channel 7:0 a write to this register with the corresponding data bit(s) set causes the action which is programmed for output compare ??to occur immediately. the action taken is the same as if a successful comparison had just taken place with the tcx register except the interrupt ?g does not get set. note: a channel 7 event, which can be a counter over?w when ttov[7] is set or a successful output compare on channel 7, overrides any channel 6:0 compares. if forced output compare on any channel occurs at the same time as the successful output compare then forced output compare action will take precedence and interrupt ?g won? get set. module base + 0x0002 76543210 r oc7m7 oc7m6 oc7m5 oc7m4 oc7m3 oc7m2 oc7m1 oc7m0 w reset 00000000 figure 16-8. output compare 7 mask register (oc7m) table 16-4. oc7m field descriptions field description 7:0 oc7m[7:0] output compare 7 mask ?a channel 7 event, which can be a counter over?w when ttov[7] is set or a successful output compare on channel 7, overrides any channel 6:0 compares. for each oc7m bit that is set, the output compare action re?cts the corresponding oc7d bit. 0 the corresponding oc7dx bit in the output compare 7 data register will not be transferred to the timer port on a channel 7 event, even if the corresponding pin is setup for output compare. 1 the corresponding oc7dx bit in the output compare 7 data register will be transferred to the timer port on a channel 7 event. note: the corresponding channel must also be setup for output compare (iosx = 1 and ocpdx = 0) for data to be transferred from the output compare 7 data register to the timer port.
timer module (tim16b8cv2) s12xs family reference manual, rev. 1.10 470 freescale semiconductor 16.3.2.4 output compare 7 data register (oc7d) read: anytime write: anytime 16.3.2.5 timer count register (tcnt) the 16-bit main timer is an up counter. a full access for the counter register should take place in one clock cycle. a separate read/write for high byte and low byte will give a different result than accessing them as a word. read: anytime module base + 0x0003 76543210 r oc7d7 oc7d6 oc7d5 oc7d4 oc7d3 oc7d2 oc7d1 oc7d0 w reset 00000000 figure 16-9. output compare 7 data register (oc7d) table 16-5. oc7d field descriptions field description 7:0 oc7d[7:0] output compare 7 data ?a channel 7 event, which can be a counter over?w when ttov[7] is set or a successful output compare on channel 7, can cause bits in the output compare 7 data register to transfer to the timer port data register depending on the output compare 7 mask register. module base + 0x0004 15 14 13 12 11 10 9 9 r tcnt15 tcnt14 tcnt13 tcnt12 tcnt11 tcnt10 tcnt9 tcnt8 w reset 00000000 figure 16-10. timer count register high (tcnth) module base + 0x0005 76543210 r tcnt7 tcnt6 tcnt5 tcnt4 tcnt3 tcnt2 tcnt1 tcnt0 w reset 00000000 figure 16-11. timer count register low (tcntl)
timer module (tim16b8cv2) s12xs family reference manual rev. 1.10 freescale semiconductor 471 write: has no meaning or effect in the normal mode; only writable in special modes (test_mode = 1). the period of the ?st count after a write to the tcnt registers may be a different size because the write is not synchronized with the prescaler clock. 16.3.2.6 timer system control register 1 (tscr1) read: anytime write: anytime module base + 0x0006 76543210 r ten tswai tsfrz tffca prnt 000 w reset 00000000 = unimplemented or reserved figure 16-12. timer system control register 1 (tscr1) table 16-6. tscr1 field descriptions field description 7 ten timer enable 0 disables the main timer, including the counter. can be used for reducing power consumption. 1 allows the timer to function normally. if for any reason the timer is not active, there is no 64 clock for the pulse accumulator because the 64 is generated by the timer prescaler. 6 tswai timer module stops while in wait 0 allows the timer module to continue running during wait. 1 disables the timer module when the mcu is in the wait mode. timer interrupts cannot be used to get the mcu out of wait. tswai also affects pulse accumulator. 5 tsfrz timer stops while in freeze mode 0 allows the timer counter to continue running while in freeze mode. 1 disables the timer counter whenever the mcu is in freeze mode. this is useful for emulation. tsfrz does not stop the pulse accumulator.
timer module (tim16b8cv2) s12xs family reference manual, rev. 1.10 472 freescale semiconductor 16.3.2.7 timer toggle on over?w register 1 (ttov) read: anytime write: anytime 4 tffca timer fast flag clear all 0 allows the timer ?g clearing to function normally. 1 for tflg1(0x000e), a read from an input capture or a write to the output compare channel (0x0010?x001f) causes the corresponding channel ?g, cnf, to be cleared. for tflg2 (0x000f), any access to the tcnt register (0x0004, 0x0005) clears the tof ?g. any access to the pacnt registers (0x0022, 0x0023) clears the paovf and paif ?gs in the paflg register (0x0021). this has the advantage of eliminating software overhead in a separate clear sequence. extra care is required to avoid accidental ?g clearing due to unintended accesses. 3 prnt precision timer 0 enables legacy timer. pr0, pr1, and pr2 bits of the tscr2 register are used for timer counter prescaler selection. 1 enables precision timer. all bits of the ptpsr register are used for precision timer prescaler selection, and all bits. this bit is writable only once out of reset. module base + 0x0007 76543210 r tov7 tov6 tov5 tov4 tov3 tov2 tov1 tov0 w reset 00000000 figure 16-13. timer toggle on over?w register 1 (ttov) table 16-7. ttov field descriptions field description 7:0 tov[7:0] toggle on over?w bits tovx toggles output compare pin on over?w. this feature only takes effect when in output compare mode. when set, it takes precedence over forced output compare but not channel 7 override events. 0 toggle output compare pin on over?w feature disabled. 1 toggle output compare pin on over?w feature enabled. table 16-6. tscr1 field descriptions (continued) field description
timer module (tim16b8cv2) s12xs family reference manual rev. 1.10 freescale semiconductor 473 16.3.2.8 timer control register 1/timer control register 2 (tctl1/tctl2) read: anytime write: anytime module base + 0x0008 76543210 r om7 ol7 om6 ol6 om5 ol5 om4 ol4 w reset 00000000 figure 16-14. timer control register 1 (tctl1) module base + 0x0009 76543210 r om3 ol3 om2 ol2 om1 ol1 om0 ol0 w reset 00000000 figure 16-15. timer control register 2 (tctl2) table 16-8. tctl1/tctl2 field descriptions field description 7:0 omx output mode these eight pairs of control bits are encoded to specify the output action to be taken as a result of a successful ocx compare. when either omx or olx is 1, the pin associated with ocx becomes an output tied to ocx. note: to enable output action by omx bits on timer port, the corresponding bit in oc7m should be cleared. for an output line to be driven by an ocx the ocpdx must be cleared. 7:0 olx output level these eight pairs of control bits are encoded to specify the output action to be taken as a result of a successful ocx compare. when either omx or olx is 1, the pin associated with ocx becomes an output tied to ocx. note: to enable output action by olx bits on timer port, the corresponding bit in oc7m should be cleared. for an output line to be driven by an ocx the ocpdx must be cleared. table 16-9. compare result output action omx olx action 0 0 no output compare action on the timer output signal 0 1 toggle ocx output line 1 0 clear ocx output line to zero 1 1 set ocx output line to one
timer module (tim16b8cv2) s12xs family reference manual, rev. 1.10 474 freescale semiconductor to operate the 16-bit pulse accumulator independently of input capture or output compare 7 and 0 respectively the user must set the corresponding bits iosx = 1, omx = 0 and olx = 0. oc7m7 in the oc7m register must also be cleared. to enable output action using the om7 and ol7 bits on the timer port,the corresponding bit oc7m7 in the oc7m register must also be cleared. the settings for these bits can be seen in table 16-10 table 16-10. the oc7 and ocx event priority note: in table 16-10 , the ios7 and iosx should be set to 1 iosx is the register tios bit x, oc7mx is the register oc7m bit x, tcx is timer input capture/output compare register, iocx is channel x, omx/olx is the register tctl1/tctl2, oc7dx is the register oc7d bit x. iocx = oc7dx+ omx/olx, means that both oc7 event and ocx event will change channel x value. 16.3.2.9 timer control register 3/timer control register 4 (tctl3 and tctl4) oc7m7=0 oc7m7=1 oc7mx=1 oc7mx=0 oc7mx=1 oc7mx=0 tc7=tcx tc7>tcx tc7=tcx tc7>tcx tc7=tcx tc7>tcx tc7=tcx tc7>tcx iocx=oc7dx ioc7=om7/o l7 iocx=oc7dx +omx/olx ioc7=om7/o l7 iocx=omx/olx ioc7=om7/ol7 iocx=oc7dx ioc7=oc7d7 iocx=oc7dx +omx/olx ioc7=oc7d7 iocx=omx/olx ioc7=oc7d7 module base + 0x000a 76543210 r edg7b edg7a edg6b edg6a edg5b edg5a edg4b edg4a w reset 00000000 figure 16-16. timer control register 3 (tctl3) module base + 0x000b 76543210 r edg3b edg3a edg2b edg2a edg1b edg1a edg0b edg0a w reset 00000000 figure 16-17. timer control register 4 (tctl4)
timer module (tim16b8cv2) s12xs family reference manual rev. 1.10 freescale semiconductor 475 read: anytime write: anytime. 16.3.2.10 timer interrupt enable register (tie) read: anytime write: anytime. table 16-11. tctl3/tctl4 field descriptions field description 7:0 edgnb edgna input capture edge control ?these eight pairs of control bits con?ure the input capture edge detector circuits. table 16-12. edge detector circuit con?uration edgnb edgna con?uration 0 0 capture disabled 0 1 capture on rising edges only 1 0 capture on falling edges only 1 1 capture on any edge (rising or falling) module base + 0x000c 76543210 r c7i c6i c5i c4i c3i c2i c1i c0i w reset 00000000 figure 16-18. timer interrupt enable register (tie) table 16-13. tie field descriptions field description 7:0 c7i:c0i input capture/output compare ??interrupt enable the bits in tie correspond bit-for-bit with the bits in the tflg1 status register. if cleared, the corresponding ?g is disabled from causing a hardware interrupt. if set, the corresponding ?g is enabled to cause a interrupt.
timer module (tim16b8cv2) s12xs family reference manual, rev. 1.10 476 freescale semiconductor 16.3.2.11 timer system control register 2 (tscr2) read: anytime write: anytime. module base + 0x000d 76543210 r toi 000 tcre pr2 pr1 pr0 w reset 00000000 = unimplemented or reserved figure 16-19. timer system control register 2 (tscr2) table 16-14. tscr2 field descriptions field description 7 toi timer over?w interrupt enable 0 interrupt inhibited. 1 hardware interrupt requested when tof ?g set. 3 tcre timer counter reset enable this bit allows the timer counter to be reset by a successful output compare 7 event. this mode of operation is similar to an up-counting modulus counter. 0 counter reset inhibited and counter free runs. 1 counter reset by a successful output compare 7. note: if tc7 = 0x0000 and tcre = 1, tcnt will stay at 0x0000 continuously. if tc7 = 0xffff and tcre = 1, tof will never be set when tcnt is reset from 0xffff to 0x0000. note: tcre=1 and tc7!=0, the tcnt cycle period will be tc7 x "prescaler counter width" + "1 bus clock", for a more detail explanation please refer to section 16.4.3, ?utput compare 2 pr[2:0] timer prescaler select ?these three bits select the frequency of the timer prescaler clock derived from the bus clock as shown in table 16-15 . table 16-15. timer clock selection pr2 pr1 pr0 timer clock 0 0 0 bus clock / 1 0 0 1 bus clock / 2 0 1 0 bus clock / 4 0 1 1 bus clock / 8 1 0 0 bus clock / 16 1 0 1 bus clock / 32 1 1 0 bus clock / 64 1 1 1 bus clock / 128
timer module (tim16b8cv2) s12xs family reference manual rev. 1.10 freescale semiconductor 477 note the newly selected prescale factor will not take effect until the next synchronized edge where all prescale counter stages equal zero. 16.3.2.12 main timer interrupt flag 1 (tflg1) read: anytime write: used in the clearing mechanism (set bits cause corresponding bits to be cleared). writing a zero will not affect current status of the bit. 16.3.2.13 main timer interrupt flag 2 (tflg2) tflg2 indicates when interrupt conditions have occurred. to clear a bit in the ?g register, write the bit to one while ten bit of tscr1 or paen bit of pactl is set to one. read: anytime write: used in clearing mechanism (set bits cause corresponding bits to be cleared). any access to tcnt will clear tflg2 register if the tffca bit in tscr register is set. module base + 0x000e 76543210 r c7f c6f c5f c4f c3f c2f c1f c0f w reset 00000000 figure 16-20. main timer interrupt flag 1 (tflg1) table 16-16. trlg1 field descriptions field description 7:0 c[7:0]f input capture/output compare channel ??flag ?these flags are set when an input capture or output compare event occurs. clearing requires writing a one to the corresponding ?g bit while ten or paen is set to one. when tffca bit in tscr register is set, a read from an input capture or a write into an output compare channel (0x0010?x001f) will cause the corresponding channel ?g cxf to be cleared. module base + 0x000f 76543210 r tof 0000000 w reset 00000000 unimplemented or reserved figure 16-21. main timer interrupt flag 2 (tflg2)
timer module (tim16b8cv2) s12xs family reference manual, rev. 1.10 478 freescale semiconductor 16.3.2.14 timer input capture/output compare registers high and low 0? (tcxh and tcxl) depending on the tios bit for the corresponding channel, these registers are used to latch the value of the free-running counter when a de?ed transition is sensed by the corresponding input capture edge detector or to trigger an output action for output compare. read: anytime write: anytime for output compare function.writes to these registers have no meaning or effect during input capture. all timer input capture/output compare registers are reset to 0x0000. note read/write access in byte mode for high byte should takes place before low byte otherwise it will give a different result. table 16-17. trlg2 field descriptions field description 7 tof timer over?w flag set when 16-bit free-running timer over?ws from 0xffff to 0x0000. clearing this bit requires writing a one to bit 7 of tflg2 register while the ten bit of tscr1 or paen bit of pactl is set to one (see also tcre control bit explanation.) module base + 0x0010 = tc0h 0x0012 = tc1h 0x0014 = tc2h 0x0016 = tc3h 0x0018 = tc4h 0x001a = tc5h 0x001c = tc6h 0x001e = tc7h 15 14 13 12 11 10 9 0 r bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 w reset 00000000 figure 16-22. timer input capture/output compare register x high (tcxh) module base + 0x0011 = tc0l 0x0013 = tc1l 0x0015 = tc2l 0x0017 = tc3l 0x0019 = tc4l 0x001b = tc5l 0x001d = tc6l 0x001f = tc7l 76543210 r bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 w reset 00000000 figure 16-23. timer input capture/output compare register x low (tcxl)
timer module (tim16b8cv2) s12xs family reference manual rev. 1.10 freescale semiconductor 479 16.3.2.15 16-bit pulse accumulator control register (pactl) when paen is set, the pact is enabled.the pact shares the input pin with ioc7. read: any time write: any time module base + 0x0020 76543210 r0 paen pamod pedge clk1 clk0 paovi pai w reset 00000000 unimplemented or reserved figure 16-24. 16-bit pulse accumulator control register (pactl) table 16-18. pactl field descriptions field description 6 paen pulse accumulator system enable ?paen is independent from ten. with timer disabled, the pulse accumulator can function unless pulse accumulator is disabled. 0 16-bit pulse accumulator system disabled. 1 pulse accumulator system enabled. 5 pamod pulse accumulator mode ?this bit is active only when the pulse accumulator is enabled (paen = 1). see table 16-19 . 0 event counter mode. 1 gated time accumulation mode. 4 pedge pulse accumulator edge control this bit is active only when the pulse accumulator is enabled (paen = 1). for pamod bit = 0 (event counter mode). see table 16-19 . 0 falling edges on ioc7 pin cause the count to be incremented. 1 rising edges on ioc7 pin cause the count to be incremented. for pamod bit = 1 (gated time accumulation mode). 0 ioc7 input pin high enables m (bus clock) divided by 64 clock to pulse accumulator and the trailing falling edge on ioc7 sets the paif ?g. 1 ioc7 input pin low enables m (bus clock) divided by 64 clock to pulse accumulator and the trailing rising edge on ioc7 sets the paif ?g. 3:2 clk[1:0] clock select bits refer to table 16-20 . 1 paov i pulse accumulator over?w interrupt enable 0 interrupt inhibited. 1 interrupt requested if paovf is set. 0 pa i pulse accumulator input interrupt enable 0 interrupt inhibited. 1 interrupt requested if paif is set.
timer module (tim16b8cv2) s12xs family reference manual, rev. 1.10 480 freescale semiconductor note if the timer is not active (ten = 0 in tscr), there is no divide-by-64 because the 64 clock is generated by the timer prescaler. for the description of paclk please refer figure 16-30 . if the pulse accumulator is disabled (paen = 0), the prescaler clock from the timer is always used as an input clock to the timer counter. the change from one selected clock to the other happens immediately after these bits are written. 16.3.2.16 pulse accumulator flag register (paflg) read: anytime write: anytime when the tffca bit in the tscr register is set, any access to the pacnt register will clear all the ?gs in the paflg register. timer module or pulse accumulator must stay enabled (ten=1 or paen=1) while clearing these bits. table 16-19. pin action pamod pedge pin action 0 0 falling edge 0 1 rising edge 1 0 div. by 64 clock enabled with pin high level 1 1 div. by 64 clock enabled with pin low level table 16-20. timer clock selection clk1 clk0 timer clock 0 0 use timer prescaler clock as timer counter clock 0 1 use paclk as input to timer counter clock 1 0 use paclk/256 as timer counter clock frequency 1 1 use paclk/65536 as timer counter clock frequency module base + 0x0021 76543210 r000000 paovf paif w reset 00000000 unimplemented or reserved figure 16-25. pulse accumulator flag register (paflg)
timer module (tim16b8cv2) s12xs family reference manual rev. 1.10 freescale semiconductor 481 16.3.2.17 pulse accumulators count registers (pacnt) read: anytime write: anytime these registers contain the number of active input edges on its input pin since the last reset. when pacnt over?ws from 0xffff to 0x0000, the interrupt ?g paovf in paflg (0x0021) is set. full count register access should take place in one clock cycle. a separate read/write for high byte and low byte will give a different result than accessing them as a word. note reading the pulse accumulator counter registers immediately after an active edge on the pulse accumulator input pin may miss the last count because the input has to be synchronized with the bus clock ?st. table 16-21. paflg field descriptions field description 1 paov f pulse accumulator over?w flag set when the 16-bit pulse accumulator over?ws from 0xffff to 0x0000. clearing this bit requires writing a one to this bit in the paflg register while ten bit of tscr1 or paen bit of pactl register is set to one. 0 paif pulse accumulator input edge flag set when the selected edge is detected at the ioc7 input pin.in event mode the event edge triggers paif and in gated time accumulation mode the trailing edge of the gate signal at the ioc7 input pin triggers paif. clearing this bit requires writing a one to this bit in the paflg register while ten bit of tscr1 or paen bit of pactl register is set to one. any access to the pacnt register will clear all the ?gs in this register when tffca bit in register tscr(0x0006) is set. module base + 0x0022 15 14 13 12 11 10 9 0 r pacnt15 pacnt14 pacnt13 pacnt12 pacnt11 pacnt10 pacnt9 pacnt8 w reset 00000000 figure 16-26. pulse accumulator count register high (pacnth) module base + 0x0023 76543210 r pacnt7 pacnt6 pacnt5 pacnt4 pacnt3 pacnt2 pacnt1 pacnt0 w reset 00000000 figure 16-27. pulse accumulator count register low (pacntl)
timer module (tim16b8cv2) s12xs family reference manual, rev. 1.10 482 freescale semiconductor 16.3.2.18 output compare pin disconnect register(ocpd) read: anytime write: anytime all bits reset to zero. 16.3.2.19 precision timer prescaler select register (ptpsr) read: anytime write: anytime all bits reset to zero. module base + 0x002c 76543210 r ocpd7 ocpd6 ocpd5 ocpd4 ocpd3 ocpd2 ocpd1 ocpd0 w reset 00000000 figure 16-28. ouput compare pin disconnect register (ocpd) table 16-22. ocpd field description field description ocpd[7:0} output compare pin disconnect bits 0 enables the timer channel port. ouptut compare action will occur on the channel pin. these bits do not affect the input capture or pulse accumulator functions 1 disables the timer channel port. output compare action will not occur on the channel pin, but the output compare ?g still become set . module base + 0x002e 76543210 r ptps7 ptps6 ptps5 ptps4 ptps3 ptps2 ptps1 ptps0 w reset 00000000 figure 16-29. precision timer prescaler select register (ptpsr)
timer module (tim16b8cv2) s12xs family reference manual rev. 1.10 freescale semiconductor 483 the prescaler can be calculated as follows depending on logical value of the ptps[7:0] and prnt bit: prnt = 1 : prescaler = ptps[7:0] + 1 table 16-24. precision timer prescaler selection examples when prnt = 1 16.4 functional description this section provides a complete functional description of the timer tim16b8cv2 block. please refer to the detailed timer block diagram in figure 16-30 as necessary. table 16-23. ptpsr field descriptions field description 7:0 ptps[7:0] precision timer prescaler select bits these eight bits specify the division rate of the main timer prescaler. these are effective only when the prnt bit of tscr1 is set to 1. table 16-24 shows some selection examples in this case. the newly selected prescale factor will not take effect until the next synchronized edge where all prescale counter stages equal zero. ptps7 ptps6 ptps5 ptps4 ptps3 ptps2 ptps1 ptps0 prescale factor 00000000 1 00000001 2 00000010 3 00000011 4 00000100 5 00000101 6 00000110 7 00000111 8 00001111 16 00011111 32 00111111 64 01111111 128 11111111 256
timer module (tim16b8cv2) s12xs family reference manual, rev. 1.10 484 freescale semiconductor figure 16-30. detailed timer block diagram 16.4.1 prescaler the prescaler divides the bus clock by 1,2,4,8,16,32,64 or 128. the prescaler select bits, pr[2:0], select the prescaler divisor. pr[2:0] are in timer system control register 2 (tscr2). prescaler channel 0 ioc0 pin 16-bit counter logic pr[2:1:0] divide-by-64 tc0 edge detect pacnt(hi):pacnt(lo) paovf pedge paovi ten pae 16-bit comparator tcnt(hi):tcnt(lo) channel 1 tc1 16-bit comparator 16-bit counter interrupt logic tof toi c0f c1f edge detect ioc1 pin logic edge detect cxf channel7 tc7 16-bit comparator c7f ioc7 pin logic edge detect om:ol0 tov0 om:ol1 tov1 om:ol7 tov7 edg1a edg1b edg7a edg7b edg0b tcre paif clear counter paif pai interrupt logic cxi interrupt request paovf ch. 7 compare ch.7 capture ch. 1 capture mux clk[1:0] paclk paclk/256 paclk/65536 ioc1 pin ioc0 pin ioc7 pin paclk paclk/256 paclk/65536 te ch. 1 compare ch. 0compare ch. 0 capture pa input channel2 edg0a channel 7 output compare ioc0 ioc1 ioc7 bus clock bus clock paovf paovi tof c0f c1f c7f
timer module (tim16b8cv2) s12xs family reference manual rev. 1.10 freescale semiconductor 485 the prescaler divides the bus clock by a prescalar value. prescaler select bits pr[2:0] of in timer system control register 2 (tscr2) are set to de?e a prescalar value that generates a divide by 1, 2, 4, 8, 16, 32, 64 and 128 when the prnt bit in tscr1 is disabled. by enabling the prnt bit of the tscr1 register, the performance of the timer can be enhanced. in this case, it is possible to set additional prescaler settings for the main timer counter in the present timer by using ptpsr[7:0] bits of ptpsr register. 16.4.2 input capture clearing the i/o (input/output) select bit, iosx, con?ures channel x as an input capture channel. the input capture function captures the time at which an external event occurs. when an active edge occurs on the pin of an input capture channel, the timer transfers the value in the timer counter into the timer channel registers, tcx. the minimum pulse width for the input capture input is greater than two bus clocks. an input capture on channel x sets the cxf ?g. the cxi bit enables the cxf ?g to generate interrupt requests. timer module or pulse accumulator must stay enabled (ten bit of tscr1 or paen bit of pactl regsiter must be set to one) while clearing cxf (writing one to cxf). 16.4.3 output compare setting the i/o select bit, iosx, con?ures channel x as an output compare channel. the output compare function can generate a periodic pulse with a programmable polarity, duration, and frequency. when the timer counter reaches the value in the channel registers of an output compare channel, the timer can set, clear, or toggle the channel pin if the corresponding ocpdx bit is set to zero. an output compare on channel x sets the cxf ?g. the cxi bit enables the cxf ?g to generate interrupt requests. timer module or pulse accumulator must stay enabled (ten bit of tscr1 or paen bit of pactl regsiter must be set to one) while clearing cxf (writing one to cxf). the output mode and level bits, omx and olx, select set, clear, toggle on output compare. clearing both omx and olx results in no output compare action on the output compare channel pin. setting a force output compare bit, focx, causes an output compare on channel x. a forced output compare does not set the channel ?g. a channel 7 event, which can be a counter over?w when ttov[7] is set or a successful output compare on channel 7, overrides output compares on all other output compare channels. the output compare 7 mask register masks the bits in the output compare 7 data register. the timer counter reset enable bit, tcre, enables channel 7 output compares to reset the timer counter. a channel 7 output compare can reset the timer counter even if the ioc7 pin is being used as the pulse accumulator input. writing to the timer port bit of an output compare pin does not affect the pin state. the value written is stored in an internal latch. when the pin becomes available for general-purpose output, the last value written to the bit appears at the pin. when tcre is set and tc7 is not equal to 0, then tcnt will cycle from 0 to tc7. when tcnt reaches tc7 value, it will last only one bus cycle then reset to 0.
timer module (tim16b8cv2) s12xs family reference manual, rev. 1.10 486 freescale semiconductor note: in figure 16-31 ,if pr[2:0] is equal to 0, one prescaler counter equal to one bus clock figure 16-31. the tcnt cycle diagram under tcre=1 condition 16.4.3.1 oc channel initialization internal register whose output drives ocx can be programmed before timer drives ocx. the desired state can be programmed to this internal register by writing a one to cforcx bit with tiosx, ocpdx and ten bits set to one. setting ocpdx to zero allows interal register to drive the programmed state to ocx. this allows a glitch free switch over of port from general purpose i/o to timer output once the ocpdx bit is set to zero. 16.4.4 pulse accumulator the pulse accumulator (pacnt) is a 16-bit counter that can operate in two modes: event counter mode ?counting edges of selected polarity on the pulse accumulator input pin, pai. gated time accumulation mode counting pulses from a divide-by-64 clock. the pamod bit selects the mode of operation. the minimum pulse width for the pai input is greater than two bus clocks. 16.4.5 event counter mode clearing the pamod bit con?ures the pacnt for event counter operation. an active edge on the ioc7 pin increments the pulse accumulator counter. the pedge bit selects falling edges or rising edges to increment the count. note the pacnt input and timer channel 7 use the same pin ioc7. to use the ioc7, disconnect it from the output logic by clearing the channel 7 output mode and output level bits, om7 and ol7. also clear the channel 7 output compare 7 mask bit, oc7m7. the pulse accumulator counter register re?ct the number of active input edges on the pacnt input pin since the last reset. the paovf bit is set when the accumulator rolls over from 0xffff to 0x0000. the pulse accumulator over?w interrupt enable bit, paovi, enables the paovf ?g to generate interrupt requests. tc7 0 1 ----- tc7-1 tc7 0 tc7 event tc7 event prescaler counter 1 bus clock
timer module (tim16b8cv2) s12xs family reference manual rev. 1.10 freescale semiconductor 487 note the pulse accumulator counter can operate in event counter mode even when the timer enable bit, ten, is clear. 16.4.6 gated time accumulation mode setting the pamod bit con?ures the pulse accumulator for gated time accumulation operation. an active level on the pacnt input pin enables a divided-by-64 clock to drive the pulse accumulator. the pedge bit selects low levels or high levels to enable the divided-by-64 clock. the trailing edge of the active level at the ioc7 pin sets the paif. the pai bit enables the paif ?g to generate interrupt requests. the pulse accumulator counter register re?ct the number of pulses from the divided-by-64 clock since the last reset. note the timer prescaler generates the divided-by-64 clock. if the timer is not active, there is no divided-by-64 clock. 16.5 resets the reset state of each individual bit is listed within section 16.3, ?emory map and register de?ition which details the registers and their bit ?lds. 16.6 interrupts this section describes interrupts originated by the tim16b8cv2 block. table 16-25 lists the interrupts generated by the tim16b8cv2 to communicate with the mcu. the tim16b8cv2 uses a total of 11 interrupt vectors. the interrupt vector offsets and interrupt numbers are chip dependent. table 16-25. tim16b8cv1 interrupts interrupt offset 1 1 chip dependent. vector 1 priority 1 source description c[7:0]f timer channel 7? active high timer channel interrupts 7? paovi pulse accumulator input active high pulse accumulator input interrupt paovf pulse accumulator over?w pulse accumulator over?w interrupt tof timer over?w timer over?w interrupt
timer module (tim16b8cv2) s12xs family reference manual, rev. 1.10 488 freescale semiconductor 16.6.1 channel [7:0] interrupt (c[7:0]f) this active high outputs will be asserted by the module to request a timer channel 7 ?0 interrupt to be serviced by the system controller. 16.6.2 pulse accumulator input interrupt (paovi) this active high output will be asserted by the module to request a timer pulse accumulator input interrupt to be serviced by the system controller. 16.6.3 pulse accumulator over?w interrupt (paovf) this active high output will be asserted by the module to request a timer pulse accumulator over?w interrupt to be serviced by the system controller. 16.6.4 timer over?w interrupt (tof) this active high output will be asserted by the module to request a timer over?w interrupt to be serviced by the system controller.
s12xs family reference manual, rev. 1.10 freescale semiconductor 489 chapter 17 voltage regulator (s12vregl3v3v1) table 17-1. revision history table 17.1 introduction module vreg_3v3 is a tri output voltage regulator that provides two separate 1.84v (typical) supplies differing in the amount of current that can be sourced and a 2.82v (typical) supply. the regulator input voltage range is from 3.3v up to 5v (typical). 17.1.1 features module vreg_3v3 includes these distinctive features: three parallel, linear voltage regulators with bandgap reference low-voltage detect (lvd) with low-voltage interrupt (lvi) power-on reset (por) low-voltage reset (lvr) high temperature detect (htd) with high temperature interrupt (hti) autonomous periodical interrupt (api) 17.1.2 modes of operation there are three modes vreg_3v3 can operate in: 1. full performance mode (fpm) (mcu is not in stop mode) the regulator is active, providing the nominal supply voltages with full current sourcing capability. features lvd (low-voltage detect), lvr (low-voltage reset), and por (power-on reset) and htd (high temperature detect) are available. the api is available. 2. reduced power mode (rpm) (mcu is in stop mode) the purpose is to reduce power consumption of the device. the output voltage may degrade to a lower value than in full performance mode, additionally the current sourcing capability is substantially reduced. only the por is available in this mode, lvd, lvr and htd are disabled. the api is available. rev. no. (item no.) date (submitted by) sections affected substantial change(s) v01.02 09 sep 2005 updates for api external access and lvr ?gs. v01.03 23 sep 2005 vae reset value is 1. v01.04 08 jun 2007 added temperature sensor to customer information
voltage regulator (s12vregl3v3v1) s12xs family reference manual, rev. 1.10 490 freescale semiconductor 3. shutdown mode controlled by vregen (see device level speci?ation for connectivity of vregen). this mode is characterized by minimum power consumption. the regulator outputs are in a high- impedance state, only the por feature is available, lvd, lvr and htd are disabled. the api internal rc oscillator clock is not available. this mode must be used to disable the chip internal regulator vreg_3v3, i.e., to bypass the vreg_3v3 to use external supplies. 17.1.3 block diagram figure 17-1 shows the function principle of vreg_3v3 by means of a block diagram. the regulator core reg consists of three parallel subblocks, reg1, reg2 and reg3, providing three independent output voltages.
voltage regulator (s12vregl3v3v1) s12xs family reference manual, rev. 1.10 freescale semiconductor 491 figure 17-1. vreg_3v3 block diagram lv r lv d por vddr vdd lvi por lvr ctrl vss vddpll vsspll vregen reg pin vdda reg: regulator core ctrl: regulator control lvd: low voltage detect lvr: low voltage reset por: power-on reset htd: high temperature detect c hti htd api api api: auto. periodical interrupt v bg api rate select bus clock reg2 reg1 reg3 vddf vssa vddx
voltage regulator (s12vregl3v3v1) s12xs family reference manual, rev. 1.10 492 freescale semiconductor 17.2 external signal description due to the nature of vreg_3v3 being a voltage regulator providing the chip internal power supply voltages, most signals are power supply signals connected to pads. table 17-2 shows all signals of vreg_3v3 associated with pins. note check device level speci?ation for connectivity of the signals. 17.2.1 vddr ?regulator power input pins signal vddr is the power input of vreg_3v3. all currents sourced into the regulator loads ?w through this pin. a chip external decoupling capacitor (100 nf...220 nf, x7r ceramic) between vddr and vssr (if vssr is not available vss) can smooth ripple on vddr. for entering shutdown mode, pin vddr should also be tied to ground on devices without vregen pin. 17.2.2 vdda, vssa ?regulator reference supply pins signals vdda/vssa , which are supposed to be relatively quiet, are used to supply the analog parts of the regulator. internal precision reference circuits are supplied from these signals. a chip external decoupling capacitor (100 nf...220 nf, x7r ceramic) between vdda and vssa can further improve the quality of this supply. 17.2.3 vdd, vss ?regulator output1 (core logic) pins signals vdd/vss are the primary outputs of vreg_3v3 that provide the power supply for the core logic. these signals are connected to device pins to allow external decoupling capacitors (220 nf, x7r ceramic). table 17-2. signal properties name function reset state pull up vddr power input (positive supply) vdda quiet input (positive supply) vssa quiet input (ground) vddx power input (positive supply) vdd primary output (positive supply) vss primary output (ground) vddf secondary output (positive supply) vddpll tertiary output (positive supply) vsspll tertiary output (ground) vregen (optional) optional regulator enable vreg_api (optional) vreg autonomous periodical interrupt output
voltage regulator (s12vregl3v3v1) s12xs family reference manual, rev. 1.10 freescale semiconductor 493 in shutdown mode an external supply driving vdd/vss can replace the voltage regulator. 17.2.4 vddf ?regulator output2 (nvm logic) pins signals vddf/vss are the secondary outputs of vreg_3v3 that provide the power supply for the nvm logic. these signals are connected to device pins to allow external decoupling capacitors (220 nf, x7r ceramic). in shutdown mode an external supply driving vddf/vss can replace the voltage regulator. 17.2.5 vddpll, vsspll ?regulator output3 (pll) pins signals vddpll/vsspll are the secondary outputs of vreg_3v3 that provide the power supply for the pll and oscillator. these signals are connected to device pins to allow external decoupling capacitors (100 nf...220 nf, x7r ceramic). in shutdown mode, an external supply driving vddpll/vsspll can replace the voltage regulator. 17.2.6 vddx ?power input pin signals vddx/vss are monitored by vreg_3v3 with the lvr feature. 17.2.7 vregen optional regulator enable pin this optional signal is used to shutdown vreg_3v3. in that case, vdd/vss and vddpll/vsspll must be provided externally. shutdown mode is entered with vregen being low. if vregen is high, the vreg_3v3 is either in full performance mode or in reduced power mode. for the connectivity of vregen, see device speci?ation. note switching from fpm or rpm to shutdown of vreg_3v3 and vice versa is not supported while mcu is powered. 17.2.8 vreg_api optional autonomous periodical interrupt output pin this pin provides the signal selected via apiea if system is set accordingly. see 17.3.2.3, autonomous periodical interrupt control register (vregapicl) and 17.4.8, autonomous periodical interrupt (api) for details. for the connectivity of vreg_api, see device speci?ation. 17.3 memory map and register de?ition this section provides a detailed description of all registers accessible in vreg_3v3. if enabled in the system, the vreg_3v3 will abort all read and write accesses to reserved registers within its memory slice. see device level speci?ation for details.
voltage regulator (s12vregl3v3v1) s12xs family reference manual, rev. 1.10 494 freescale semiconductor 17.3.1 module memory map a summary of the registers associated with the vreg_3v3 sub-block is shown in table 17-3 . detailed descriptions of the registers and bits are given in the subsections that follow address name bit 7 6 54321 bit 0 0x02f0 vreghtcl r0 0 vsel vae hten htds htie htif w 0x02f1 vregctrl r00000lvds lvie lvif w 0x02f2 vregapic l r apiclk 00 apifes apiea apife apie apif w 0x02f3 vregapit r r apitr5 apitr4 apitr3 apitr2 apitr1 apitr0 00 w 0x02f4 vregapir h r apir15 apir14 apir13 apir12 apir11 apir10 apir9 apir8 w 0x02f5 vregapir l r apir7 apir6 apir5 apir4 apir3 apir2 apir1 apir0 w 0x02f6 reserved 06 r00000000 w 0x02f7 vreghttr r htoen 000 httr3 httr2 httr1 httr0 w table 17-3. register summary
voltage regulator (s12vregl3v3v1) s12xs family reference manual, rev. 1.10 freescale semiconductor 495 17.3.2 register descriptions this section describes all the vreg_3v3 registers and their individual bits. 17.3.2.1 h igh t emperature control register (vreghtcl) the vreghtcl register allows to con?ure the vreg temperature sense features. 0x02f0 76543210 r0 0 vsel vae hten htds htie htif w reset 0 0 0 10000 = unimplemented or reserved table 17-4. vreghtcl field descriptions field description 7, 6 reserved these reserved bits are used for test purposes and writable only in special modes. they must remain clear for correct temperature sensor operation. 5 vsel voltage access select bit ?if set, the bandgap reference voltage v bg can be accessed internally (i.e. multiplexed to an internal analog to digital converter channel). the internal access must be enabled by bit vae. see device level speci?ation for connectivity. 0 an internal temperature proportional voltage v ht can be accessed internally if vae is set. 1 bandgap reference voltage v bg can be accessed internally if vae is set. 4 vae voltage access enable bit ?if set, the voltage selected by bit vsel can be accessed internally (i.e. multiplexed to an internal analog to digital converter channel). see device level speci?ation for connectivity. 0 voltage selected by vsel can not be accessed internally (i.e. external analog input is connected to analog to digital converter channel). 1 voltage selected by vsel can be accessed internally. 3 hten high temperature enable bit ?if set the temperature sense is enabled. 0 the temperature sense is disabled. 1 the temperature sense is enabled. 2 htds high temperature detect status bit this read-only status bit re?cts the temperature status. writes have no effect. 0 temperature t die is below level t htid or rpm or shutdown mode. 1 temperature t die is above level t htia and fpm. 1 htie high temperature interrupt enable bit 0 interrupt request is disabled. 1 interrupt will be requested whenever htif is set. 0 htif high temperature interrupt flag ?htif ?high temperature interrupt flag htif is set to 1 when htds status bit changes. this ?g can only be cleared by writing a 1.}writing a 0 has no effect. if enabled (htie=1), htif causes an interrupt request. 0 no change in htds bit. 1 htds bit has changed. note: on entering the reduced power mode the htif is not cleared by the vreg.
voltage regulator (s12vregl3v3v1) s12xs family reference manual, rev. 1.10 496 freescale semiconductor 17.3.2.2 control register (vregctrl) the vregctrl register allows the con?uration of the vreg_3v3 low-voltage detect features. 0x02f1 76543210 r00000lvds lvie lvif w reset 0 0 0 00000 = unimplemented or reserved figure 17-2. control register (vregctrl) table 17-5. vregctrl field descriptions field description 2 lvds low-voltage detect status bit ?this read-only status bit re?cts the input voltage. writes have no effect. 0 input voltage v dda is above level v lvid or rpm or shutdown mode. 1 input voltage v dda is below level v lvia and fpm. 1 lvie low-voltage interrupt enable bit 0 interrupt request is disabled. 1 interrupt will be requested whenever lvif is set. 0 lvif low-voltage interrupt flag lvif is set to 1 when lvds status bit changes. this ?g can only be cleared by writing a 1. writing a 0 has no effect. if enabled (lvie = 1), lvif causes an interrupt request. 0 no change in lvds bit. 1 lvds bit has changed. note: on entering the reduced power mode the lvif is not cleared by the vreg_3v3.
voltage regulator (s12vregl3v3v1) s12xs family reference manual, rev. 1.10 freescale semiconductor 497 17.3.2.3 autonomous periodical interrupt control register (vregapicl) the vregapicl register allows the con?uration of the vreg_3v3 autonomous periodical interrupt features. 0x02f2 76543210 r apiclk 00 apies apiea apife apie apif w reset 0 0 0 00000 = unimplemented or reserved figure 17-3. autonomous periodical interrupt control register (vregapicl) table 17-6. vregapicl field descriptions field description 7 apiclk autonomous periodical interrupt clock select bit ?selects the clock source for the api. writable only if apife = 0; apiclk cannot be changed if apife is set by the same write operation. 0 autonomous periodical interrupt clock used as source. 1 bus clock used as source. 4 apies autonomous periodical interrupt external select bit selects the waveform at the external pin.if set, at the external pin a clock is visible with 2 times the selected api period ( table 17-10 ). if not set, at the external pin will be a high pulse at the end of every selected period with the size of half of the min period ( table 17-10 ). see device level speci?ation for connectivity. 0 at the external periodic high pulses are visible, if apiea and apife is set. 1 at the external pin a clock is visible, if apiea and apife is set. 3 apiea autonomous periodical interrupt external access enable bit if set, the waveform selected by bit apies can be accessed externally. see device level speci?ation for connectivity. 0 waveform selected by apies can not be accessed externally. 1 waveform selected by apies can be accessed externally, if apife is set. 2 apife autonomous periodical interrupt feature enable bit ?enables the api feature and starts the api timer when set. 0 autonomous periodical interrupt is disabled. 1 autonomous periodical interrupt is enabled and timer starts running. 1 apie autonomous periodical interrupt enable bit 0 api interrupt request is disabled. 1 api interrupt will be requested whenever apif is set. 0 apif autonomous periodical interrupt flag ?apif is set to 1 when the in the api con?ured time has elapsed. this ?g can only be cleared by writing a 1 to it. clearing of the ?g has precedence over setting. writing a 0 has no effect. if enabled (apie = 1), apif causes an interrupt request. 0 api timeout has not yet occurred. 1 api timeout has occurred.
voltage regulator (s12vregl3v3v1) s12xs family reference manual, rev. 1.10 498 freescale semiconductor 17.3.2.4 autonomous periodical interrupt trimming register (vregapitr) the vregapitr register allows to trim the api timeout period. 0x02f3 76543210 r apitr5 apitr4 apitr3 apitr2 apitr1 apitr0 00 w reset 0 1 0 1 0 1 0 1 0 1 0 1 00 1. reset value is either 0 or preset by factory. see section 1 (device overview) for details. = unimplemented or reserved figure 17-4. autonomous periodical interrupt trimming register (vregapitr) table 17-7. vregapitr field descriptions field description 7? apitr[5:0] autonomous periodical interrupt period trimming bits ?see table 17-8 for trimming effects. table 17-8. trimming effect of apit bit trimming effect apitr[5] increases period apitr[4] decreases period less than apitr[5] increased it apitr[3] decreases period less than apitr[4] apitr[2] decreases period less than apitr[3] apitr[1] decreases period less than apitr[2] apitr[0] decreases period less than apitr[1]
voltage regulator (s12vregl3v3v1) s12xs family reference manual, rev. 1.10 freescale semiconductor 499 17.3.2.5 autonomous periodical interrupt rate high and low register (vregapirh / vregapirl) the vregapirh and vregapirl register allows the con?uration of the vreg_3v3 autonomous periodical interrupt rate. 0x02f4 76543210 r apir15 apir14 apir13 apir12 apir11 apir10 apir9 apir8 w reset 0 0 0 00000 = unimplemented or reserved figure 17-5. autonomous periodical interrupt rate high register (vregapirh) 0x02f5 76543210 r apir7 apir6 apir5 apir4 apir3 apir2 apir1 apir0 w reset 0 0 0 00000 figure 17-6. autonomous periodical interrupt rate low register (vregapirl) table 17-9. vregapirh / vregapirl field descriptions field description 15-0 apir[15:0] autonomous periodical interrupt rate bits these bits de?e the timeout period of the api. see table 17- 10 for details of the effect of the autonomous periodical interrupt rate bits. writable only if apife = 0 of vregapicl register.
voltage regulator (s12vregl3v3v1) s12xs family reference manual, rev. 1.10 500 freescale semiconductor the period can be calculated as follows depending of apiclk: period = 2*(apir[15:0] + 1) * 0.1 ms or period = 2*(apir[15:0] + 1) * bus clock period table 17-10. selectable autonomous periodical interrupt periods apiclk apir[15:0] selected period 0 0000 0.2 ms 1 1 when trimmed within speci?d accuracy. see electrical speci?ations for details. 0 0001 0.4 ms 1 0 0002 0.6 ms 1 0 0003 0.8 ms 1 0 0004 1.0 ms 1 0 0005 1.2 ms 1 0 ..... ..... 0 fffd 13106.8 ms 1 0 fffe 13107.0 ms 1 0 ffff 13107.2 ms 1 1 0000 2 * bus clock period 1 0001 4 * bus clock period 1 0002 6 * bus clock period 1 0003 8 * bus clock period 1 0004 10 * bus clock period 1 0005 12 * bus clock period 1 ..... ..... 1 fffd 131068 * bus clock period 1 fffe 131070 * bus clock period 1 ffff 131072 * bus clock period
voltage regulator (s12vregl3v3v1) s12xs family reference manual, rev. 1.10 freescale semiconductor 501 17.3.2.6 reserved 06 the reserved 06 is reserved for test purposes. 17.3.2.7 high temperature trimming register (vreghttr) the vreghttr register allows to trim the vreg temperature sense. fiption table 17-12. trimming effect 0x02f6 76543210 r00000000 w reset 0 0 0 00000 = unimplemented or reserved figure 17-7. reserved 06 0x02f7 76543210 r htoen 000 httr3 httr2 httr1 httr0 w reset 0 0 0 0 0 1 0 1 0 1 0 1 1. reset value is either 0 or preset by factory. see section 1 (device overview) for details. = unimplemented or reserved figure 17-8. vreghttr table 17-11. vreghttr ?ld descriptions field description 7 htoen high temperature offset enable bit ?if set the temperature sense offset is enabled 0 the temperature sense offset is disabled 1 the temperature sense offset is enabled 3? httr[3:0] high temperature trimming bits ?see table 23-16 for trimming effects. bit trimming effect httr[3] increases v ht twice of httr[2] httr[2] increases v ht twice of httr[1] httr[1] increases v ht twice of httr[0] httr[0] increases v ht (to compensate temperature offset)
voltage regulator (s12vregl3v3v1) s12xs family reference manual, rev. 1.10 502 freescale semiconductor 17.4 functional description 17.4.1 general module vreg_3v3 is a voltage regulator, as depicted in figure 17-1 . the regulator functional elements are the regulator core (reg), a low-voltage detect module (lvd), a control block (ctrl), a power-on reset module (por), and a low-voltage reset module (lvr)and a high temperature sensor (htd). 17.4.2 regulator core (reg) respectively its regulator core has three parallel, independent regulation loops (reg1,reg2 and reg3). reg1 and reg3 differ only in the amount of current that can be delivered. the regulators are linear regulator with a bandgap reference when operated in full performance mode. they act as a voltage clamp in reduced power mode. all load currents ?w from input vddr to vss or vsspll. the reference circuits are supplied by vdda and vssa. 17.4.2.1 full performance mode in full performance mode, the output voltage is compared with a reference voltage by an operational ampli?r. the ampli?d input voltage difference drives the gate of an output transistor. 17.4.2.2 reduced power mode in reduced power mode, the gate of the output transistor is connected directly to a reference voltage to reduce power consumption. mode switching from reduced power to full performance requires a transition time of t vup , if the voltage regulator is enabled. 17.4.3 low-voltage detect (lvd) subblock lvd is responsible for generating the low-voltage interrupt (lvi). lvd monitors the input voltage (v dda ? ssa ) and continuously updates the status ?g lvds. interrupt ?g lvif is set whenever status ?g lvds changes its value. the lvd is available in fpm and is inactive in reduced power mode or shutdown mode. 17.4.4 power-on reset (por) this functional block monitors vdd. if v dd is below v pord , por is asserted; if v dd exceeds v pord , the por is deasserted. por asserted forces the mcu into reset. por deasserted will trigger the power- on sequence. 17.4.5 low-voltage reset (lvr) block lvr monitors the supplies vdd, vddx and vddf. if one (or more) drops below its corresponding assertion level, signal lvr asserts; if all vdd,vddx and vddf supplies are above their
voltage regulator (s12vregl3v3v1) s12xs family reference manual, rev. 1.10 freescale semiconductor 503 corresponding deassertion levels, signal lvr deasserts. the lvr function is available only in full performance mode. 17.4.6 htd - high temperature detect subblock htd is responsible for generating the high temperature interrupt (hti). htd monitors the die temperature t die and continuously updates the status ?g htds. interrupt ?g htif is set whenever status ?g htds changes its value. the htd is available in fpm and is inactive in reduced power mode and shutdown mode. the ht trimming bits httr[3:0] can be set so that the temperature offset is zero, if accurate temperature measurement is desired. see table 23-16 for the trimming effect of apitr. 17.4.7 regulator control (ctrl) this part contains the register block of vreg_3v3 and further digital functionality needed to control the operating modes. ctrl also represents the interface to the digital core logic. 17.4.8 autonomous periodical interrupt (api) subblock api can generate periodical interrupts independent of the clock source of the mcu. to enable the timer, the bit apife needs to be set. the api timer is either clocked by a trimmable internal rc oscillator or the bus clock. timer operation will freeze when mcu clock source is selected and bus clock is turned off. see crg speci?ation for details. the clock source can be selected with bit apiclk. apiclk can only be written when apife is not set. the apir[15:0] bits determine the interrupt period. apir[15:0] can only be written when apife is cleared. as soon as apife is set, the timer starts running for the period selected by apir[15:0] bits. when the con?ured time has elapsed, the ?g apif is set. an interrupt, indicated by ?g apif = 1, is triggered if interrupt enable bit apie = 1. the timer is started automatically again after it has set apif. the procedure to change apiclk or apir[15:0] is ?st to clear apife, then write to apiclk or apir[15:0], and afterwards set apife. the api trimming bits apitr[5:0] must be set so the minimum period equals 0.2 ms if stable frequency is desired. see table 17-8 for the trimming effect of apitr. note the ?st period after enabling the counter by apife might be reduced by api start up delay t sdel . the api internal rc oscillator clock is not available if vreg_3v3 is in shutdown mode.
voltage regulator (s12vregl3v3v1) s12xs family reference manual, rev. 1.10 504 freescale semiconductor it is possible to generate with the api a waveform at an external pin by enabling the api by setting apife and enabling the external access with setting apiea. by setting apies the waveform can be selected. if apies is set, then at the external pin a clock is visible with 2 times the selected api period ( table 17-10 ). if apies is not set, then at the external pin will be a high pulse at the end of every selected period with the size of half of the min period ( table 17-10 ). see device level speci?ation for connectivity. 17.4.9 resets this section describes how vreg_3v3 controls the reset of the mcu.the reset values of registers and signals are provided in section 17.3, ?emory map and register de?ition . possible reset sources are listed in table 17-13 . 17.4.10 description of reset operation 17.4.10.1 power-on reset (por) during chip power-up the digital core may not work if its supply voltage v dd is below the por deassertion level (v pord ). therefore, signal por, which forces the other blocks of the device into reset, is kept high until v dd exceeds v pord . the mcu will run the start-up sequence after por deassertion. the power-on reset is active in all operation modes of vreg_3v3. 17.4.10.2 low-voltage reset (lvr) for details on low-voltage reset, see section 17.4.5, ?ow-voltage reset (lvr) . 17.4.11 interrupts this section describes all interrupts originated by vreg_3v3. the interrupt vectors requested by vreg_3v3 are listed in table 17-14 . vector addresses and interrupt priorities are de?ed at mcu level. table 17-13. reset sources reset source local enable power-on reset always active low-voltage reset available only in full performance mode table 17-14. interrupt vectors interrupt source local enable low-voltage interrupt (lvi) lvie = 1; available only in full performance mode high temperature interrupt (hti) htie=1; available only in full performance mode autonomous periodical interrupt (api) apie = 1
voltage regulator (s12vregl3v3v1) s12xs family reference manual, rev. 1.10 freescale semiconductor 505 17.4.11.1 low-voltage interrupt (lvi) in fpm, vreg_3v3 monitors the input voltage v dda . whenever v dda drops below level v lvia, the status bit lvds is set to 1. on the other hand, lvds is reset to 0 when v dda rises above level v lvid .an interrupt, indicated by ?g lvif = 1, is triggered by any change of the status bit lvds if interrupt enable bit lvie = 1. note on entering the reduced power mode, the lvif is not cleared by the vreg_3v3. 17.4.11.2 hti - high temperature interrupt in fpm vreg monitors the die temperature t die . whenever t die exceeds level t htia the status bit htds is set to 1. vice versa, htds is reset to 0 when t die get below level t htid . an interrupt, indicated by ?g htif=1, is triggered by any change of the status bit htds if interrupt enable bit htie=1. note on entering the reduced power mode the htif is not cleared by the vreg. 17.4.11.3 autonomous periodical interrupt (api) as soon as the con?ured timeout period of the api has elapsed, the apif bit is set. an interrupt, indicated by ?g apif = 1, is triggered if interrupt enable bit apie = 1.
voltage regulator (s12vregl3v3v1) s12xs family reference manual, rev. 1.10 506 freescale semiconductor
s12xs family reference manual, rev. 1.10 freescale semiconductor 507 chapter 18 256 kbyte flash module (s12xftmr256k1v1) 18.1 introduction the ftmr256k1 module implements the following: 256 kbytes of p-flash (program flash) memory 8 kbytes of d-flash (data flash) memory the flash memory is ideal for single-supply applications allowing for ?ld reprogramming without requiring external high voltage sources for program or erase operations. the flash module includes a memory controller that executes commands to modify flash memory contents. the user interface to the memory controller consists of the indexed flash common command object (fccob) register which is written to with the command, global address, data, and any required command parameters. the memory controller must complete the execution of a command before the fccob register can be written to with a new command. table 18-1. revision history revision number revision date sections affected description of changes v01.04 03 jan 2008 - cosmetic changes v01.05 19 dec 2008 18.1/18-507 18.4.2.4/18-542 18.4.2.6/18-544 18.4.2.11/18-54 7 18.4.2.11/18-54 7 18.4.2.11/18-54 7 - clarify single bit fault correction for p-flash phrase - add statement concerning code runaway when executing read once, program once, and verify backdoor access key commands from flash block containing associated ?lds - relate key 0 to associated backdoor comparison key address - change ?ower down reset?to ?eset?in section 18.4.2.11 v01.06 25 sep 2009 18.3.2/18-514 18.3.2.1/18-516 18.4.1.2/18-536 18.6/18-556 the following changes were made to clarify module behavior related to flash register access during reset sequence and while flash commands are active: - add caution concerning register writes while command is active - writes to fclkdiv are allowed during reset sequence while ccif is clear - add caution concerning register writes while command is active - writes to fccobix, fccobhi, fccoblo registers are ignored during reset sequence
s12xs family reference manual, rev. 1.10 freescale semiconductor 508 caution a flash word or phrase must be in the erased state before being programmed. cumulative programming of bits within a flash word or phrase is not allowed. the flash memory may be read as bytes, aligned words, or misaligned words. read access time is one bus cycle for bytes and aligned words, and two bus cycles for misaligned words. for flash memory, an erased bit reads 1 and a programmed bit reads 0. it is not possible to read from a flash block while any command is executing on that speci? flash block. it is possible to read from a flash block while a command is executing on a different flash block. both p-flash and d-flash memories are implemented with error correction codes (ecc) that can resolve single bit faults and detect double bit faults. for p-flash memory, the ecc implementation requires that programming be done on an aligned 8 byte basis (a flash phrase). since p-flash memory is always read by phrase, only one single bit fault in the phrase containing the byte or word accessed will be corrected. 18.1.1 glossary command write sequence ?an mcu instruction sequence to execute built-in algorithms (including program and erase) on the flash memory. d-flash memory ?the d-flash memory constitutes the nonvolatile memory store for data. d-flash sector the d-flash sector is the smallest portion of the d-flash memory that can be erased. the d-flash sector consists of four 64 byte rows for a total of 256 bytes. nvm command mode an nvm mode using the cpu to setup the fccob register to pass parameters required for flash command execution. phrase an aligned group of four 16-bit words within the p-flash memory. each phrase includes eight ecc bits for single bit fault correction and double bit fault detection within the phrase. p-flash memory the p-flash memory constitutes the main nonvolatile memory store for applications. p-flash sector ?the p-flash sector is the smallest portion of the p-flash memory that can be erased. each p-flash sector contains 1024 bytes. program ifr ?nonvolatile information register located in the p-flash block that contains the device id, version id, and the program once ?ld. the program ifr is visible in the global memory map by setting the pgmifron bit in the mmcctl1 register.
256 kbyte flash module (s12xftmr256k1v1) s12xs family reference manual, rev. 1.10 freescale semiconductor 509 18.1.2 features 18.1.2.1 p-flash features 256 kbytes of p-flash memory composed of one 256 kbyte flash block divided into 256 sectors of 1024 bytes single bit fault correction and double bit fault detection within a 64-bit phrase during read operations automated program and erase algorithm with verify and generation of ecc parity bits fast sector erase and phrase program operation flexible protection scheme to prevent accidental program or erase of p-flash memory 18.1.2.2 d-flash features 8 kbytes of d-flash memory composed of one 8 kbyte flash block divided into 32 sectors of 256 bytes single bit fault correction and double bit fault detection within a word during read operations automated program and erase algorithm with verify and generation of ecc parity bits fast sector erase and word program operation protection scheme to prevent accidental program or erase of d-flash memory ability to program up to four words in a burst sequence 18.1.2.3 other flash module features no external high-voltage power supply required for flash memory program and erase operations interrupt generation on flash command completion and flash error detection security mechanism to prevent unauthorized access to the flash memory 18.1.3 block diagram the block diagram of the flash module is shown in figure 18-1 .
256 kbyte flash module (s12xftmr256k1v1) s12xs family reference manual, rev. 1.10 510 freescale semiconductor figure 18-1. ftmr256k1 block diagram 18.2 external signal description the flash module contains no signals that connect off-chip. 18.3 memory map and registers this section describes the memory map and registers for the flash module. read data from unimplemented memory space in the flash module is unde?ed. write access to unimplemented or reserved memory space in the flash module will be ignored by the flash module. oscillator clock divider clock (xtal) command interrupt request fclk protection security registers flash interface p-flash 32kx72 sector 0 sector 1 sector 127 sector 0 sector 1 sector 127 16bit internal bus 16kx72 16kx72 error interrupt request cpu memory controller d-flash 4kx22 sector 0 sector 1 sector 31 scratch ram 384x16
256 kbyte flash module (s12xftmr256k1v1) s12xs family reference manual, rev. 1.10 freescale semiconductor 511 18.3.1 module memory map the s12x architecture places the p-flash memory between global addresses 0x7c_0000 and 0x7f_ffff as shown in table 18-2 . the p-flash memory map is shown in figure 18-2 . the fprot register, described in section 18.3.2.9 , can be set to protect regions in the flash memory from accidental program or erase. three separate memory regions, one growing upward from global address 0x7f_8000 in the flash memory (called the lower region), one growing downward from global address 0x7f_ffff in the flash memory (called the higher region), and the remaining addresses in the flash memory, can be activated for protection. the flash memory addresses covered by these protectable regions are shown in the p-flash memory map. the higher address region is mainly targeted to hold the boot loader code since it covers the vector space. default protection settings as well as security information that allows the mcu to restrict access to the flash module are stored in the flash con?uration ?ld as described in table 18-3 . table 18-2. p-flash memory addressing global address size (bytes) description 0x7c_0000 ?0x7f_ffff 256 k p-flash block 0 contains flash con?uration field (see table 18-3 ) table 18-3. flash con?uration field 1 1 older versions may have swapped protection byte addresses global address size (bytes) description 0x7f_ff00 ?0x7f_ff07 8 backdoor comparison key refer to section 18.4.2.11, ?erify backdoor access key command , and section 18.5.1, ?nsecuring the mcu using backdoor key access 0x7f_ff08 0x7f_ff0b 2 2 0x7ff08 - 0x7f_ff0f form a flash phrase and must be programmed in a single command write sequence. each byte in the 0x7f_ff08 - 0x7f_ff0b reserved ?ld should be programmed to 0xff. 4 reserved 0x7f_ff0c 2 1 p-flash protection byte . refer to section 18.3.2.9, ?-flash protection register (fprot) 0x7f_ff0d 2 1 d-flash protection byte . refer to section 18.3.2.10, ?-flash protection register (dfprot) 0x7f_ff0e 2 1 flash nonvolatile byte refer to section 18.3.2.15, ?lash option register (fopt) 0x7f_ff0f 2 1 flash security byte refer to section 18.3.2.2, ?lash security register (fsec)
256 kbyte flash module (s12xftmr256k1v1) s12xs family reference manual, rev. 1.10 512 freescale semiconductor figure 18-2. p-flash memory map flash con?uration field 0x7f_c000 flash protected/unprotected lower region 1, 2, 4, 8 kbytes 0x7f_8000 0x7f_9000 0x7f_8400 0x7f_8800 0x7f_a000 p-flash end = 0x7f_ffff 0x7f_f800 0x7f_f000 0x7f_e000 flash protected/unprotected higher region 2, 4, 8, 16 kbytes flash protected/unprotected region 8 kbytes (up to 29 kbytes) 16 bytes (0x7f_ff00 - 0x7f_ff0f) flash protected/unprotected region 224 kbytes p-flash start = 0x7c_0000
256 kbyte flash module (s12xftmr256k1v1) s12xs family reference manual, rev. 1.10 freescale semiconductor 513 table 18-4. program ifr fields global address (pgmifron) size (bytes) field description 0x40_0000 ?0x40_0007 8 device id 0x40_0008 ?0x40_00e7 224 reserved 0x40_00e8 ?0x40_00e9 2 version id 0x40_00ea ?0x40_00ff 22 reserved 0x40_0100 ?0x40_013f 64 program once field refer to section 18.4.2.6, ?rogram once command 0x40_0140 ?0x40_01ff 192 reserved table 18-5. d-flash and memory controller resource fields global address size (bytes) description 0x10_0000 ?0x10_1fff 8,192 d-flash memory 0x10_2000 ?0x11_ffff 122,880 reserved 0x12_0000 ?0x12_007f 128 d-flash nonvolatile information register (dfifron 1 = 1) 1 mmcctl1 register bit 0x12_0080 ?0x12_0fff 3,968 reserved 0x12_1000 ?0x12_1fff 4,096 reserved 0x12_2000 ?0x12_3cff 7,242 reserved 0x12_3d00 ?0x12_3fff 768 memory controller scratch ram (mgramon 1 = 1) 0x12_4000 ?0x12_e7ff 43,008 reserved 0x12_e800 ?0x12_ffff 6,144 reserved 0x13_0000 ?0x13_ffff 65,536 reserved
256 kbyte flash module (s12xftmr256k1v1) s12xs family reference manual, rev. 1.10 514 freescale semiconductor figure 18-3. d-flash and memory controller resource memory map 18.3.2 register descriptions the flash module contains a set of 20 control and status registers located between flash module base + 0x0000 and 0x0013. a summary of the flash module registers is given in figure 18-4 with detailed descriptions in the following subsections. caution writes to any flash register must be avoided while a flash command is active (ccif=0) to prevent corruption of flash register contents and memory controller behavior. address & name 76543210 0x0000 fclkdiv r fdivld fdiv6 fdiv5 fdiv4 fdiv3 fdiv2 fdiv1 fdiv0 w 0x0001 fsec r keyen1 keyen0 rnv5 rnv4 rnv3 rnv2 sec1 sec0 w figure 18-4. ftmr256k1 register summary 0x12_ffff 0x12_4000 0x12_1000 memory controller scratch ram (mgramon) 768 bytes d-flash nonvolatile information register (dfifron) 128 bytes d-flash memory 8 kbytes d-flash start = 0x10_0000 0x12_0000 0x12_2000 0x12_e800 d-flash end = 0x10_1fff
256 kbyte flash module (s12xftmr256k1v1) s12xs family reference manual, rev. 1.10 freescale semiconductor 515 0x0002 fccobix r0 0 0 0 0 ccobix2 ccobix1 ccobix0 w 0x0003 feccrix r0 0 0 0 0 eccrix2 eccrix1 eccrix0 w 0x0004 fcnfg r ccie 00 ignsf 00 fdfd fsfd w 0x0005 fercnfg r 0 dfdie sfdie w 0x0006 fstat r ccif 0 accerr fpviol mgbusy rsvd mgstat1 mgstat0 w 0x0007 ferstat r0 0 0 0 0 0 dfdif sfdif w 0x0008 fprot r fpopen rnv6 fphdis fphs1 fphs0 fpldis fpls1 fpls0 w 0x0009 dfprot r dpopen 00 dps4 dps3 dps2 dps1 dps0 w 0x000a fccobhi r ccob15 ccob14 ccob13 ccob12 ccob11 ccob10 ccob9 ccob8 w 0x000b fccoblo r ccob7 ccob6 ccob5 ccob4 ccob3 ccob2 ccob1 ccob0 w 0x000c frsv0 r00000000 w 0x000d frsv1 r00000000 w 0x000e feccrhi r eccr15 eccr14 eccr13 eccr12 eccr11 eccr10 eccr9 eccr8 w 0x000f feccrlo r eccr7 eccr6 eccr5 eccr4 eccr3 eccr2 eccr1 eccr0 w address & name 76543210 figure 18-4. ftmr256k1 register summary (continued)
256 kbyte flash module (s12xftmr256k1v1) s12xs family reference manual, rev. 1.10 516 freescale semiconductor 18.3.2.1 flash clock divider register (fclkdiv) the fclkdiv register is used to control timed events in program and erase algorithms. all bits in the fclkdiv register are readable, bits 6? are write once and bit 7 is not writable. 0x0010 fopt r nv7 nv6 nv5 nv4 nv3 nv2 nv1 nv0 w 0x0011 frsv2 r00000000 w 0x0012 frsv3 r00000000 w 0x0013 frsv4 r00000000 w = unimplemented or reserved offset module base + 0x0000 76543210 r fdivld fdiv[6:0] w reset 00000000 = unimplemented or reserved figure 18-5. flash clock divider register (fclkdiv) table 18-6. fclkdiv field descriptions field description 7 fdivld clock divider loaded 0 fclkdiv register has not been written 1 fclkdiv register has been written since the last reset 6? fdiv[6:0] clock divider bits ?fdiv[6:0] must be set to effectively divide oscclk down to generate an internal flash clock, fclk, with a target frequency of 1 mhz for use by the flash module to control timed events during program and erase algorithms. table 18-7 shows recommended values for fdiv[6:0] based on oscclk frequency. please refer to section 18.4.1, ?lash command operations , for more information. address & name 76543210 figure 18-4. ftmr256k1 register summary (continued)
256 kbyte flash module (s12xftmr256k1v1) s12xs family reference manual, rev. 1.10 freescale semiconductor 517 caution the fclkdiv register should never be written while a flash command is executing (ccif=0). the fclkdiv register is writable during the flash reset sequence even though ccif is clear.
256 kbyte flash module (s12xftmr256k1v1) s12xs family reference manual, rev. 1.10 518 freescale semiconductor table 18-7. fdiv vs oscclk frequency oscclk frequency (mhz) fdiv[6:0] oscclk frequency (mhz) fdiv[6:0] min 1 1 fdiv shown generates an fclk frequency of >0.8 mhz max 2 2 fdiv shown generates an fclk frequency of 1.05 mhz min 1 max 2 1.60 2.10 0x01 33.60 34.65 0x20 2.40 3.15 0x02 34.65 35.70 0x21 3.20 4.20 0x03 35.70 36.75 0x22 4.20 5.25 0x04 36.75 37.80 0x23 5.25 6.30 0x05 37.80 38.85 0x24 6.30 7.35 0x06 38.85 39.90 0x25 7.35 8.40 0x07 39.90 40.95 0x26 8.40 9.45 0x08 40.95 42.00 0x27 9.45 10.50 0x09 42.00 43.05 0x28 10.50 11.55 0x0a 43.05 44.10 0x29 11.55 12.60 0x0b 44.10 45.15 0x2a 12.60 13.65 0x0c 45.15 46.20 0x2b 13.65 14.70 0x0d 46.20 47.25 0x2c 14.70 15.75 0x0e 47.25 48.30 0x2d 15.75 16.80 0x0f 48.30 49.35 0x2e 16.80 17.85 0x10 49.35 50.40 0x2f 17.85 18.90 0x11 18.90 19.95 0x12 19.95 21.00 0x13 21.00 22.05 0x14 22.05 23.10 0x15 23.10 24.15 0x16 24.15 25.20 0x17 25.20 26.25 0x18 26.25 27.30 0x19 27.30 28.35 0x1a 28.35 29.40 0x1b 29.40 30.45 0x1c 30.45 31.50 0x1d 31.50 32.55 0x1e 32.55 33.60 0x1f
256 kbyte flash module (s12xftmr256k1v1) s12xs family reference manual, rev. 1.10 freescale semiconductor 519 18.3.2.2 flash security register (fsec) the fsec register holds all bits associated with the security of the mcu and flash module. all bits in the fsec register are readable but not writable. during the reset sequence, the fsec register is loaded with the contents of the flash security byte in the flash configuration field at global address 0x7f_ff0f located in p-flash memory (see table 18-3 ) as indicated by reset condition f in figure 18-6 . if a double bit fault is detected while reading the p-flash phrase containing the flash security byte during the reset sequence, all bits in the fsec register will be set to leave the flash module in a secured state with backdoor key access disabled. offset module base + 0x0001 76543210 r keyen[1:0] rnv[5:2] sec[1:0] w reset f f ffffff = unimplemented or reserved figure 18-6. flash security register (fsec) table 18-8. fsec field descriptions field description 7? keyen[1:0] backdoor key security enable bits the keyen[1:0] bits de?e the enabling of backdoor key access to the flash module as shown in table 18-9 . 5? rnv[5:2} reserved nonvolatile bits ?the rnv bits should remain in the erased state for future enhancements. 1? sec[1:0] flash security bits ?the sec[1:0] bits de?e the security state of the mcu as shown in table 18-10 . if the flash module is unsecured using backdoor key access, the sec bits are forced to 10. table 18-9. flash keyen states keyen[1:0] status of backdoor key access 00 disabled 01 disabled 1 1 preferred keyen state to disable backdoor key access. 10 enabled 11 disabled table 18-10. flash security states sec[1:0] status of security 00 secured 01 secured 1 10 unsecured 11 secured
256 kbyte flash module (s12xftmr256k1v1) s12xs family reference manual, rev. 1.10 520 freescale semiconductor the security function in the flash module is described in section 18.5 . 18.3.2.3 flash ccob index register (fccobix) the fccobix register is used to index the fccob register for flash memory operations. ccobix bits are readable and writable while remaining bits read 0 and are not writable. 18.3.2.4 flash eccr index register (feccrix) the feccrix register is used to index the feccr register for ecc fault reporting. eccrix bits are readable and writable while remaining bits read 0 and are not writable. 1 preferred sec state to set mcu to secured state. offset module base + 0x0002 76543210 r00000 ccobix[2:0] w reset 00000000 = unimplemented or reserved figure 18-7. fccob index register (fccobix) table 18-11. fccobix field descriptions field description 2? ccobix[1:0] common command register index the ccobix bits are used to select which word of the fccob register array is being read or written to. see section 18.3.2.11, ?lash common command object register (fccob) , for more details. offset module base + 0x0003 76543210 r00000 eccrix[2:0] w reset 00000000 = unimplemented or reserved figure 18-8. feccr index register (feccrix) table 18-12. feccrix field descriptions field description 2-0 eccrix[2:0] ecc error register index ?the eccrix bits are used to select which word of the feccr register array is being read. see section 18.3.2.14, ?lash ecc error results register (feccr) , for more details.
256 kbyte flash module (s12xftmr256k1v1) s12xs family reference manual, rev. 1.10 freescale semiconductor 521 18.3.2.5 flash con?uration register (fcnfg) the fcnfg register enables the flash command complete interrupt and forces ecc faults on flash array read access from the cpu or xgate. ccie, ignsf, fdfd, and fsfd bits are readable and writable while remaining bits read 0 and are not writable. 18.3.2.6 flash error con?uration register (fercnfg) the fercnfg register enables the flash error interrupts for the ferstat flags. offset module base + 0x0004 76543210 r ccie 00 ignsf 00 fdfd fsfd w reset 00000000 = unimplemented or reserved figure 18-9. flash con?uration register (fcnfg) table 18-13. fcnfg field descriptions field description 7 ccie command complete interrupt enable ?the ccie bit controls interrupt generation when a flash command has completed. 0 command complete interrupt disabled 1 an interrupt will be requested whenever the ccif ?g in the fstat register is set (see section 18.3.2.7 ) 4 ignsf ignore single bit fault ?the ignsf controls single bit fault reporting in the ferstat register (see section 18.3.2.8 ). 0 all single bit faults detected during array reads are reported 1 single bit faults detected during array reads are not reported and the single bit fault interrupt will not be generated 1 fdfd force double bit fault detect the fdfd bit allows the user to simulate a double bit fault during flash array read operations and check the associated interrupt routine. the fdfd bit is cleared by writing a 0 to fdfd. the feccr registers will not be updated during the flash array read operation with fdfd set unless an actual double bit fault is detected. 0 flash array read operations will set the dfdif ?g in the ferstat register only if a double bit fault is detected 1 any flash array read operation will force the dfdif ?g in the ferstat register to be set (see section 18.3.2.7 ) and an interrupt will be generated as long as the dfdie interrupt enable in the fercnfg register is set (see section 18.3.2.6 ) 0 fsfd force single bit fault detect the fsfd bit allows the user to simulate a single bit fault during flash array read operations and check the associated interrupt routine. the fsfd bit is cleared by writing a 0 to fsfd. the feccr registers will not be updated during the flash array read operation with fsfd set unless an actual single bit fault is detected. 0 flash array read operations will set the sfdif ?g in the ferstat register only if a single bit fault is detected 1 flash array read operation will force the sfdif ?g in the ferstat register to be set (see section 18.3.2.7 ) and an interrupt will be generated as long as the sfdie interrupt enable in the fercnfg register is set (see section 18.3.2.6 )
256 kbyte flash module (s12xftmr256k1v1) s12xs family reference manual, rev. 1.10 522 freescale semiconductor all assigned bits in the fercnfg register are readable and writable. 18.3.2.7 flash status register (fstat) the fstat register reports the operational status of the flash module. ccif, accerr, and fpviol bits are readable and writable, mgbusy and mgstat bits are readable but not writable, while remaining bits read 0 and are not writable. offset module base + 0x0005 76543210 r 0 dfdie sfdie w reset 00000000 = unimplemented or reserved figure 18-10. flash error con?uration register (fercnfg) table 18-14. fercnfg field descriptions field description 1 dfdie double bit fault detect interrupt enable the dfdie bit controls interrupt generation when a double bit fault is detected during a flash block read operation. 0 dfdif interrupt disabled 1 an interrupt will be requested whenever the dfdif ?g is set (see section 18.3.2.8 ) 0 sfdie single bit fault detect interrupt enable the sfdie bit controls interrupt generation when a single bit fault is detected during a flash block read operation. 0 sfdif interrupt disabled whenever the sfdif ?g is set (see section 18.3.2.8 ) 1 an interrupt will be requested whenever the sfdif ?g is set (see section 18.3.2.8 ) offset module base + 0x0006 76543210 r ccif 0 accerr fpviol mgbusy rsvd mgstat[1:0] w reset 1000000 1 1 reset value can deviate from the value shown if a double bit fault is detected during the reset sequence (see section 18.6 ). 0 1 = unimplemented or reserved figure 18-11. flash status register (fstat)
256 kbyte flash module (s12xftmr256k1v1) s12xs family reference manual, rev. 1.10 freescale semiconductor 523 18.3.2.8 flash error status register (ferstat) the ferstat register re?cts the error status of internal flash operations. all ?gs in the ferstat register are readable and only writable to clear the ?g. table 18-15. fstat field descriptions field description 7 ccif command complete interrupt flag ?the ccif ?g indicates that a flash command has completed. the ccif ?g is cleared by writing a 1 to ccif to launch a command and ccif will stay low until command completion or command violation. 0 flash command in progress 1 flash command has completed 5 accerr flash access error flag ?the accerr bit indicates an illegal access has occurred to the flash memory caused by either a violation of the command write sequence (see section 18.4.1.2 ) or issuing an illegal flash command. while accerr is set, the ccif ?g cannot be cleared to launch a command. the accerr bit is cleared by writing a 1 to accerr. writing a 0 to the accerr bit has no effect on accerr. 0 no access error detected 1 access error detected 4 fpviol flash protection violation flag ?he fpviol bit indicates an attempt was made to program or erase an address in a protected area of p-flash or d-flash memory during a command write sequence. the fpviol bit is cleared by writing a 1 to fpviol. writing a 0 to the fpviol bit has no effect on fpviol. while fpviol is set, it is not possible to launch a command or start a command write sequence. 0 no protection violation detected 1 protection violation detected 3 mgbusy memory controller busy flag ?the mgbusy ?g re?cts the active state of the memory controller . 0 memory controller is idle 1 memory controller is busy executing a flash command (ccif = 0) 2 rsvd reserved bit ?this bit is reserved and always reads 0 . 1? mgstat[1:0] memory controller command completion status flag one or more mgstat ?g bits are set if an error is detected during execution of a flash command or during the flash reset sequence. see section 18.4.2, ?lash command description , and section 18.6, ?nitialization ?for details. offset module base + 0x0007 76543210 r000000 dfdif sfdif w reset 00000000 = unimplemented or reserved figure 18-12. flash error status register (ferstat)
256 kbyte flash module (s12xftmr256k1v1) s12xs family reference manual, rev. 1.10 524 freescale semiconductor 18.3.2.9 p-flash protection register (fprot) the fprot register defines which p-flash sectors are protected against program and erase operations. the (unreserved) bits of the fprot register are writable with the restriction that the size of the protected region can only be increased (see section 18.3.2.9.1, ?-flash protection restrictions , and table 18-21 ). during the reset sequence, the fprot register is loaded with the contents of the p-flash protection byte in the flash configuration field at global address 0x7f_ff0c located in p-flash memory (see table 18-3 ) as indicated by reset condition ??in figure 18-13 . to change the p-flash protection that will be loaded during the reset sequence, the upper sector of the p-flash memory must be unprotected, then the p-flash protection byte must be reprogrammed. if a double bit fault is detected while reading the p-flash phrase containing the p-flash protection byte during the reset sequence, the fpopen bit will be cleared and remaining bits in the fprot register will be set to leave the p-flash memory fully protected. trying to alter data in any protected area in the p-flash memory will result in a protection violation error and the fpviol bit will be set in the fstat register. the block erase of a p-flash block is not possible if any of the p-flash sectors contained in the same p-flash block are protected. table 18-16. ferstat field descriptions field description 1 dfdif double bit fault detect interrupt flag ?the setting of the dfdif ?g indicates that a double bit fault was detected in the stored parity and data bits during a flash array read operation or that a flash array read operation was attempted on a flash block that was under a flash command operation. the dfdif ?g is cleared by writing a 1 to dfdif. writing a 0 to dfdif has no effect on dfdif. 0 no double bit fault detected 1 double bit fault detected or an invalid flash array read operation attempted 0 sfdif single bit fault detect interrupt flag ?with the ignsf bit in the fcnfg register clear, the sfdif ?g indicates that a single bit fault was detected in the stored parity and data bits during a flash array read operation or that a flash array read operation was attempted on a flash block that was under a flash command operation. the sfdif ?g is cleared by writing a 1 to sfdif. writing a 0 to sfdif has no effect on sfdif. 0 no single bit fault detected 1 single bit fault detected and corrected or an invalid flash array read operation attempted offset module base + 0x0008 76543210 r fpopen rnv6 fphdis fphs[1:0] fpldis fpls[1:0] w reset f f ffffff = unimplemented or reserved figure 18-13. flash protection register (fprot)
256 kbyte flash module (s12xftmr256k1v1) s12xs family reference manual, rev. 1.10 freescale semiconductor 525 table 18-17. fprot field descriptions field description 7 fpopen flash protection operation enable ?the fpopen bit determines the protection function for program or erase operations as shown in table 18-18 for the p-flash block. 0 when fpopen is clear, the fphdis and fpldis bits de?e unprotected address ranges as speci?d by the corresponding fphs and fpls bits 1 when fpopen is set, the fphdis and fpldis bits enable protection for the address range speci?d by the corresponding fphs and fpls bits 6 rnv[6] reserved nonvolatile bit ?the rnv bit should remain in the erased state for future enhancements. 5 fphdis flash protection higher address range disable ?the fphdis bit determines whether there is a protected/unprotected area in a speci? region of the p-flash memory ending with global address 0x7f_ffff. 0 protection/unprotection enabled 1 protection/unprotection disabled 4? fphs[1:0] flash protection higher address size the fphs bits determine the size of the protected/unprotected area in p-flash memory as shown in table 18-19 . the fphs bits can only be written to while the fphdis bit is set. 2 fpldis flash protection lower address range disable ?the fpldis bit determines whether there is a protected/unprotected area in a speci? region of the p-flash memory beginning with global address 0x7f_8000. 0 protection/unprotection enabled 1 protection/unprotection disabled 1? fpls[1:0] flash protection lower address size the fpls bits determine the size of the protected/unprotected area in p-flash memory as shown in table 18-20 . the fpls bits can only be written to while the fpldis bit is set. table 18-18. p-flash protection function fpopen fphdis fpldis function 1 1 for range sizes, refer to table 18-19 and table 18-20 . 1 1 1 no p-flash protection 1 1 0 protected low range 1 0 1 protected high range 1 0 0 protected high and low ranges 0 1 1 full p-flash memory protected 0 1 0 unprotected low range 0 0 1 unprotected high range 0 0 0 unprotected high and low ranges table 18-19. p-flash protection higher address range fphs[1:0] global address range protected size 00 0x7f_f800?x7f_ffff 2 kbytes 01 0x7f_f000?x7f_ffff 4 kbytes 10 0x7f_e000?x7f_ffff 8 kbytes 11 0x7f_c000?x7f_ffff 16 kbytes
256 kbyte flash module (s12xftmr256k1v1) s12xs family reference manual, rev. 1.10 526 freescale semiconductor all possible p-flash protection scenarios are shown in figure 18-14 . although the protection scheme is loaded from the flash memory at global address 0x7f_ff0c during the reset sequence, it can be changed by the user. the p-flash protection scheme can be used by applications requiring reprogramming in single chip mode while providing as much protection as possible if reprogramming is not required. table 18-20. p-flash protection lower address range fpls[1:0] global address range protected size 00 0x7f_8000?x7f_83ff 1 kbyte 01 0x7f_8000?x7f_87ff 2 kbytes 10 0x7f_8000?x7f_8fff 4 kbytes 11 0x7f_8000?x7f_9fff 8 kbytes
256 kbyte flash module (s12xftmr256k1v1) s12xs family reference manual, rev. 1.10 freescale semiconductor 527 figure 18-14. p-flash protection scenarios 7 6 5 4 fphs[1:0] fpls[1:0] 3 2 1 0 fphs[1:0] fpls[1:0] fphdis = 1 fpldis = 1 fphdis = 1 fpldis = 0 fphdis = 0 fpldis = 1 fphdis = 0 fpldis = 0 scenario scenario unprotected region protected region with size protected region protected region with size defined by fpls defined by fphs not defined by fpls, fphs 0x7f_8000 0x7f_ffff 0x7f_8000 0x7f_ffff flash start flash start fpopen = 1 fpopen = 0
256 kbyte flash module (s12xftmr256k1v1) s12xs family reference manual, rev. 1.10 528 freescale semiconductor 18.3.2.9.1 p-flash protection restrictions the general guideline is that p-flash protection can only be added and not removed. table 18-21 specifies all valid transitions between p-flash protection scenarios. any attempt to write an invalid scenario to the fprot register will be ignored. the contents of the fprot register reflect the active protection scenario. see the fphs and fpls bit descriptions for additional restrictions. 18.3.2.10 d-flash protection register (dfprot) the dfprot register de?es which d-flash sectors are protected against program and erase operations. the (unreserved) bits of the dfprot register are writable with the restriction that protection can be added but not removed. writes must increase the dps value and the dpoen bit can only be written from 1 (protection disabled) to 0 (protection enabled). if the dpopen bit is set, the state of the dps bits is irrelevant. during the reset sequence, the dfprot register is loaded with the contents of the d-flash protection byte in the flash configuration field at global address 0x7f_ff0d located in p-flash memory (see table 18-3 ) as indicated by reset condition f in figure 18-15 . to change the d-flash protection that will be loaded during the reset sequence, the p-flash sector containing the d-flash protection byte must be unprotected, then the d-flash protection byte must be programmed. if a double bit fault is detected while reading the table 18-21. p-flash protection scenario transitions from protection scenario to protection scenario 1 1 allowed transitions marked with x, see figure 18-14 for a de?ition of the scenarios. 01234567 0 xxxx 1 xx 2 xx 3 x 4 xx 5 xxxx 6 xxxx 7 xxxxxxxx offset module base + 0x0009 76543210 r dpopen 00 dps[4:0] w reset f 0 0 fffff = unimplemented or reserved figure 18-15. d-flash protection register (dfprot)
256 kbyte flash module (s12xftmr256k1v1) s12xs family reference manual, rev. 1.10 freescale semiconductor 529 p-flash phrase containing the d-flash protection byte during the reset sequence, the dpopen bit will be cleared and dps bits will be set to leave the d-flash memory fully protected. trying to alter data in any protected area in the d-flash memory will result in a protection violation error and the fpviol bit will be set in the fstat register. block erase of the d-flash memory is not possible if any of the d-flash sectors are protected. table 18-22. dfprot field descriptions field description 7 dpopen d-flash protection control 0 enables d-flash memory protection from program and erase with protected address range de?ed by dps bits 1 disables d-flash memory protection from program and erase 4? dps[4:0] d-flash protection size the dps[4:0] bits determine the size of the protected area in the d-flash memory as shown in table 18-23 . table 18-23. d-flash protection address range dps[4:0] global address range protected size 0_0000 0x10_0000 ?0x10_00ff 256 bytes 0_0001 0x10_0000 ?0x10_01ff 512 bytes 0_0010 0x10_0000 ?0x10_02ff 768 bytes 0_0011 0x10_0000 ?0x10_03ff 1024 bytes 0_0100 0x10_0000 ?0x10_04ff 1280 bytes 0_0101 0x10_0000 ?0x10_05ff 1536 bytes 0_0110 0x10_0000 ?0x10_06ff 1792 bytes 0_0111 0x10_0000 ?0x10_07ff 2048 bytes 0_1000 0x10_0000 ?0x10_08ff 2304 bytes 0_1001 0x10_0000 ?0x10_09ff 2560 bytes 0_1010 0x10_0000 ?0x10_0aff 2816 bytes 0_1011 0x10_0000 ?0x10_0bff 3072 bytes 0_1100 0x10_0000 ?0x10_0cff 3328 bytes 0_1101 0x10_0000 ?0x10_0dff 3584 bytes 0_1110 0x10_0000 ?0x10_0eff 3840 bytes 0_1111 0x10_0000 ?0x10_0fff 4096 bytes 1_0000 0x10_0000 ?0x10_10ff 4352 bytes 1_0001 0x10_0000 ?0x10_11ff 4608 bytes 1_0010 0x10_0000 ?0x10_12ff 4864 bytes 1_0011 0x10_0000 ?0x10_13ff 5120 bytes 1_0100 0x10_0000 ?0x10_14ff 5376 bytes 1_0101 0x10_0000 ?0x10_15ff 5632 bytes
256 kbyte flash module (s12xftmr256k1v1) s12xs family reference manual, rev. 1.10 530 freescale semiconductor 18.3.2.11 flash common command object register (fccob) the fccob is an array of six words addressed via the ccobix index found in the fccobix register. byte wide reads and writes are allowed to the fccob register. 18.3.2.11.1 fccob - nvm command mode nvm command mode uses the indexed fccob register to provide a command code and its relevant parameters to the memory controller. the user first sets up all required fccob fields and then initiates the command? execution by writing a 1 to the ccif bit in the fstat register (a 1 written by the user clears the ccif command completion flag to 0). when the user clears the ccif bit in the fstat register all fccob parameter fields are locked and cannot be changed by the user until the command completes 1_0110 0x10_0000 ?0x10_16ff 5888 bytes 1_0111 0x10_0000 ?0x10_17ff 6144 bytes 1_1000 0x10_0000 ?0x10_18ff 6400 bytes 1_1001 0x10_0000 ?0x10_19ff 6656 bytes 1_1010 0x10_0000 ?0x10_1aff 6912 bytes 1_1011 0x10_0000 ?0x10_1bff 7168 bytes 1_1100 0x10_0000 ?0x10_1cff 7424 bytes 1_1101 0x10_0000 ?0x10_1dff 7680 bytes 1_1110 0x10_0000 ?0x10_1eff 7936 bytes 1_1111 0x10_0000 ?0x10_1fff 8192 bytes offset module base + 0x000a 76543210 r ccob[15:8] w reset 00000000 figure 18-16. flash common command object high register (fccobhi) offset module base + 0x000b 76543210 r ccob[7:0] w reset 00000000 figure 18-17. flash common command object low register (fccoblo) table 18-23. d-flash protection address range dps[4:0] global address range protected size
256 kbyte flash module (s12xftmr256k1v1) s12xs family reference manual, rev. 1.10 freescale semiconductor 531 (as evidenced by the memory controller returning ccif to 1). some commands return information to the fccob register array. the generic format for the fccob parameter fields in nvm command mode is shown in table 18-24 . the return values are available for reading after the ccif flag in the fstat register has been returned to 1 by the memory controller. writes to the unimplemented parameter fields (ccobix = 110 and ccobix = 111) are ignored with reads from these fields returning 0x0000. table 18-24 shows the generic flash command format. the high byte of the first word in the ccob array contains the command code, followed by the parameters for this specific flash command. for details on the fccob settings required by each command, see the flash command descriptions in section 18.4.2 . 18.3.2.12 flash reserved0 register (frsv0) this flash register is reserved for factory testing. all bits in the frsv0 register read 0 and are not writable. table 18-24. fccob - nvm command mode (typical usage) ccobix[2:0] byte fccob parameter fields (nvm command mode) 000 hi fcmd[7:0] de?ing flash command lo 0, global address [22:16] 001 hi global address [15:8] lo global address [7:0] 010 hi data 0 [15:8] lo data 0 [7:0] 011 hi data 1 [15:8] lo data 1 [7:0] 100 hi data 2 [15:8] lo data 2 [7:0] 101 hi data 3 [15:8] lo data 3 [7:0] offset module base + 0x000c 76543210 r00000000 w reset 00000000 = unimplemented or reserved figure 18-18. flash reserved0 register (frsv0)
256 kbyte flash module (s12xftmr256k1v1) s12xs family reference manual, rev. 1.10 532 freescale semiconductor 18.3.2.13 flash reserved1 register (frsv1) this flash register is reserved for factory testing. all bits in the frsv1 register read 0 and are not writable. 18.3.2.14 flash ecc error results register (feccr) the feccr registers contain the result of a detected ecc fault for both single bit and double bit faults. the feccr register provides access to several ecc related fields as defined by the eccrix index bits in the feccrix register (see section 18.3.2.4 ). once ecc fault information has been stored, no other fault information will be recorded until the specific ecc fault flag has been cleared. in the event of simultaneous ecc faults the priority for fault recording is double bit fault over single bit fault. all feccr bits are readable but not writable. offset module base + 0x000d 76543210 r00000000 w reset 00000000 = unimplemented or reserved figure 18-19. flash reserved1 register (frsv1) offset module base + 0x000e 76543210 r eccr[15:8] w reset 00000000 = unimplemented or reserved figure 18-20. flash ecc error results high register (feccrhi) offset module base + 0x000f 76543210 r eccr[7:0] w reset 00000000 = unimplemented or reserved figure 18-21. flash ecc error results low register (feccrlo)
256 kbyte flash module (s12xftmr256k1v1) s12xs family reference manual, rev. 1.10 freescale semiconductor 533 the p-flash word addressed by eccrix = 001 contains the lower 16 bits of the global address. the following four words addressed by eccrix = 010 to 101 contain the 64-bit wide data phrase. the four data words and the parity byte are the uncorrected data read from the p-flash block. the d-flash word addressed by eccrix = 001 contains the lower 16 bits of the global address. the uncorrected 16-bit data word is addressed by eccrix = 010. 18.3.2.15 flash option register (fopt) the fopt register is the flash option register. all bits in the fopt register are readable but are not writable. table 18-25. feccr index settings eccrix[2:0] feccr register content bits [15:8] bit[7] bits[6:0] 000 parity bits read from flash block 0 global address [22:16] 001 global address [15:0] 010 data 0 [15:0] 011 data 1 [15:0] (p-flash only) 100 data 2 [15:0] (p-flash only) 101 data 3 [15:0] (p-flash only) 110 not used, returns 0x0000 when read 111 not used, returns 0x0000 when read table 18-26. feccr index=000 bit descriptions field description 15:8 par[7:0] ecc parity bits ?contains the 8 parity bits from the 72 bit wide p-flash data word or the 6 parity bits, allocated to par[5:0], from the 22 bit wide d-flash word with par[7:6]=00. 6? gaddr[22:16] global address ?the gaddr[22:16] ?ld contains the upper seven bits of the global address having caused the error. offset module base + 0x0010 76543210 r nv[7:0] w reset f f ffffff = unimplemented or reserved figure 18-22. flash option register (fopt)
256 kbyte flash module (s12xftmr256k1v1) s12xs family reference manual, rev. 1.10 534 freescale semiconductor during the reset sequence, the fopt register is loaded from the flash nonvolatile byte in the flash configuration field at global address 0x7f_ff0e located in p-flash memory (see table 18-3 ) as indicated by reset condition f in figure 18-22 . if a double bit fault is detected while reading the p-flash phrase containing the flash nonvolatile byte during the reset sequence, all bits in the fopt register will be set. 18.3.2.16 flash reserved2 register (frsv2) this flash register is reserved for factory testing. all bits in the frsv2 register read 0 and are not writable. 18.3.2.17 flash reserved3 register (frsv3) this flash register is reserved for factory testing. all bits in the frsv3 register read 0 and are not writable. 18.3.2.18 flash reserved4 register (frsv4) this flash register is reserved for factory testing. table 18-27. fopt field descriptions field description 7? nv[7:0] nonvolatile bits the nv[7:0] bits are available as nonvolatile bits. refer to the device user guide for proper use of the nv bits. offset module base + 0x0011 76543210 r00000000 w reset 00000000 = unimplemented or reserved figure 18-23. flash reserved2 register (frsv2) offset module base + 0x0012 76543210 r00000000 w reset 00000000 = unimplemented or reserved figure 18-24. flash reserved3 register (frsv3)
256 kbyte flash module (s12xftmr256k1v1) s12xs family reference manual, rev. 1.10 freescale semiconductor 535 all bits in the frsv4 register read 0 and are not writable. 18.4 functional description 18.4.1 flash command operations flash command operations are used to modify flash memory contents. the next sections describe: how to write the fclkdiv register that is used to generate a time base (fclk) derived from oscclk for flash program and erase command operations the command write sequence used to set flash command parameters and launch execution valid flash commands available for execution 18.4.1.1 writing the fclkdiv register prior to issuing any flash program or erase command after a reset, the user is required to write the fclkdiv register to divide oscclk down to a target fclk of 1 mhz. table 18-7 shows recommended values for the fdiv ?ld based on oscclk frequency. note programming or erasing the flash memory cannot be performed if the bus clock runs at less than 1 mhz. setting fdiv too high can destroy the flash memory due to overstress. setting fdiv too low can result in incomplete programming or erasure of the flash memory cells. when the fclkdiv register is written, the fdivld bit is set automatically. if the fdivld bit is 0, the fclkdiv register has not been written since the last reset. if the fclkdiv register has not been written, any flash program or erase command loaded during a command write sequence will not execute and the accerr bit in the fstat register will set. offset module base + 0x0013 76543210 r00000000 w reset 00000000 = unimplemented or reserved figure 18-25. flash reserved4 register (frsv4)
256 kbyte flash module (s12xftmr256k1v1) s12xs family reference manual, rev. 1.10 536 freescale semiconductor 18.4.1.2 command write sequence the memory controller will launch all valid flash commands entered using a command write sequence. before launching a command, the accerr and fpviol bits in the fstat register must be clear (see section 18.3.2.7 ) and the ccif flag should be tested to determine the status of the current command write sequence. if ccif is 0, the previous command write sequence is still active, a new command write sequence cannot be started, and all writes to the fccob register are ignored. caution writes to any flash register must be avoided while a flash command is active (ccif=0) to prevent corruption of flash register contents and memory controller behavior. 18.4.1.2.1 de?e fccob contents the fccob parameter ?lds must be loaded with all required parameters for the flash command being executed. access to the fccob parameter ?lds is controlled via the ccobix bits in the fccobix register (see section 18.3.2.3 ). the contents of the fccob parameter ?lds are transferred to the memory controller when the user clears the ccif command completion ?g in the fstat register (writing 1 clears the ccif to 0). the ccif ?g will remain clear until the flash command has completed. upon completion, the memory controller will return ccif to 1 and the fccob register will be used to communicate any results. the ?w for a generic command write sequence is shown in figure 18-26 .
256 kbyte flash module (s12xftmr256k1v1) s12xs family reference manual, rev. 1.10 freescale semiconductor 537 figure 18-26. generic flash command write sequence flowchart write to fccobix register write: fstat register (to launch command) clear ccif 0x80 clear accerr/fpviol 0x30 write: fstat register yes no access error and protection violation read: fstat register read: fstat register no start yes check ccif set? fccob accerr/ fpviol set? exit write: fclkdiv register read: fclkdiv register yes no clock register written check fdivld set? no bit polling for command completion check yes ccif set? to identify speci? command parameter to load. write to fccob register to load required command parameter. yes no more parameters? availability check results from previous command note: fclkdiv must be set after each reset
256 kbyte flash module (s12xftmr256k1v1) s12xs family reference manual, rev. 1.10 538 freescale semiconductor 18.4.1.3 valid flash module commands 18.4.1.4 p-flash commands table 18-29 summarizes the valid p-flash commands along with the effects of the commands on the p-flash block and other resources within the flash module. table 18-28. flash commands by mode fcmd command unsecured secured ns 1 1 unsecured normal single chip mode. nx 2 2 unsecured normal expanded mode. ss 3 3 unsecured special single chip mode. st 4 4 unsecured special mode. ns 5 5 secured normal single chip mode. nx 6 6 secured normal expanded mode. ss 7 7 secured special single chip mode. st 8 8 secured special mode. 0x01 erase verify all blocks ???????? 0x02 erase verify block ???????? 0x03 erase verify p-flash section ????? 0x04 read once ????? 0x06 program p-flash ????? 0x07 program once ????? 0x08 erase all blocks ?? ?? 0x09 erase flash block ????? 0x0a erase p-flash sector ????? 0x0b unsecure flash ?? ?? 0x0c verify backdoor access key ?? 0x0d set user margin level ????? 0x0e set field margin level ?? 0x10 erase verify d-flash section ????? 0x11 program d-flash ????? 0x12 erase d-flash sector ?????
256 kbyte flash module (s12xftmr256k1v1) s12xs family reference manual, rev. 1.10 freescale semiconductor 539 18.4.1.5 d-flash commands table 18-30 summarizes the valid d-flash commands along with the effects of the commands on the d-flash block. table 18-29. p-flash commands fcmd command function on p-flash memory 0x01 erase verify all blocks verify that all p-flash (and d-flash) blocks are erased. 0x02 erase verify block verify that a p-flash block is erased. 0x03 erase verify p-flash section verify that a given number of words starting at the address provided are erased. 0x04 read once read a dedicated 64 byte ?ld in the nonvolatile information register in p-flash block 0 that was previously programmed using the program once command. 0x06 program p-flash program a phrase in a p-flash block. 0x07 program once program a dedicated 64 byte ?ld in the nonvolatile information register in p-flash block 0 that is allowed to be programmed only once. 0x08 erase all blocks erase all p-flash (and d-flash) blocks. an erase of all flash blocks is only possible when the fpldis, fphdis, and fpopen bits in the fprot register and the dpopen bit in the dfprot register are set prior to launching the command. 0x09 erase flash block erase a p-flash (or d-flash) block. an erase of the full p-flash block is only possible when fpldis, fphdis and fpopen bits in the fprot register are set prior to launching the command. 0x0a erase p-flash sector erase all bytes in a p-flash sector. 0x0b unsecure flash supports a method of releasing mcu security by erasing all p-flash (and d-flash) blocks and verifying that all p-flash (and d-flash) blocks are erased. 0x0c verify backdoor access key supports a method of releasing mcu security by verifying a set of security keys. 0x0d set user margin level speci?s a user margin read level for all p-flash blocks. 0x0e set field margin level speci?s a ?ld margin read level for all p-flash blocks (special modes only). table 18-30. d-flash commands fcmd command function on d-flash memory 0x01 erase verify all blocks verify that all d-flash (and p-flash) blocks are erased. 0x02 erase verify block verify that the d-flash block is erased. 0x08 erase all blocks erase all d-flash (and p-flash) blocks. an erase of all flash blocks is only possible when the fpldis, fphdis, and fpopen bits in the fprot register and the dpopen bit in the dfprot register are set prior to launching the command. 0x09 erase flash block erase a d-flash (or p-flash) block. an erase of the full d-flash block is only possible when dpopen bit in the dfprot register is set prior to launching the command.
256 kbyte flash module (s12xftmr256k1v1) s12xs family reference manual, rev. 1.10 540 freescale semiconductor 18.4.2 flash command description this section provides details of all available flash commands launched by a command write sequence. the accerr bit in the fstat register will be set during the command write sequence if any of the following illegal steps are performed, causing the command not to be processed by the memory controller: starting any command write sequence that programs or erases flash memory before initializing the fclkdiv register writing an invalid command as part of the command write sequence for additional possible errors, refer to the error handling table provided for each command if a flash block is read during execution of an algorithm (ccif = 0) on that same block, the read operation will return invalid data. if the sfdif or dfdif flags were not previously set when the invalid read operation occurred, both the sfdif and dfdif flags will be set and the feccr registers will be loaded with the global address used in the invalid read operation with the data and parity fields set to all 0. if the accerr or fpviol bits are set in the fstat register, the user must clear these bits before starting any command write sequence (see section 18.3.2.7 ). caution a flash word or phrase must be in the erased state before being programmed. cumulative programming of bits within a flash word or phrase is not allowed. 18.4.2.1 erase verify all blocks command the erase verify all blocks command will verify that all p-flash and d-flash blocks have been erased. 0x0b unsecure flash supports a method of releasing mcu security by erasing all d-flash (and p-flash) blocks and verifying that all d-flash (and p-flash) blocks are erased. 0x0d set user margin level speci?s a user margin read level for the d-flash block. 0x0e set field margin level speci?s a ?ld margin read level for the d-flash block (special modes only). 0x10 erase verify d-flash section verify that a given number of words starting at the address provided are erased. 0x11 program d-flash program up to four words in the d-flash block. 0x12 erase d-flash sector erase all bytes in a sector of the d-flash block. table 18-31. erase verify all blocks command fccob requirements ccobix[2:0] fccob parameters 000 0x01 not required table 18-30. d-flash commands fcmd command function on d-flash memory
256 kbyte flash module (s12xftmr256k1v1) s12xs family reference manual, rev. 1.10 freescale semiconductor 541 upon clearing ccif to launch the erase verify all blocks command, the memory controller will verify that the entire flash memory space is erased. the ccif ?g will set after the erase verify all blocks operation has completed. 18.4.2.2 erase verify block command the erase verify block command allows the user to verify that an entire p-flash or d-flash block has been erased. the fccob upper global address bits determine which block must be veri?d. upon clearing ccif to launch the erase verify block command, the memory controller will verify that the selected p-flash or d-flash block is erased. the ccif ?g will set after the erase verify block operation has completed. 18.4.2.3 erase verify p-flash section command the erase verify p-flash section command will verify that a section of code in the p-flash memory is erased. the erase verify p-flash section command defines the starting point of the code to be verified and the number of phrases. the section to be verified cannot cross a 256 kbyte boundary in the p-flash memory space. table 18-32. erase verify all blocks command error handling register error bit error condition fstat accerr set if ccobix[2:0] != 000 at command launch fpviol none mgstat1 set if any errors have been encountered during the read mgstat0 set if any non-correctable errors have been encountered during the read table 18-33. erase verify block command fccob requirements ccobix[2:0] fccob parameters 000 0x02 global address [22:16] of the flash block to be veri?d . table 18-34. erase verify block command error handling register error bit error condition fstat accerr set if ccobix[2:0] != 000 at command launch set if an invalid global address [22:16] is supplied fpviol none mgstat1 set if any errors have been encountered during the read mgstat0 set if any non-correctable errors have been encountered during the read
256 kbyte flash module (s12xftmr256k1v1) s12xs family reference manual, rev. 1.10 542 freescale semiconductor upon clearing ccif to launch the erase verify p-flash section command, the memory controller will verify the selected section of flash memory is erased. the ccif ?g will set after the erase verify p-flash section operation has completed. 18.4.2.4 read once command the read once command provides read access to a reserved 64 byte field (8 phrases) located in the nonvolatile information register of p-flash block 0. the read once field is programmed using the program once command described in section 18.4.2.6 . the read once command must not be executed from the flash block containing the program once reserved field to avoid code runaway. upon clearing ccif to launch the read once command, a read once phrase is fetched and stored in the fccob indexed register. the ccif ?g will set after the read once operation has completed. valid table 18-35. erase verify p-flash section command fccob requirements ccobix[2:0] fccob parameters 000 0x03 global address [22:16] of a p-flash block 001 global address [15:0] of the ?st phrase to be veri?d 010 number of phrases to be veri?d table 18-36. erase verify p-flash section command error handling register error bit error condition fstat accerr set if ccobix[2:0] != 010 at command launch set if command not available in current mode (see table 18-28 ) set if an invalid global address [22:0] is supplied set if a misaligned phrase address is supplied (global address [2:0] != 000) set if the requested section crosses a 256 kbyte boundary fpviol none mgstat1 set if any errors have been encountered during the read mgstat0 set if any non-correctable errors have been encountered during the read table 18-37. read once command fccob requirements ccobix[2:0] fccob parameters 000 0x04 not required 001 read once phrase index (0x0000 - 0x0007) 010 read once word 0 value 011 read once word 1 value 100 read once word 2 value 101 read once word 3 value
256 kbyte flash module (s12xftmr256k1v1) s12xs family reference manual, rev. 1.10 freescale semiconductor 543 phrase index values for the read once command range from 0x0000 to 0x0007. during execution of the read once command, any attempt to read addresses within p-flash block will return invalid data. 18.4.2.5 program p-flash command the program p-flash operation will program a previously erased phrase in the p-flash memory using an embedded algorithm. caution a p-flash phrase must be in the erased state before being programmed. cumulative programming of bits within a flash phrase is not allowed. upon clearing ccif to launch the program p-flash command, the memory controller will program the data words to the supplied global address and will then proceed to verify the data words read back as expected. the ccif ?g will set after the program p-flash operation has completed. table 18-38. read once command error handling register error bit error condition fstat accerr set if ccobix[2:0] != 001 at command launch set if command not available in current mode (see table 18-28 ) set if an invalid phrase index is supplied fpviol none mgstat1 set if any errors have been encountered during the read mgstat0 set if any non-correctable errors have been encountered during the read table 18-39. program p-flash command fccob requirements ccobix[2:0] fccob parameters 000 0x06 global address [22:16] to identify p-flash block 001 global address [15:0] of phrase location to be programmed 1 1 global address [2:0] must be 000 010 word 0 program value 011 word 1 program value 100 word 2 program value 101 word 3 program value
256 kbyte flash module (s12xftmr256k1v1) s12xs family reference manual, rev. 1.10 544 freescale semiconductor 18.4.2.6 program once command the program once command restricts programming to a reserved 64 byte field (8 phrases) in the nonvolatile information register located in p-flash block 0. the program once reserved field can be read using the read once command as described in section 18.4.2.4 . the program once command must only be issued once since the nonvolatile information register in p-flash block 0 cannot be erased. the program once command must not be executed from the flash block containing the program once reserved field to avoid code runaway. upon clearing ccif to launch the program once command, the memory controller ?st veri?s that the selected phrase is erased. if erased, then the selected phrase will be programmed and then veri?d with read back. the ccif ?g will remain clear, setting only after the program once operation has completed. the reserved nonvolatile information register accessed by the program once command cannot be erased and any attempt to program one of these phrases a second time will not be allowed. valid phrase index values for the program once command range from 0x0000 to 0x0007. during execution of the program once command, any attempt to read addresses within p-flash block 0 will return invalid data. table 18-40. program p-flash command error handling register error bit error condition fstat accerr set if ccobix[2:0] != 101 at command launch set if command not available in current mode (see table 18-28 ) set if an invalid global address [22:0] is supplied set if a misaligned phrase address is supplied (global address [2:0] != 000) fpviol set if the global address [22:0] points to a protected area mgstat1 set if any errors have been encountered during the verify operation mgstat0 set if any non-correctable errors have been encountered during the verify operation table 18-41. program once command fccob requirements ccobix[2:0] fccob parameters 000 0x07 not required 001 program once phrase index (0x0000 - 0x0007) 010 program once word 0 value 011 program once word 1 value 100 program once word 2 value 101 program once word 3 value
256 kbyte flash module (s12xftmr256k1v1) s12xs family reference manual, rev. 1.10 freescale semiconductor 545 r, 18.4.2.7 erase all blocks command the erase all blocks operation will erase the entire p-flash and d-flash memory space. upon clearing ccif to launch the erase all blocks command, the memory controller will erase the entire flash memory space and verify that it is erased. if the memory controller veri?s that the entire flash memory space was properly erased, security will be released. during the execution of this command (ccif=0) the user must not write to any flash module register. the ccif ?g will set after the erase all blocks operation has completed. 18.4.2.8 erase flash block command the erase flash block operation will erase all addresses in a p-flash or d-flash block. table 18-42. program once command error handling register error bit error condition fstat accerr set if ccobix[2:0] != 101 at command launch set if command not available in current mode (see table 18-28 ) set if an invalid phrase index is supplied set if the requested phrase has already been programmed 1 1 if a program once phrase is initially programmed to 0xffff_ffff_ffff_ffff, the program once command will be allowed to execute again on that same phrase. fpviol none mgstat1 set if any errors have been encountered during the verify operation mgstat0 set if any non-correctable errors have been encountered during the verify operation table 18-43. erase all blocks command fccob requirements ccobix[2:0] fccob parameters 000 0x08 not required table 18-44. erase all blocks command error handling register error bit error condition fstat accerr set if ccobix[2:0] != 000 at command launch set if command not available in current mode (see table 18-28 ) fpviol set if any area of the p-flash or d-flash memory is protected mgstat1 set if any errors have been encountered during the verify operation mgstat0 set if any non-correctable errors have been encountered during the verify operation
256 kbyte flash module (s12xftmr256k1v1) s12xs family reference manual, rev. 1.10 546 freescale semiconductor upon clearing ccif to launch the erase flash block command, the memory controller will erase the selected flash block and verify that it is erased. the ccif ?g will set after the erase flash block operation has completed. 18.4.2.9 erase p-flash sector command the erase p-flash sector operation will erase all addresses in a p-flash sector. upon clearing ccif to launch the erase p-flash sector command, the memory controller will erase the selected flash sector and then verify that it is erased. the ccif ?g will be set after the erase p-flash sector operation has completed. table 18-45. erase flash block command fccob requirements ccobix[2:0] fccob parameters 000 0x09 global address [22:16] to identify flash block 001 global address [15:0] in flash block to be erased table 18-46. erase flash block command error handling register error bit error condition fstat accerr set if ccobix[2:0] != 001 at command launch set if command not available in current mode (see table 18-28 ) set if an invalid global address [22:16] is supplied set if the supplied p-flash address is not phrase-aligned or if the d-flash address is not word-aligned fpviol set if an area of the selected flash block is protected mgstat1 set if any errors have been encountered during the verify operation mgstat0 set if any non-correctable errors have been encountered during the verify operation table 18-47. erase p-flash sector command fccob requirements ccobix[2:0] fccob parameters 000 0x0a global address [22:16] to identify p-flash block to be erased 001 global address [15:0] anywhere within the sector to be erased. refer to section 18.1.2.1 for the p-flash sector size.
256 kbyte flash module (s12xftmr256k1v1) s12xs family reference manual, rev. 1.10 freescale semiconductor 547 18.4.2.10 unsecure flash command the unsecure flash command will erase the entire p-flash and d-flash memory space and, if the erase is successful, will release security. upon clearing ccif to launch the unsecure flash command, the memory controller will erase the entire p-flash and d-flash memory space and verify that it is erased. if the memory controller veri?s that the entire flash memory space was properly erased, security will be released. if the erase verify is not successful, the unsecure flash operation sets mgstat1 and terminates without changing the security state. during the execution of this command (ccif=0) the user must not write to any flash module register. the ccif ?g is set after the unsecure flash operation has completed. 18.4.2.11 verify backdoor access key command the verify backdoor access key command will only execute if it is enabled by the keyen bits in the fsec register (see table 18-9 ). the verify backdoor access key command releases security if user-supplied keys match those stored in the flash security bytes of the flash configuration field (see table 18-48. erase p-flash sector command error handling register error bit error condition fstat accerr set if ccobix[2:0] != 001 at command launch set if command not available in current mode (see table 18-28 ) set if an invalid global address [22:16] is supplied set if a misaligned phrase address is supplied (global address [2:0] != 000) fpviol set if the selected p-flash sector is protected mgstat1 set if any errors have been encountered during the verify operation mgstat0 set if any non-correctable errors have been encountered during the verify operation table 18-49. unsecure flash command fccob requirements ccobix[2:0] fccob parameters 000 0x0b not required table 18-50. unsecure flash command error handling register error bit error condition fstat accerr set if ccobix[2:0] != 000 at command launch set if command not available in current mode (see table 18-28 ) fpviol set if any area of the p-flash or d-flash memory is protected mgstat1 set if any errors have been encountered during the verify operation mgstat0 set if any non-correctable errors have been encountered during the verify operation
256 kbyte flash module (s12xftmr256k1v1) s12xs family reference manual, rev. 1.10 548 freescale semiconductor table 18-3 ). the verify backdoor access key command must not be executed from the flash block containing the backdoor comparison key to avoid code runaway. upon clearing ccif to launch the verify backdoor access key command, the memory controller will check the fsec keyen bits to verify that this command is enabled. if not enabled, the memory controller sets the accerr bit in the fstat register and terminates. if the command is enabled, the memory controller compares the key provided in fccob to the backdoor comparison key in the flash con?uration ?ld with key 0 compared to 0x7f_ff00, etc. if the backdoor keys match, security will be released. if the backdoor keys do not match, security is not released and all future attempts to execute the verify backdoor access key command are aborted (set accerr) until a reset occurs. the ccif flag is set after the verify backdoor access key operation has completed. 18.4.2.12 set user margin level command the set user margin level command causes the memory controller to set the margin level for future read operations of a specific p-flash or d-flash block. table 18-51. verify backdoor access key command fccob requirements ccobix[2:0] fccob parameters 000 0x0c not required 001 key 0 010 key 1 011 key 2 100 key 3 table 18-52. verify backdoor access key command error handling register error bit error condition fstat accerr set if ccobix[2:0] != 100 at command launch set if an incorrect backdoor key is supplied set if backdoor key access has not been enabled (keyen[1:0] != 10, see section 18.3.2.2 ) set if the backdoor key has mismatched since the last reset fpviol none mgstat1 none mgstat0 none table 18-53. set user margin level command fccob requirements ccobix[2:0] fccob parameters 000 0x0d global address [22:16] to identify the flash block 001 margin level setting
256 kbyte flash module (s12xftmr256k1v1) s12xs family reference manual, rev. 1.10 freescale semiconductor 549 upon clearing ccif to launch the set user margin level command, the memory controller will set the user margin level for the targeted block and then set the ccif ?g. valid margin level settings for the set user margin level command are de?ed in table 18-54 . note user margin levels can be used to check that flash memory contents have adequate margin for normal level read operations. if unexpected results are encountered when checking flash memory contents at user margin levels, a potential loss of information has been detected. 18.4.2.13 set field margin level command the set field margin level command, valid in special modes only, causes the memory controller to set the margin level specified for future read operations of a specific p-flash or d-flash block. table 18-54. valid set user margin level settings ccob (ccobix=001) level description 0x0000 return to normal level 0x0001 user margin-1 level 1 1 read margin to the erased state 0x0002 user margin-0 level 2 2 read margin to the programmed state table 18-55. set user margin level command error handling register error bit error condition fstat accerr set if ccobix[2:0] != 001 at command launch set if command not available in current mode (see table 18-28 ) set if an invalid global address [22:16] is supplied set if an invalid margin level setting is supplied fpviol none mgstat1 none mgstat0 none table 18-56. set field margin level command fccob requirements ccobix[2:0] fccob parameters 000 0x0e global address [22:16] to identify the flash block 001 margin level setting
256 kbyte flash module (s12xftmr256k1v1) s12xs family reference manual, rev. 1.10 550 freescale semiconductor upon clearing ccif to launch the set field margin level command, the memory controller will set the ?ld margin level for the targeted block and then set the ccif ?g. valid margin level settings for the set field margin level command are de?ed in table 18-57 . caution field margin levels must only be used during verify of the initial factory programming. note field margin levels can be used to check that flash memory contents have adequate margin for data retention at the normal level setting. if unexpected results are encountered when checking flash memory contents at ?ld margin levels, the flash memory contents should be erased and reprogrammed. 18.4.2.14 erase verify d-flash section command the erase verify d-flash section command will verify that a section of code in the d-flash is erased. the erase verify d-flash section command defines the starting point of the data to be verified and the number of words. table 18-57. valid set field margin level settings ccob (ccobix=001) level description 0x0000 return to normal level 0x0001 user margin-1 level 1 1 read margin to the erased state 0x0002 user margin-0 level 2 2 read margin to the programmed state 0x0003 field margin-1 level 1 0x0004 field margin-0 level 2 table 18-58. set field margin level command error handling register error bit error condition fstat accerr set if ccobix[2:0] != 001 at command launch set if command not available in current mode (see table 18-28 ) set if an invalid global address [22:16] is supplied set if an invalid margin level setting is supplied fpviol none mgstat1 none mgstat0 none
256 kbyte flash module (s12xftmr256k1v1) s12xs family reference manual, rev. 1.10 freescale semiconductor 551 upon clearing ccif to launch the erase verify d-flash section command, the memory controller will verify the selected section of d-flash memory is erased. the ccif ?g will set after the erase verify d-flash section operation has completed. 18.4.2.15 program d-flash command the program d-flash operation programs one to four previously erased words in the d-flash block. the program d-flash operation will confirm that the targeted location(s) were successfully programmed upon completion. caution a flash word must be in the erased state before being programmed. cumulative programming of bits within a flash word is not allowed. table 18-59. erase verify d-flash section command fccob requirements ccobix[2:0] fccob parameters 000 0x10 global address [22:16] to identify the d-flash block 001 global address [15:0] of the ?st word to be veri?d 010 number of words to be veri?d table 18-60. erase verify d-flash section command error handling register error bit error condition fstat accerr set if ccobix[2:0] != 010 at command launch set if command not available in current mode (see table 18-28 ) set if an invalid global address [22:0] is supplied set if a misaligned word address is supplied (global address [0] != 0) set if the requested section breaches the end of the d-flash block fpviol none mgstat1 set if any errors have been encountered during the read mgstat0 set if any non-correctable errors have been encountered during the read table 18-61. program d-flash command fccob requirements ccobix[2:0] fccob parameters 000 0x11 global address [22:16] to identify the d-flash block 001 global address [15:0] of word to be programmed 010 word 0 program value 011 word 1 program value, if desired 100 word 2 program value, if desired
256 kbyte flash module (s12xftmr256k1v1) s12xs family reference manual, rev. 1.10 552 freescale semiconductor upon clearing ccif to launch the program d-flash command, the user-supplied words will be transferred to the memory controller and be programmed if the area is unprotected. the ccobix index value at program d-flash command launch determines how many words will be programmed in the d-flash block. the ccif ?g is set when the operation has completed. 18.4.2.16 erase d-flash sector command the erase d-flash sector operation will erase all addresses in a sector of the d-flash block. upon clearing ccif to launch the erase d-flash sector command, the memory controller will erase the selected flash sector and verify that it is erased. the ccif ?g will set after the erase d-flash sector operation has completed. 101 word 3 program value, if desired table 18-62. program d-flash command error handling register error bit error condition fstat accerr set if ccobix[2:0] < 010 at command launch set if ccobix[2:0] > 101 at command launch set if command not available in current mode (see table 18-28 ) set if an invalid global address [22:0] is supplied set if a misaligned word address is supplied (global address [0] != 0) set if the requested group of words breaches the end of the d-flash block fpviol set if the selected area of the d-flash memory is protected mgstat1 set if any errors have been encountered during the verify operation mgstat0 set if any non-correctable errors have been encountered during the verify operation table 18-63. erase d-flash sector command fccob requirements ccobix[2:0] fccob parameters 000 0x12 global address [22:16] to identify d-flash block 001 global address [15:0] anywhere within the sector to be erased. see section 18.1.2.2 for d-flash sector size. table 18-61. program d-flash command fccob requirements ccobix[2:0] fccob parameters
256 kbyte flash module (s12xftmr256k1v1) s12xs family reference manual, rev. 1.10 freescale semiconductor 553 18.4.3 interrupts the flash module can generate an interrupt when a flash command operation has completed or when a flash command operation has detected an ecc fault. note vector addresses and their relative interrupt priority are determined at the mcu level. 18.4.3.1 description of flash interrupt operation the flash module uses the ccif ?g in combination with the ccie interrupt enable bit to generate the flash command interrupt request. the flash module uses the dfdif and sfdif ?gs in combination with the dfdie and sfdie interrupt enable bits to generate the flash error interrupt request. for a detailed description of the register bits involved, refer to section 18.3.2.5, ?lash configuration register (fcnfg) ? section 18.3.2.6, ?lash error configuration register (fercnfg) ? section 18.3.2.7, ?lash status register (fstat) ? and section 18.3.2.8, ?lash error status register (ferstat) ? the logic used for generating the flash module interrupts is shown in figure 18-27 . table 18-64. erase d-flash sector command error handling register error bit error condition fstat accerr set if ccobix[2:0] != 001 at command launch set if command not available in current mode (see table 18-28 ) set if an invalid global address [22:0] is supplied set if a misaligned word address is supplied (global address [0] != 0) fpviol set if the selected area of the d-flash memory is protected mgstat1 set if any errors have been encountered during the verify operation mgstat0 set if any non-correctable errors have been encountered during the verify operation table 18-65. flash interrupt sources interrupt source interrupt flag local enable global (ccr) mask flash command complete ccif (fstat register) ccie (fcnfg register) i bit ecc double bit fault on flash read dfdif (ferstat register) dfdie (fercnfg register) i bit ecc single bit fault on flash read sfdif (ferstat register) sfdie (fercnfg register) i bit
256 kbyte flash module (s12xftmr256k1v1) s12xs family reference manual, rev. 1.10 554 freescale semiconductor figure 18-27. flash module interrupts implementation 18.4.4 wait mode the flash module is not affected if the mcu enters wait mode. the flash module can recover the mcu from wait via the ccif interrupt (see section 18.4.3, ?nterrupts ). 18.4.5 stop mode if a flash command is active (ccif = 0) when the mcu requests stop mode, the current flash operation will be completed before the cpu is allowed to enter stop mode. 18.5 security the flash module provides security information to the mcu. the flash security state is de?ed by the sec bits of the fsec register (see table 18-10 ). during reset, the flash module initializes the fsec register using data read from the security byte of the flash con?uration ?ld at global address 0x7f_ff0f. the security state out of reset can be permanently changed by programming the security byte of the flash con?uration ?ld. this assumes that you are starting from a mode where the necessary p-flash erase and program commands are available and that the upper region of the p-flash is unprotected. if the flash security byte is successfully programmed, its new value will take affect after the next mcu reset. the following subsections describe these security-related subjects: unsecuring the mcu using backdoor key access unsecuring the mcu in special single chip mode using bdm mode and security effects on flash command availability 18.5.1 unsecuring the mcu using backdoor key access the mcu may be unsecured by using the backdoor key access feature which requires knowledge of the contents of the backdoor keys (four 16-bit words programmed at addresses 0x7f_ff00?x7f_ff07). if the keyen[1:0] bits are in the enabled state (see section 18.3.2.2 ), the verify backdoor access key command (see section 18.4.2.11 ) allows the user to present four prospective keys for comparison to the flash error interrupt request ccif ccie dfdif dfdie sfdif sfdie flash command interrupt request
256 kbyte flash module (s12xftmr256k1v1) s12xs family reference manual, rev. 1.10 freescale semiconductor 555 keys stored in the flash memory via the memory controller. if the keys presented in the verify backdoor access key command match the backdoor keys stored in the flash memory, the sec bits in the fsec register (see table 18-10 ) will be changed to unsecure the mcu. key values of 0x0000 and 0xffff are not permitted as backdoor keys. while the verify backdoor access key command is active, p-flash block 0 will not be available for read access and will return invalid data. the user code stored in the p-flash memory must have a method of receiving the backdoor keys from an external stimulus. this external stimulus would typically be through one of the on-chip serial ports. if the keyen[1:0] bits are in the enabled state (see section 18.3.2.2 ), the mcu can be unsecured by the backdoor key access sequence described below: 1. follow the command sequence for the verify backdoor access key command as explained in section 18.4.2.11 2. if the verify backdoor access key command is successful, the mcu is unsecured and the sec[1:0] bits in the fsec register are forced to the unsecure state of 10 the verify backdoor access key command is monitored by the memory controller and an illegal key will prohibit future use of the verify backdoor access key command. a reset of the mcu is the only method to re-enable the verify backdoor access key command. after the backdoor keys have been correctly matched, the mcu will be unsecured. after the mcu is unsecured, the sector containing the flash security byte can be erased and the flash security byte can be reprogrammed to the unsecure state, if desired. in the unsecure state, the user has full control of the contents of the backdoor keys by programming addresses 0x7f_ff00?x7f_ff07 in the flash con?uration ?ld. the security as de?ed in the flash security byte (0x7f_ff0f) is not changed by using the verify backdoor access key command sequence. the backdoor keys stored in addresses 0x7f_ff00?x7f_ff07 are unaffected by the verify backdoor access key command sequence. after the next reset of the mcu, the security state of the flash module is determined by the flash security byte (0x7f_ff0f). the verify backdoor access key command sequence has no effect on the program and erase protections de?ed in the flash protection register, fprot. 18.5.2 unsecuring the mcu in special single chip mode using bdm the mcu can be unsecured in special single chip mode by erasing the p-flash and d-flash memory by one of the following methods: reset the mcu into special single chip mode, delay while the erase test is performed by the bdm, send bdm commands to disable protection in the p-flash and d-flash memory, and execute the erase all blocks command write sequence to erase the p-flash and d-flash memory. reset the mcu into special expanded wide mode, disable protection in the p-flash and d-flash memory and run code from external memory to execute the erase all blocks command write sequence to erase the p-flash and d-flash memory. after the ccif ?g sets to indicate that the erase all blocks operation has completed, reset the mcu into special single chip mode. the bdm will execute the erase verify all blocks command write sequence to verify that the p-flash and d-flash memory is erased. if the p-flash and d-flash memory are verified as
256 kbyte flash module (s12xftmr256k1v1) s12xs family reference manual, rev. 1.10 556 freescale semiconductor erased the mcu will be unsecured. all bdm commands will be enabled and the flash security byte may be programmed to the unsecure state by the following method: send bdm commands to execute a ?rogram p-flash?command sequence to program the flash security byte to the unsecured state and reset the mcu. 18.5.3 mode and security effects on flash command availability the availability of flash module commands depends on the mcu operating mode and security state as shown in table 18-28 . 18.6 initialization on each system reset the flash module executes a reset sequence which establishes initial values for the flash block configuration parameters, the fprot and dfprot protection registers, and the fopt and fsec registers. the flash module reverts to built-in default values that leave the module in a fully protected and secured state if errors are encountered during execution of the reset sequence. if a double bit fault is detected during the reset sequence, both mgstat bits in the fstat register will be set. ccif remains clear throughout the reset sequence. the flash module holds off all cpu access for the initial portion of the reset sequence. while flash reads are possible when the hold is removed, writes to the fccobix, fccobhi, and fccoblo registers are ignored to prevent command activity while the memory controller remains busy. completion of the reset sequence is marked by setting ccif high which enables writes to the fccobix, fccobhi, and fccoblo registers to launch any available flash command. if a reset occurs while any flash command is in progress, that command will be immediately aborted. the state of the word being programmed or the sector/block being erased is not guaranteed.
s12xs family reference manual, rev. 1.10 freescale semiconductor 557 preliminary chapter 19 128 kbyte flash module (s12xftmr128k1v1) 19.1 introduction the ftmr128k1 module implements the following: 128 kbytes of p-flash (program flash) memory 8 kbytes of d-flash (data flash) memory the flash memory is ideal for single-supply applications allowing for ?ld reprogramming without requiring external high voltage sources for program or erase operations. the flash module includes a memory controller that executes commands to modify flash memory contents. the user interface to the memory controller consists of the indexed flash common command object (fccob) register which is written to with the command, global address, data, and any required command parameters. the memory controller must complete the execution of a command before the fccob register can be written to with a new command. table 19-1. revision history revision number revision date sections affected description of changes v01.04 03 jan 2008 - cosmetic changes v01.05 19 dec 2008 19.1/19-557 19.4.2.4/19-592 19.4.2.6/19-594 19.4.2.11/19-59 7 19.4.2.11/19-59 7 19.4.2.11/19-59 7 - clarify single bit fault correction for p-flash phrase - add statement concerning code runaway when executing read once, program once, and verify backdoor access key commands from flash block containing associated ?lds - relate key 0 to associated backdoor comparison key address - change ?ower down reset?to ?eset?in section 19.4.2.11 v01.06 25 sep 2009 19.3.2/19-564 19.3.2.1/19-566 19.4.1.2/19-586 19.6/19-606 the following changes were made to clarify module behavior related to flash register access during reset sequence and while flash commands are active: - add caution concerning register writes while command is active - writes to fclkdiv are allowed during reset sequence while ccif is clear - add caution concerning register writes while command is active - writes to fccobix, fccobhi, fccoblo registers are ignored during reset sequence
s12xs family reference manual, rev. 1.10 freescale semiconductor 558 preliminary caution a flash word or phrase must be in the erased state before being programmed. cumulative programming of bits within a flash word or phrase is not allowed. the flash memory may be read as bytes, aligned words, or misaligned words. read access time is one bus cycle for bytes and aligned words, and two bus cycles for misaligned words. for flash memory, an erased bit reads 1 and a programmed bit reads 0. it is not possible to read from a flash block while any command is executing on that speci? flash block. it is possible to read from a flash block while a command is executing on a different flash block. both p-flash and d-flash memories are implemented with error correction codes (ecc) that can resolve single bit faults and detect double bit faults. for p-flash memory, the ecc implementation requires that programming be done on an aligned 8 byte basis (a flash phrase). since p-flash memory is always read by phrase, only one single bit fault in the phrase containing the byte or word accessed will be corrected. 19.1.1 glossary command write sequence ?an mcu instruction sequence to execute built-in algorithms (including program and erase) on the flash memory. d-flash memory ?the d-flash memory constitutes the nonvolatile memory store for data. d-flash sector the d-flash sector is the smallest portion of the d-flash memory that can be erased. the d-flash sector consists of four 64 byte rows for a total of 256 bytes. nvm command mode an nvm mode using the cpu to setup the fccob register to pass parameters required for flash command execution. phrase an aligned group of four 16-bit words within the p-flash memory. each phrase includes eight ecc bits for single bit fault correction and double bit fault detection within the phrase. p-flash memory the p-flash memory constitutes the main nonvolatile memory store for applications. p-flash sector ?the p-flash sector is the smallest portion of the p-flash memory that can be erased. each p-flash sector contains 1024 bytes. program ifr ?nonvolatile information register located in the p-flash block that contains the device id, version id, and the program once ?ld. the program ifr is visible in the global memory map by setting the pgmifron bit in the mmcctl1 register.
128 kbyte flash module (s12xftmr128k1v1) s12xs family reference manual, rev. 1.10 freescale semiconductor 559 19.1.2 features 19.1.2.1 p-flash features 128 kbytes of p-flash memory composed of one 128 kbyte flash block divided into 128 sectors of 1024 bytes single bit fault correction and double bit fault detection within a 64-bit phrase during read operations automated program and erase algorithm with verify and generation of ecc parity bits fast sector erase and phrase program operation flexible protection scheme to prevent accidental program or erase of p-flash memory 19.1.2.2 d-flash features 8 kbytes of d-flash memory composed of one 8 kbyte flash block divided into 32 sectors of 256 bytes single bit fault correction and double bit fault detection within a word during read operations automated program and erase algorithm with verify and generation of ecc parity bits fast sector erase and word program operation protection scheme to prevent accidental program or erase of d-flash memory ability to program up to four words in a burst sequence 19.1.2.3 other flash module features no external high-voltage power supply required for flash memory program and erase operations interrupt generation on flash command completion and flash error detection security mechanism to prevent unauthorized access to the flash memory 19.1.3 block diagram the block diagram of the flash module is shown in figure 19-1 .
128 kbyte flash module (s12xftmr128k1v1) s12xs family reference manual, rev. 1.10 560 freescale semiconductor figure 19-1. ftmr128k1 block diagram 19.2 external signal description the flash module contains no signals that connect off-chip. 19.3 memory map and registers this section describes the memory map and registers for the flash module. read data from unimplemented memory space in the flash module is unde?ed. write access to unimplemented or reserved memory space in the flash module will be ignored by the flash module. oscillator clock divider clock (xtal) command interrupt request fclk protection security registers flash interface 16bit internal bus sector 0 sector 1 sector 127 16kx72 p-flash error interrupt request cpu d-flash 4kx22 sector 0 sector 1 sector 31 scratch ram 384x16bits memory controller
128 kbyte flash module (s12xftmr128k1v1) s12xs family reference manual, rev. 1.10 freescale semiconductor 561 19.3.1 module memory map the s12x architecture places the p-flash memory between global addresses 0x7e_0000 and 0x7f_ffff as shown in table 19-2 . the p-flash memory map is shown in figure 19-2 . the fprot register, described in section 19.3.2.9 , can be set to protect regions in the flash memory from accidental program or erase. three separate memory regions, one growing upward from global address 0x7f_8000 in the flash memory (called the lower region), one growing downward from global address 0x7f_ffff in the flash memory (called the higher region), and the remaining addresses in the flash memory, can be activated for protection. the flash memory addresses covered by these protectable regions are shown in the p-flash memory map. the higher address region is mainly targeted to hold the boot loader code since it covers the vector space. default protection settings as well as security information that allows the mcu to restrict access to the flash module are stored in the flash con?uration ?ld as described in table 19-3 . table 19-2. p-flash memory addressing global address size (bytes) description 0x7e_0000 ?0x7f_ffff 128 k p-flash block 0 contains flash con?uration field (see table 19-3 ) table 19-3. flash con?uration field 1 1 older versions may have swapped protection byte addresses global address size (bytes) description 0x7f_ff00 ?0x7f_ff07 8 backdoor comparison key refer to section 19.4.2.11, ?erify backdoor access key command , and section 19.5.1, ?nsecuring the mcu using backdoor key access 0x7f_ff08 0x7f_ff0b 2 2 0x7ff08 - 0x7f_ff0f form a flash phrase and must be programmed in a single command write sequence. each byte in the 0x7f_ff08 - 0x7f_ff0b reserved ?ld should be programmed to 0xff. 4 reserved 0x7f_ff0c 2 1 p-flash protection byte . refer to section 19.3.2.9, ?-flash protection register (fprot) 0x7f_ff0d 2 1 d-flash protection byte . refer to section 19.3.2.10, ?-flash protection register (dfprot) 0x7f_ff0e 2 1 flash nonvolatile byte refer to section 19.3.2.15, ?lash option register (fopt) 0x7f_ff0f 2 1 flash security byte refer to section 19.3.2.2, ?lash security register (fsec)
128 kbyte flash module (s12xftmr128k1v1) s12xs family reference manual, rev. 1.10 562 freescale semiconductor figure 19-2. p-flash memory map flash con?uration field 0x7f_c000 flash protected/unprotected lower region 1, 2, 4, 8 kbytes 0x7f_8000 0x7f_9000 0x7f_8400 0x7f_8800 0x7f_a000 p-flash end = 0x7f_ffff 0x7f_f800 0x7f_f000 0x7f_e000 flash protected/unprotected higher region 2, 4, 8, 16 kbytes flash protected/unprotected region 8 kbytes (up to 29 kbytes) 16 bytes (0x7f_ff00 - 0x7f_ff0f) flash protected/unprotected region 96 kbytes p-flash start = 0x7e_0000
128 kbyte flash module (s12xftmr128k1v1) s12xs family reference manual, rev. 1.10 freescale semiconductor 563 table 19-4. program ifr fields global address (pgmifron) size (bytes) field description 0x40_0000 ?0x40_0007 8 device id 0x40_0008 ?0x40_00e7 224 reserved 0x40_00e8 ?0x40_00e9 2 version id 0x40_00ea ?0x40_00ff 22 reserved 0x40_0100 ?0x40_013f 64 program once field refer to section 19.4.2.6, ?rogram once command 0x40_0140 ?0x40_01ff 192 reserved table 19-5. d-flash and memory controller resource fields global address size (bytes) description 0x10_0000 ?0x10_1fff 8,192 d-flash memory 0x10_2000 ?0x11_ffff 122,880 reserved 0x12_0000 ?0x12_007f 128 d-flash nonvolatile information register (dfifron 1 = 1) 1 mmcctl1 register bit 0x12_0080 ?0x12_0fff 3,968 reserved 0x12_1000 ?0x12_1fff 4,096 reserved 0x12_2000 ?0x12_3cff 7,242 reserved 0x12_3d00 ?0x12_3fff 768 memory controller scratch ram (mgramon 1 = 1) 0x12_4000 ?0x12_e7ff 43,008 reserved 0x12_e800 ?0x12_ffff 6,144 reserved 0x13_0000 ?0x13_ffff 65,536 reserved
128 kbyte flash module (s12xftmr128k1v1) s12xs family reference manual, rev. 1.10 564 freescale semiconductor figure 19-3. d-flash and memory controller resource memory map 19.3.2 register descriptions the flash module contains a set of 20 control and status registers located between flash module base + 0x0000 and 0x0013. a summary of the flash module registers is given in figure 19-4 with detailed descriptions in the following subsections. caution writes to any flash register must be avoided while a flash command is active (ccif=0) to prevent corruption of flash register contents and memory controller behavior. address & name 76543210 0x0000 fclkdiv r fdivld fdiv6 fdiv5 fdiv4 fdiv3 fdiv2 fdiv1 fdiv0 w 0x0001 fsec r keyen1 keyen0 rnv5 rnv4 rnv3 rnv2 sec1 sec0 w figure 19-4. ftmr128k1 register summary 0x12_ffff 0x12_4000 0x12_1000 memory controller scratch ram (mgramon) 768 bytes d-flash nonvolatile information register (dfifron) 128 bytes d-flash memory 8 kbytes d-flash start = 0x10_0000 0x12_0000 0x12_2000 0x12_e800 d-flash end = 0x10_1fff
128 kbyte flash module (s12xftmr128k1v1) s12xs family reference manual, rev. 1.10 freescale semiconductor 565 0x0002 fccobix r0 0 0 0 0 ccobix2 ccobix1 ccobix0 w 0x0003 feccrix r0 0 0 0 0 eccrix2 eccrix1 eccrix0 w 0x0004 fcnfg r ccie 00 ignsf 00 fdfd fsfd w 0x0005 fercnfg r 0 dfdie sfdie w 0x0006 fstat r ccif 0 accerr fpviol mgbusy rsvd mgstat1 mgstat0 w 0x0007 ferstat r0 0 0 0 0 0 dfdif sfdif w 0x0008 fprot r fpopen rnv6 fphdis fphs1 fphs0 fpldis fpls1 fpls0 w 0x0009 dfprot r dpopen 00 dps4 dps3 dps2 dps1 dps0 w 0x000a fccobhi r ccob15 ccob14 ccob13 ccob12 ccob11 ccob10 ccob9 ccob8 w 0x000b fccoblo r ccob7 ccob6 ccob5 ccob4 ccob3 ccob2 ccob1 ccob0 w 0x000c frsv0 r00000000 w 0x000d frsv1 r00000000 w 0x000e feccrhi r eccr15 eccr14 eccr13 eccr12 eccr11 eccr10 eccr9 eccr8 w 0x000f feccrlo r eccr7 eccr6 eccr5 eccr4 eccr3 eccr2 eccr1 eccr0 w address & name 76543210 figure 19-4. ftmr128k1 register summary (continued)
128 kbyte flash module (s12xftmr128k1v1) s12xs family reference manual, rev. 1.10 566 freescale semiconductor 19.3.2.1 flash clock divider register (fclkdiv) the fclkdiv register is used to control timed events in program and erase algorithms. all bits in the fclkdiv register are readable, bits 6? are write once and bit 7 is not writable. 0x0010 fopt r nv7 nv6 nv5 nv4 nv3 nv2 nv1 nv0 w 0x0011 frsv2 r00000000 w 0x0012 frsv3 r00000000 w 0x0013 frsv4 r00000000 w = unimplemented or reserved offset module base + 0x0000 76543210 r fdivld fdiv[6:0] w reset 00000000 = unimplemented or reserved figure 19-5. flash clock divider register (fclkdiv) table 19-6. fclkdiv field descriptions field description 7 fdivld clock divider loaded 0 fclkdiv register has not been written 1 fclkdiv register has been written since the last reset 6? fdiv[6:0] clock divider bits ?fdiv[6:0] must be set to effectively divide oscclk down to generate an internal flash clock, fclk, with a target frequency of 1 mhz for use by the flash module to control timed events during program and erase algorithms. table 19-7 shows recommended values for fdiv[6:0] based on oscclk frequency. please refer to section 19.4.1, ?lash command operations , for more information. address & name 76543210 figure 19-4. ftmr128k1 register summary (continued)
128 kbyte flash module (s12xftmr128k1v1) s12xs family reference manual, rev. 1.10 freescale semiconductor 567 caution the fclkdiv register should never be written while a flash command is executing (ccif=0). the fclkdiv register is writable during the flash reset sequence even though ccif is clear.
128 kbyte flash module (s12xftmr128k1v1) s12xs family reference manual, rev. 1.10 568 freescale semiconductor table 19-7. fdiv vs oscclk frequency oscclk frequency (mhz) fdiv[6:0] oscclk frequency (mhz) fdiv[6:0] min 1 1 fdiv shown generates an fclk frequency of >0.8 mhz max 2 2 fdiv shown generates an fclk frequency of 1.05 mhz min 1 max 2 1.60 2.10 0x01 33.60 34.65 0x20 2.40 3.15 0x02 34.65 35.70 0x21 3.20 4.20 0x03 35.70 36.75 0x22 4.20 5.25 0x04 36.75 37.80 0x23 5.25 6.30 0x05 37.80 38.85 0x24 6.30 7.35 0x06 38.85 39.90 0x25 7.35 8.40 0x07 39.90 40.95 0x26 8.40 9.45 0x08 40.95 42.00 0x27 9.45 10.50 0x09 42.00 43.05 0x28 10.50 11.55 0x0a 43.05 44.10 0x29 11.55 12.60 0x0b 44.10 45.15 0x2a 12.60 13.65 0x0c 45.15 46.20 0x2b 13.65 14.70 0x0d 46.20 47.25 0x2c 14.70 15.75 0x0e 47.25 48.30 0x2d 15.75 16.80 0x0f 48.30 49.35 0x2e 16.80 17.85 0x10 49.35 50.40 0x2f 17.85 18.90 0x11 18.90 19.95 0x12 19.95 21.00 0x13 21.00 22.05 0x14 22.05 23.10 0x15 23.10 24.15 0x16 24.15 25.20 0x17 25.20 26.25 0x18 26.25 27.30 0x19 27.30 28.35 0x1a 28.35 29.40 0x1b 29.40 30.45 0x1c 30.45 31.50 0x1d 31.50 32.55 0x1e 32.55 33.60 0x1f
128 kbyte flash module (s12xftmr128k1v1) s12xs family reference manual, rev. 1.10 freescale semiconductor 569 19.3.2.2 flash security register (fsec) the fsec register holds all bits associated with the security of the mcu and flash module. all bits in the fsec register are readable but not writable. during the reset sequence, the fsec register is loaded with the contents of the flash security byte in the flash configuration field at global address 0x7f_ff0f located in p-flash memory (see table 19-3 ) as indicated by reset condition f in figure 19-6 . if a double bit fault is detected while reading the p-flash phrase containing the flash security byte during the reset sequence, all bits in the fsec register will be set to leave the flash module in a secured state with backdoor key access disabled. offset module base + 0x0001 76543210 r keyen[1:0] rnv[5:2] sec[1:0] w reset f f ffffff = unimplemented or reserved figure 19-6. flash security register (fsec) table 19-8. fsec field descriptions field description 7? keyen[1:0] backdoor key security enable bits the keyen[1:0] bits de?e the enabling of backdoor key access to the flash module as shown in table 19-9 . 5? rnv[5:2} reserved nonvolatile bits ?the rnv bits should remain in the erased state for future enhancements. 1? sec[1:0] flash security bits ?the sec[1:0] bits de?e the security state of the mcu as shown in table 19-10 . if the flash module is unsecured using backdoor key access, the sec bits are forced to 10. table 19-9. flash keyen states keyen[1:0] status of backdoor key access 00 disabled 01 disabled 1 1 preferred keyen state to disable backdoor key access. 10 enabled 11 disabled table 19-10. flash security states sec[1:0] status of security 00 secured 01 secured 1 10 unsecured 11 secured
128 kbyte flash module (s12xftmr128k1v1) s12xs family reference manual, rev. 1.10 570 freescale semiconductor the security function in the flash module is described in section 19.5 . 19.3.2.3 flash ccob index register (fccobix) the fccobix register is used to index the fccob register for flash memory operations. ccobix bits are readable and writable while remaining bits read 0 and are not writable. 19.3.2.4 flash eccr index register (feccrix) the feccrix register is used to index the feccr register for ecc fault reporting. eccrix bits are readable and writable while remaining bits read 0 and are not writable. 1 preferred sec state to set mcu to secured state. offset module base + 0x0002 76543210 r00000 ccobix[2:0] w reset 00000000 = unimplemented or reserved figure 19-7. fccob index register (fccobix) table 19-11. fccobix field descriptions field description 2? ccobix[1:0] common command register index the ccobix bits are used to select which word of the fccob register array is being read or written to. see section 19.3.2.11, ?lash common command object register (fccob) , for more details. offset module base + 0x0003 76543210 r00000 eccrix[2:0] w reset 00000000 = unimplemented or reserved figure 19-8. feccr index register (feccrix) table 19-12. feccrix field descriptions field description 2-0 eccrix[2:0] ecc error register index ?the eccrix bits are used to select which word of the feccr register array is being read. see section 19.3.2.14, ?lash ecc error results register (feccr) , for more details.
128 kbyte flash module (s12xftmr128k1v1) s12xs family reference manual, rev. 1.10 freescale semiconductor 571 19.3.2.5 flash con?uration register (fcnfg) the fcnfg register enables the flash command complete interrupt and forces ecc faults on flash array read access from the cpu or xgate. ccie, ignsf, fdfd, and fsfd bits are readable and writable while remaining bits read 0 and are not writable. 19.3.2.6 flash error con?uration register (fercnfg) the fercnfg register enables the flash error interrupts for the ferstat flags. offset module base + 0x0004 76543210 r ccie 00 ignsf 00 fdfd fsfd w reset 00000000 = unimplemented or reserved figure 19-9. flash con?uration register (fcnfg) table 19-13. fcnfg field descriptions field description 7 ccie command complete interrupt enable ?the ccie bit controls interrupt generation when a flash command has completed. 0 command complete interrupt disabled 1 an interrupt will be requested whenever the ccif ?g in the fstat register is set (see section 19.3.2.7 ) 4 ignsf ignore single bit fault ?the ignsf controls single bit fault reporting in the ferstat register (see section 19.3.2.8 ). 0 all single bit faults detected during array reads are reported 1 single bit faults detected during array reads are not reported and the single bit fault interrupt will not be generated 1 fdfd force double bit fault detect the fdfd bit allows the user to simulate a double bit fault during flash array read operations and check the associated interrupt routine. the fdfd bit is cleared by writing a 0 to fdfd. the feccr registers will not be updated during the flash array read operation with fdfd set unless an actual double bit fault is detected. 0 flash array read operations will set the dfdif ?g in the ferstat register only if a double bit fault is detected 1 any flash array read operation will force the dfdif ?g in the ferstat register to be set (see section 19.3.2.7 ) and an interrupt will be generated as long as the dfdie interrupt enable in the fercnfg register is set (see section 19.3.2.6 ) 0 fsfd force single bit fault detect the fsfd bit allows the user to simulate a single bit fault during flash array read operations and check the associated interrupt routine. the fsfd bit is cleared by writing a 0 to fsfd. the feccr registers will not be updated during the flash array read operation with fsfd set unless an actual single bit fault is detected. 0 flash array read operations will set the sfdif ?g in the ferstat register only if a single bit fault is detected 1 flash array read operation will force the sfdif ?g in the ferstat register to be set (see section 19.3.2.7 ) and an interrupt will be generated as long as the sfdie interrupt enable in the fercnfg register is set (see section 19.3.2.6 )
128 kbyte flash module (s12xftmr128k1v1) s12xs family reference manual, rev. 1.10 572 freescale semiconductor all assigned bits in the fercnfg register are readable and writable. 19.3.2.7 flash status register (fstat) the fstat register reports the operational status of the flash module. ccif, accerr, and fpviol bits are readable and writable, mgbusy and mgstat bits are readable but not writable, while remaining bits read 0 and are not writable. offset module base + 0x0005 76543210 r 0 dfdie sfdie w reset 00000000 = unimplemented or reserved figure 19-10. flash error con?uration register (fercnfg) table 19-14. fercnfg field descriptions field description 1 dfdie double bit fault detect interrupt enable the dfdie bit controls interrupt generation when a double bit fault is detected during a flash block read operation. 0 dfdif interrupt disabled 1 an interrupt will be requested whenever the dfdif ?g is set (see section 19.3.2.8 ) 0 sfdie single bit fault detect interrupt enable the sfdie bit controls interrupt generation when a single bit fault is detected during a flash block read operation. 0 sfdif interrupt disabled whenever the sfdif ?g is set (see section 19.3.2.8 ) 1 an interrupt will be requested whenever the sfdif ?g is set (see section 19.3.2.8 ) offset module base + 0x0006 76543210 r ccif 0 accerr fpviol mgbusy rsvd mgstat[1:0] w reset 1000000 1 1 reset value can deviate from the value shown if a double bit fault is detected during the reset sequence (see section 19.6 ). 0 1 = unimplemented or reserved figure 19-11. flash status register (fstat)
128 kbyte flash module (s12xftmr128k1v1) s12xs family reference manual, rev. 1.10 freescale semiconductor 573 19.3.2.8 flash error status register (ferstat) the ferstat register re?cts the error status of internal flash operations. all ?gs in the ferstat register are readable and only writable to clear the ?g. table 19-15. fstat field descriptions field description 7 ccif command complete interrupt flag ?the ccif ?g indicates that a flash command has completed. the ccif ?g is cleared by writing a 1 to ccif to launch a command and ccif will stay low until command completion or command violation. 0 flash command in progress 1 flash command has completed 5 accerr flash access error flag ?the accerr bit indicates an illegal access has occurred to the flash memory caused by either a violation of the command write sequence (see section 19.4.1.2 ) or issuing an illegal flash command. while accerr is set, the ccif ?g cannot be cleared to launch a command. the accerr bit is cleared by writing a 1 to accerr. writing a 0 to the accerr bit has no effect on accerr. 0 no access error detected 1 access error detected 4 fpviol flash protection violation flag ?he fpviol bit indicates an attempt was made to program or erase an address in a protected area of p-flash or d-flash memory during a command write sequence. the fpviol bit is cleared by writing a 1 to fpviol. writing a 0 to the fpviol bit has no effect on fpviol. while fpviol is set, it is not possible to launch a command or start a command write sequence. 0 no protection violation detected 1 protection violation detected 3 mgbusy memory controller busy flag ?the mgbusy ?g re?cts the active state of the memory controller . 0 memory controller is idle 1 memory controller is busy executing a flash command (ccif = 0) 2 rsvd reserved bit ?this bit is reserved and always reads 0 . 1? mgstat[1:0] memory controller command completion status flag one or more mgstat ?g bits are set if an error is detected during execution of a flash command or during the flash reset sequence. see section 19.4.2, ?lash command description , and section 19.6, ?nitialization ?for details. offset module base + 0x0007 76543210 r000000 dfdif sfdif w reset 00000000 = unimplemented or reserved figure 19-12. flash error status register (ferstat)
128 kbyte flash module (s12xftmr128k1v1) s12xs family reference manual, rev. 1.10 574 freescale semiconductor 19.3.2.9 p-flash protection register (fprot) the fprot register defines which p-flash sectors are protected against program and erase operations. the (unreserved) bits of the fprot register are writable with the restriction that the size of the protected region can only be increased (see section 19.3.2.9.1, ?-flash protection restrictions , and table 19-21 ). during the reset sequence, the fprot register is loaded with the contents of the p-flash protection byte in the flash configuration field at global address 0x7f_ff0c located in p-flash memory (see table 19-3 ) as indicated by reset condition ??in figure 19-13 . to change the p-flash protection that will be loaded during the reset sequence, the upper sector of the p-flash memory must be unprotected, then the p-flash protection byte must be reprogrammed. if a double bit fault is detected while reading the p-flash phrase containing the p-flash protection byte during the reset sequence, the fpopen bit will be cleared and remaining bits in the fprot register will be set to leave the p-flash memory fully protected. trying to alter data in any protected area in the p-flash memory will result in a protection violation error and the fpviol bit will be set in the fstat register. the block erase of a p-flash block is not possible if any of the p-flash sectors contained in the same p-flash block are protected. table 19-16. ferstat field descriptions field description 1 dfdif double bit fault detect interrupt flag ?the setting of the dfdif ?g indicates that a double bit fault was detected in the stored parity and data bits during a flash array read operation or that a flash array read operation was attempted on a flash block that was under a flash command operation. the dfdif ?g is cleared by writing a 1 to dfdif. writing a 0 to dfdif has no effect on dfdif. 0 no double bit fault detected 1 double bit fault detected or an invalid flash array read operation attempted 0 sfdif single bit fault detect interrupt flag ?with the ignsf bit in the fcnfg register clear, the sfdif ?g indicates that a single bit fault was detected in the stored parity and data bits during a flash array read operation or that a flash array read operation was attempted on a flash block that was under a flash command operation. the sfdif ?g is cleared by writing a 1 to sfdif. writing a 0 to sfdif has no effect on sfdif. 0 no single bit fault detected 1 single bit fault detected and corrected or an invalid flash array read operation attempted offset module base + 0x0008 76543210 r fpopen rnv6 fphdis fphs[1:0] fpldis fpls[1:0] w reset f f ffffff = unimplemented or reserved figure 19-13. flash protection register (fprot)
128 kbyte flash module (s12xftmr128k1v1) s12xs family reference manual, rev. 1.10 freescale semiconductor 575 table 19-17. fprot field descriptions field description 7 fpopen flash protection operation enable ?the fpopen bit determines the protection function for program or erase operations as shown in table 19-18 for the p-flash block. 0 when fpopen is clear, the fphdis and fpldis bits de?e unprotected address ranges as speci?d by the corresponding fphs and fpls bits 1 when fpopen is set, the fphdis and fpldis bits enable protection for the address range speci?d by the corresponding fphs and fpls bits 6 rnv[6] reserved nonvolatile bit ?the rnv bit should remain in the erased state for future enhancements. 5 fphdis flash protection higher address range disable ?the fphdis bit determines whether there is a protected/unprotected area in a speci? region of the p-flash memory ending with global address 0x7f_ffff. 0 protection/unprotection enabled 1 protection/unprotection disabled 4? fphs[1:0] flash protection higher address size the fphs bits determine the size of the protected/unprotected area in p-flash memory as shown in table 19-19 . the fphs bits can only be written to while the fphdis bit is set. 2 fpldis flash protection lower address range disable ?the fpldis bit determines whether there is a protected/unprotected area in a speci? region of the p-flash memory beginning with global address 0x7f_8000. 0 protection/unprotection enabled 1 protection/unprotection disabled 1? fpls[1:0] flash protection lower address size the fpls bits determine the size of the protected/unprotected area in p-flash memory as shown in table 19-20 . the fpls bits can only be written to while the fpldis bit is set. table 19-18. p-flash protection function fpopen fphdis fpldis function 1 1 for range sizes, refer to table 19-19 and table 19-20 . 1 1 1 no p-flash protection 1 1 0 protected low range 1 0 1 protected high range 1 0 0 protected high and low ranges 0 1 1 full p-flash memory protected 0 1 0 unprotected low range 0 0 1 unprotected high range 0 0 0 unprotected high and low ranges table 19-19. p-flash protection higher address range fphs[1:0] global address range protected size 00 0x7f_f800?x7f_ffff 2 kbytes 01 0x7f_f000?x7f_ffff 4 kbytes 10 0x7f_e000?x7f_ffff 8 kbytes 11 0x7f_c000?x7f_ffff 16 kbytes
128 kbyte flash module (s12xftmr128k1v1) s12xs family reference manual, rev. 1.10 576 freescale semiconductor all possible p-flash protection scenarios are shown in figure 19-14 . although the protection scheme is loaded from the flash memory at global address 0x7f_ff0c during the reset sequence, it can be changed by the user. the p-flash protection scheme can be used by applications requiring reprogramming in single chip mode while providing as much protection as possible if reprogramming is not required. table 19-20. p-flash protection lower address range fpls[1:0] global address range protected size 00 0x7f_8000?x7f_83ff 1 kbyte 01 0x7f_8000?x7f_87ff 2 kbytes 10 0x7f_8000?x7f_8fff 4 kbytes 11 0x7f_8000?x7f_9fff 8 kbytes
128 kbyte flash module (s12xftmr128k1v1) s12xs family reference manual, rev. 1.10 freescale semiconductor 577 figure 19-14. p-flash protection scenarios 7 6 5 4 fphs[1:0] fpls[1:0] 3 2 1 0 fphs[1:0] fpls[1:0] fphdis = 1 fpldis = 1 fphdis = 1 fpldis = 0 fphdis = 0 fpldis = 1 fphdis = 0 fpldis = 0 scenario scenario unprotected region protected region with size protected region protected region with size defined by fpls defined by fphs not defined by fpls, fphs 0x7f_8000 0x7f_ffff 0x7f_8000 0x7f_ffff flash start flash start fpopen = 1 fpopen = 0
128 kbyte flash module (s12xftmr128k1v1) s12xs family reference manual, rev. 1.10 578 freescale semiconductor 19.3.2.9.1 p-flash protection restrictions the general guideline is that p-flash protection can only be added and not removed. table 19-21 specifies all valid transitions between p-flash protection scenarios. any attempt to write an invalid scenario to the fprot register will be ignored. the contents of the fprot register reflect the active protection scenario. see the fphs and fpls bit descriptions for additional restrictions. 19.3.2.10 d-flash protection register (dfprot) the dfprot register de?es which d-flash sectors are protected against program and erase operations. the (unreserved) bits of the dfprot register are writable with the restriction that protection can be added but not removed. writes must increase the dps value and the dpoen bit can only be written from 1 (protection disabled) to 0 (protection enabled). if the dpopen bit is set, the state of the dps bits is irrelevant. during the reset sequence, the dfprot register is loaded with the contents of the d-flash protection byte in the flash configuration field at global address 0x7f_ff0d located in p-flash memory (see table 19-3 ) as indicated by reset condition f in figure 19-15 . to change the d-flash protection that will be loaded during the reset sequence, the p-flash sector containing the d-flash protection byte must be unprotected, then the d-flash protection byte must be programmed. if a double bit fault is detected while reading the table 19-21. p-flash protection scenario transitions from protection scenario to protection scenario 1 1 allowed transitions marked with x, see figure 19-14 for a de?ition of the scenarios. 01234567 0 xxxx 1 xx 2 xx 3 x 4 xx 5 xxxx 6 xxxx 7 xxxxxxxx offset module base + 0x0009 76543210 r dpopen 00 dps[4:0] w reset f 0 0 fffff = unimplemented or reserved figure 19-15. d-flash protection register (dfprot)
128 kbyte flash module (s12xftmr128k1v1) s12xs family reference manual, rev. 1.10 freescale semiconductor 579 p-flash phrase containing the d-flash protection byte during the reset sequence, the dpopen bit will be cleared and dps bits will be set to leave the d-flash memory fully protected. trying to alter data in any protected area in the d-flash memory will result in a protection violation error and the fpviol bit will be set in the fstat register. block erase of the d-flash memory is not possible if any of the d-flash sectors are protected. table 19-22. dfprot field descriptions field description 7 dpopen d-flash protection control 0 enables d-flash memory protection from program and erase with protected address range de?ed by dps bits 1 disables d-flash memory protection from program and erase 4? dps[4:0] d-flash protection size the dps[4:0] bits determine the size of the protected area in the d-flash memory as shown in table 19-23 . table 19-23. d-flash protection address range dps[4:0] global address range protected size 0_0000 0x10_0000 ?0x10_00ff 256 bytes 0_0001 0x10_0000 ?0x10_01ff 512 bytes 0_0010 0x10_0000 ?0x10_02ff 768 bytes 0_0011 0x10_0000 ?0x10_03ff 1024 bytes 0_0100 0x10_0000 ?0x10_04ff 1280 bytes 0_0101 0x10_0000 ?0x10_05ff 1536 bytes 0_0110 0x10_0000 ?0x10_06ff 1792 bytes 0_0111 0x10_0000 ?0x10_07ff 2048 bytes 0_1000 0x10_0000 ?0x10_08ff 2304 bytes 0_1001 0x10_0000 ?0x10_09ff 2560 bytes 0_1010 0x10_0000 ?0x10_0aff 2816 bytes 0_1011 0x10_0000 ?0x10_0bff 3072 bytes 0_1100 0x10_0000 ?0x10_0cff 3328 bytes 0_1101 0x10_0000 ?0x10_0dff 3584 bytes 0_1110 0x10_0000 ?0x10_0eff 3840 bytes 0_1111 0x10_0000 ?0x10_0fff 4096 bytes 1_0000 0x10_0000 ?0x10_10ff 4352 bytes 1_0001 0x10_0000 ?0x10_11ff 4608 bytes 1_0010 0x10_0000 ?0x10_12ff 4864 bytes 1_0011 0x10_0000 ?0x10_13ff 5120 bytes 1_0100 0x10_0000 ?0x10_14ff 5376 bytes 1_0101 0x10_0000 ?0x10_15ff 5632 bytes
128 kbyte flash module (s12xftmr128k1v1) s12xs family reference manual, rev. 1.10 580 freescale semiconductor 19.3.2.11 flash common command object register (fccob) the fccob is an array of six words addressed via the ccobix index found in the fccobix register. byte wide reads and writes are allowed to the fccob register. 19.3.2.11.1 fccob - nvm command mode nvm command mode uses the indexed fccob register to provide a command code and its relevant parameters to the memory controller. the user first sets up all required fccob fields and then initiates the command? execution by writing a 1 to the ccif bit in the fstat register (a 1 written by the user clears the ccif command completion flag to 0). when the user clears the ccif bit in the fstat register all fccob parameter fields are locked and cannot be changed by the user until the command completes 1_0110 0x10_0000 ?0x10_16ff 5888 bytes 1_0111 0x10_0000 ?0x10_17ff 6144 bytes 1_1000 0x10_0000 ?0x10_18ff 6400 bytes 1_1001 0x10_0000 ?0x10_19ff 6656 bytes 1_1010 0x10_0000 ?0x10_1aff 6912 bytes 1_1011 0x10_0000 ?0x10_1bff 7168 bytes 1_1100 0x10_0000 ?0x10_1cff 7424 bytes 1_1101 0x10_0000 ?0x10_1dff 7680 bytes 1_1110 0x10_0000 ?0x10_1eff 7936 bytes 1_1111 0x10_0000 ?0x10_1fff 8192 bytes offset module base + 0x000a 76543210 r ccob[15:8] w reset 00000000 figure 19-16. flash common command object high register (fccobhi) offset module base + 0x000b 76543210 r ccob[7:0] w reset 00000000 figure 19-17. flash common command object low register (fccoblo) table 19-23. d-flash protection address range dps[4:0] global address range protected size
128 kbyte flash module (s12xftmr128k1v1) s12xs family reference manual, rev. 1.10 freescale semiconductor 581 (as evidenced by the memory controller returning ccif to 1). some commands return information to the fccob register array. the generic format for the fccob parameter fields in nvm command mode is shown in table 19-24 . the return values are available for reading after the ccif flag in the fstat register has been returned to 1 by the memory controller. writes to the unimplemented parameter fields (ccobix = 110 and ccobix = 111) are ignored with reads from these fields returning 0x0000. table 19-24 shows the generic flash command format. the high byte of the first word in the ccob array contains the command code, followed by the parameters for this specific flash command. for details on the fccob settings required by each command, see the flash command descriptions in section 19.4.2 . 19.3.2.12 flash reserved0 register (frsv0) this flash register is reserved for factory testing. all bits in the frsv0 register read 0 and are not writable. table 19-24. fccob - nvm command mode (typical usage) ccobix[2:0] byte fccob parameter fields (nvm command mode) 000 hi fcmd[7:0] de?ing flash command lo 0, global address [22:16] 001 hi global address [15:8] lo global address [7:0] 010 hi data 0 [15:8] lo data 0 [7:0] 011 hi data 1 [15:8] lo data 1 [7:0] 100 hi data 2 [15:8] lo data 2 [7:0] 101 hi data 3 [15:8] lo data 3 [7:0] offset module base + 0x000c 76543210 r00000000 w reset 00000000 = unimplemented or reserved figure 19-18. flash reserved0 register (frsv0)
128 kbyte flash module (s12xftmr128k1v1) s12xs family reference manual, rev. 1.10 582 freescale semiconductor 19.3.2.13 flash reserved1 register (frsv1) this flash register is reserved for factory testing. all bits in the frsv1 register read 0 and are not writable. 19.3.2.14 flash ecc error results register (feccr) the feccr registers contain the result of a detected ecc fault for both single bit and double bit faults. the feccr register provides access to several ecc related fields as defined by the eccrix index bits in the feccrix register (see section 19.3.2.4 ). once ecc fault information has been stored, no other fault information will be recorded until the specific ecc fault flag has been cleared. in the event of simultaneous ecc faults the priority for fault recording is double bit fault over single bit fault. all feccr bits are readable but not writable. offset module base + 0x000d 76543210 r00000000 w reset 00000000 = unimplemented or reserved figure 19-19. flash reserved1 register (frsv1) offset module base + 0x000e 76543210 r eccr[15:8] w reset 00000000 = unimplemented or reserved figure 19-20. flash ecc error results high register (feccrhi) offset module base + 0x000f 76543210 r eccr[7:0] w reset 00000000 = unimplemented or reserved figure 19-21. flash ecc error results low register (feccrlo)
128 kbyte flash module (s12xftmr128k1v1) s12xs family reference manual, rev. 1.10 freescale semiconductor 583 the p-flash word addressed by eccrix = 001 contains the lower 16 bits of the global address. the following four words addressed by eccrix = 010 to 101 contain the 64-bit wide data phrase. the four data words and the parity byte are the uncorrected data read from the p-flash block. the d-flash word addressed by eccrix = 001 contains the lower 16 bits of the global address. the uncorrected 16-bit data word is addressed by eccrix = 010. 19.3.2.15 flash option register (fopt) the fopt register is the flash option register. all bits in the fopt register are readable but are not writable. table 19-25. feccr index settings eccrix[2:0] feccr register content bits [15:8] bit[7] bits[6:0] 000 parity bits read from flash block 0 global address [22:16] 001 global address [15:0] 010 data 0 [15:0] 011 data 1 [15:0] (p-flash only) 100 data 2 [15:0] (p-flash only) 101 data 3 [15:0] (p-flash only) 110 not used, returns 0x0000 when read 111 not used, returns 0x0000 when read table 19-26. feccr index=000 bit descriptions field description 15:8 par[7:0] ecc parity bits ?contains the 8 parity bits from the 72 bit wide p-flash data word or the 6 parity bits, allocated to par[5:0], from the 22 bit wide d-flash word with par[7:6]=00. 6? gaddr[22:16] global address ?the gaddr[22:16] ?ld contains the upper seven bits of the global address having caused the error. offset module base + 0x0010 76543210 r nv[7:0] w reset f f ffffff = unimplemented or reserved figure 19-22. flash option register (fopt)
128 kbyte flash module (s12xftmr128k1v1) s12xs family reference manual, rev. 1.10 584 freescale semiconductor during the reset sequence, the fopt register is loaded from the flash nonvolatile byte in the flash configuration field at global address 0x7f_ff0e located in p-flash memory (see table 19-3 ) as indicated by reset condition f in figure 19-22 . if a double bit fault is detected while reading the p-flash phrase containing the flash nonvolatile byte during the reset sequence, all bits in the fopt register will be set. 19.3.2.16 flash reserved2 register (frsv2) this flash register is reserved for factory testing. all bits in the frsv2 register read 0 and are not writable. 19.3.2.17 flash reserved3 register (frsv3) this flash register is reserved for factory testing. all bits in the frsv3 register read 0 and are not writable. 19.3.2.18 flash reserved4 register (frsv4) this flash register is reserved for factory testing. table 19-27. fopt field descriptions field description 7? nv[7:0] nonvolatile bits the nv[7:0] bits are available as nonvolatile bits. refer to the device user guide for proper use of the nv bits. offset module base + 0x0011 76543210 r00000000 w reset 00000000 = unimplemented or reserved figure 19-23. flash reserved2 register (frsv2) offset module base + 0x0012 76543210 r00000000 w reset 00000000 = unimplemented or reserved figure 19-24. flash reserved3 register (frsv3)
128 kbyte flash module (s12xftmr128k1v1) s12xs family reference manual, rev. 1.10 freescale semiconductor 585 all bits in the frsv4 register read 0 and are not writable. 19.4 functional description 19.4.1 flash command operations flash command operations are used to modify flash memory contents. the next sections describe: how to write the fclkdiv register that is used to generate a time base (fclk) derived from oscclk for flash program and erase command operations the command write sequence used to set flash command parameters and launch execution valid flash commands available for execution 19.4.1.1 writing the fclkdiv register prior to issuing any flash program or erase command after a reset, the user is required to write the fclkdiv register to divide oscclk down to a target fclk of 1 mhz. table 19-7 shows recommended values for the fdiv ?ld based on oscclk frequency. note programming or erasing the flash memory cannot be performed if the bus clock runs at less than 1 mhz. setting fdiv too high can destroy the flash memory due to overstress. setting fdiv too low can result in incomplete programming or erasure of the flash memory cells. when the fclkdiv register is written, the fdivld bit is set automatically. if the fdivld bit is 0, the fclkdiv register has not been written since the last reset. if the fclkdiv register has not been written, any flash program or erase command loaded during a command write sequence will not execute and the accerr bit in the fstat register will set. offset module base + 0x0013 76543210 r00000000 w reset 00000000 = unimplemented or reserved figure 19-25. flash reserved4 register (frsv4)
128 kbyte flash module (s12xftmr128k1v1) s12xs family reference manual, rev. 1.10 586 freescale semiconductor 19.4.1.2 command write sequence the memory controller will launch all valid flash commands entered using a command write sequence. before launching a command, the accerr and fpviol bits in the fstat register must be clear (see section 19.3.2.7 ) and the ccif flag should be tested to determine the status of the current command write sequence. if ccif is 0, the previous command write sequence is still active, a new command write sequence cannot be started, and all writes to the fccob register are ignored. caution writes to any flash register must be avoided while a flash command is active (ccif=0) to prevent corruption of flash register contents and memory controller behavior. 19.4.1.2.1 de?e fccob contents the fccob parameter ?lds must be loaded with all required parameters for the flash command being executed. access to the fccob parameter ?lds is controlled via the ccobix bits in the fccobix register (see section 19.3.2.3 ). the contents of the fccob parameter ?lds are transferred to the memory controller when the user clears the ccif command completion ?g in the fstat register (writing 1 clears the ccif to 0). the ccif ?g will remain clear until the flash command has completed. upon completion, the memory controller will return ccif to 1 and the fccob register will be used to communicate any results. the ?w for a generic command write sequence is shown in figure 19-26 .
128 kbyte flash module (s12xftmr128k1v1) s12xs family reference manual, rev. 1.10 freescale semiconductor 587 figure 19-26. generic flash command write sequence flowchart write to fccobix register write: fstat register (to launch command) clear ccif 0x80 clear accerr/fpviol 0x30 write: fstat register yes no access error and protection violation read: fstat register read: fstat register no start yes check ccif set? fccob accerr/ fpviol set? exit write: fclkdiv register read: fclkdiv register yes no clock register written check fdivld set? no bit polling for command completion check yes ccif set? to identify speci? command parameter to load. write to fccob register to load required command parameter. yes no more parameters? availability check results from previous command note: fclkdiv must be set after each reset
128 kbyte flash module (s12xftmr128k1v1) s12xs family reference manual, rev. 1.10 588 freescale semiconductor 19.4.1.3 valid flash module commands 19.4.1.4 p-flash commands table 19-29 summarizes the valid p-flash commands along with the effects of the commands on the p-flash block and other resources within the flash module. table 19-28. flash commands by mode fcmd command unsecured secured ns 1 1 unsecured normal single chip mode. nx 2 2 unsecured normal expanded mode. ss 3 3 unsecured special single chip mode. st 4 4 unsecured special mode. ns 5 5 secured normal single chip mode. nx 6 6 secured normal expanded mode. ss 7 7 secured special single chip mode. st 8 8 secured special mode. 0x01 erase verify all blocks ???????? 0x02 erase verify block ???????? 0x03 erase verify p-flash section ????? 0x04 read once ????? 0x06 program p-flash ????? 0x07 program once ????? 0x08 erase all blocks ?? ?? 0x09 erase flash block ????? 0x0a erase p-flash sector ????? 0x0b unsecure flash ?? ?? 0x0c verify backdoor access key ?? 0x0d set user margin level ????? 0x0e set field margin level ?? 0x10 erase verify d-flash section ????? 0x11 program d-flash ????? 0x12 erase d-flash sector ?????
128 kbyte flash module (s12xftmr128k1v1) s12xs family reference manual, rev. 1.10 freescale semiconductor 589 19.4.1.5 d-flash commands table 19-30 summarizes the valid d-flash commands along with the effects of the commands on the d-flash block. table 19-29. p-flash commands fcmd command function on p-flash memory 0x01 erase verify all blocks verify that all p-flash (and d-flash) blocks are erased. 0x02 erase verify block verify that a p-flash block is erased. 0x03 erase verify p-flash section verify that a given number of words starting at the address provided are erased. 0x04 read once read a dedicated 64 byte ?ld in the nonvolatile information register in p-flash block 0 that was previously programmed using the program once command. 0x06 program p-flash program a phrase in a p-flash block. 0x07 program once program a dedicated 64 byte ?ld in the nonvolatile information register in p-flash block 0 that is allowed to be programmed only once. 0x08 erase all blocks erase all p-flash (and d-flash) blocks. an erase of all flash blocks is only possible when the fpldis, fphdis, and fpopen bits in the fprot register and the dpopen bit in the dfprot register are set prior to launching the command. 0x09 erase flash block erase a p-flash (or d-flash) block. an erase of the full p-flash block is only possible when fpldis, fphdis and fpopen bits in the fprot register are set prior to launching the command. 0x0a erase p-flash sector erase all bytes in a p-flash sector. 0x0b unsecure flash supports a method of releasing mcu security by erasing all p-flash (and d-flash) blocks and verifying that all p-flash (and d-flash) blocks are erased. 0x0c verify backdoor access key supports a method of releasing mcu security by verifying a set of security keys. 0x0d set user margin level speci?s a user margin read level for all p-flash blocks. 0x0e set field margin level speci?s a ?ld margin read level for all p-flash blocks (special modes only). table 19-30. d-flash commands fcmd command function on d-flash memory 0x01 erase verify all blocks verify that all d-flash (and p-flash) blocks are erased. 0x02 erase verify block verify that the d-flash block is erased. 0x08 erase all blocks erase all d-flash (and p-flash) blocks. an erase of all flash blocks is only possible when the fpldis, fphdis, and fpopen bits in the fprot register and the dpopen bit in the dfprot register are set prior to launching the command. 0x09 erase flash block erase a d-flash (or p-flash) block. an erase of the full d-flash block is only possible when dpopen bit in the dfprot register is set prior to launching the command.
128 kbyte flash module (s12xftmr128k1v1) s12xs family reference manual, rev. 1.10 590 freescale semiconductor 19.4.2 flash command description this section provides details of all available flash commands launched by a command write sequence. the accerr bit in the fstat register will be set during the command write sequence if any of the following illegal steps are performed, causing the command not to be processed by the memory controller: starting any command write sequence that programs or erases flash memory before initializing the fclkdiv register writing an invalid command as part of the command write sequence for additional possible errors, refer to the error handling table provided for each command if a flash block is read during execution of an algorithm (ccif = 0) on that same block, the read operation will return invalid data. if the sfdif or dfdif flags were not previously set when the invalid read operation occurred, both the sfdif and dfdif flags will be set and the feccr registers will be loaded with the global address used in the invalid read operation with the data and parity fields set to all 0. if the accerr or fpviol bits are set in the fstat register, the user must clear these bits before starting any command write sequence (see section 19.3.2.7 ). caution a flash word or phrase must be in the erased state before being programmed. cumulative programming of bits within a flash word or phrase is not allowed. 19.4.2.1 erase verify all blocks command the erase verify all blocks command will verify that all p-flash and d-flash blocks have been erased. 0x0b unsecure flash supports a method of releasing mcu security by erasing all d-flash (and p-flash) blocks and verifying that all d-flash (and p-flash) blocks are erased. 0x0d set user margin level speci?s a user margin read level for the d-flash block. 0x0e set field margin level speci?s a ?ld margin read level for the d-flash block (special modes only). 0x10 erase verify d-flash section verify that a given number of words starting at the address provided are erased. 0x11 program d-flash program up to four words in the d-flash block. 0x12 erase d-flash sector erase all bytes in a sector of the d-flash block. table 19-31. erase verify all blocks command fccob requirements ccobix[2:0] fccob parameters 000 0x01 not required table 19-30. d-flash commands fcmd command function on d-flash memory
128 kbyte flash module (s12xftmr128k1v1) s12xs family reference manual, rev. 1.10 freescale semiconductor 591 upon clearing ccif to launch the erase verify all blocks command, the memory controller will verify that the entire flash memory space is erased. the ccif ?g will set after the erase verify all blocks operation has completed. 19.4.2.2 erase verify block command the erase verify block command allows the user to verify that an entire p-flash or d-flash block has been erased. the fccob upper global address bits determine which block must be veri?d. upon clearing ccif to launch the erase verify block command, the memory controller will verify that the selected p-flash or d-flash block is erased. the ccif ?g will set after the erase verify block operation has completed. 19.4.2.3 erase verify p-flash section command the erase verify p-flash section command will verify that a section of code in the p-flash memory is erased. the erase verify p-flash section command defines the starting point of the code to be verified and the number of phrases. the section to be verified cannot cross a 128 kbyte boundary in the p-flash memory space. table 19-32. erase verify all blocks command error handling register error bit error condition fstat accerr set if ccobix[2:0] != 000 at command launch fpviol none mgstat1 set if any errors have been encountered during the read mgstat0 set if any non-correctable errors have been encountered during the read table 19-33. erase verify block command fccob requirements ccobix[2:0] fccob parameters 000 0x02 global address [22:16] of the flash block to be veri?d . table 19-34. erase verify block command error handling register error bit error condition fstat accerr set if ccobix[2:0] != 000 at command launch set if an invalid global address [22:16] is supplied fpviol none mgstat1 set if any errors have been encountered during the read mgstat0 set if any non-correctable errors have been encountered during the read
128 kbyte flash module (s12xftmr128k1v1) s12xs family reference manual, rev. 1.10 592 freescale semiconductor upon clearing ccif to launch the erase verify p-flash section command, the memory controller will verify the selected section of flash memory is erased. the ccif ?g will set after the erase verify p-flash section operation has completed. 19.4.2.4 read once command the read once command provides read access to a reserved 64 byte field (8 phrases) located in the nonvolatile information register of p-flash block 0. the read once field is programmed using the program once command described in section 19.4.2.6 . the read once command must not be executed from the flash block containing the program once reserved field to avoid code runaway. upon clearing ccif to launch the read once command, a read once phrase is fetched and stored in the fccob indexed register. the ccif ?g will set after the read once operation has completed. valid table 19-35. erase verify p-flash section command fccob requirements ccobix[2:0] fccob parameters 000 0x03 global address [22:16] of a p-flash block 001 global address [15:0] of the ?st phrase to be veri?d 010 number of phrases to be veri?d table 19-36. erase verify p-flash section command error handling register error bit error condition fstat accerr set if ccobix[2:0] != 010 at command launch set if command not available in current mode (see table 19-28 ) set if an invalid global address [22:0] is supplied set if a misaligned phrase address is supplied (global address [2:0] != 000) set if the requested section crosses a 128 kbyte boundary fpviol none mgstat1 set if any errors have been encountered during the read mgstat0 set if any non-correctable errors have been encountered during the read table 19-37. read once command fccob requirements ccobix[2:0] fccob parameters 000 0x04 not required 001 read once phrase index (0x0000 - 0x0007) 010 read once word 0 value 011 read once word 1 value 100 read once word 2 value 101 read once word 3 value
128 kbyte flash module (s12xftmr128k1v1) s12xs family reference manual, rev. 1.10 freescale semiconductor 593 phrase index values for the read once command range from 0x0000 to 0x0007. during execution of the read once command, any attempt to read addresses within p-flash block will return invalid data. 19.4.2.5 program p-flash command the program p-flash operation will program a previously erased phrase in the p-flash memory using an embedded algorithm. caution a p-flash phrase must be in the erased state before being programmed. cumulative programming of bits within a flash phrase is not allowed. upon clearing ccif to launch the program p-flash command, the memory controller will program the data words to the supplied global address and will then proceed to verify the data words read back as expected. the ccif ?g will set after the program p-flash operation has completed. table 19-38. read once command error handling register error bit error condition fstat accerr set if ccobix[2:0] != 001 at command launch set if command not available in current mode (see table 19-28 ) set if an invalid phrase index is supplied fpviol none mgstat1 set if any errors have been encountered during the read mgstat0 set if any non-correctable errors have been encountered during the read table 19-39. program p-flash command fccob requirements ccobix[2:0] fccob parameters 000 0x06 global address [22:16] to identify p-flash block 001 global address [15:0] of phrase location to be programmed 1 1 global address [2:0] must be 000 010 word 0 program value 011 word 1 program value 100 word 2 program value 101 word 3 program value
128 kbyte flash module (s12xftmr128k1v1) s12xs family reference manual, rev. 1.10 594 freescale semiconductor 19.4.2.6 program once command the program once command restricts programming to a reserved 64 byte field (8 phrases) in the nonvolatile information register located in p-flash block 0. the program once reserved field can be read using the read once command as described in section 19.4.2.4 . the program once command must only be issued once since the nonvolatile information register in p-flash block 0 cannot be erased. the program once command must not be executed from the flash block containing the program once reserved field to avoid code runaway. upon clearing ccif to launch the program once command, the memory controller ?st veri?s that the selected phrase is erased. if erased, then the selected phrase will be programmed and then veri?d with read back. the ccif ?g will remain clear, setting only after the program once operation has completed. the reserved nonvolatile information register accessed by the program once command cannot be erased and any attempt to program one of these phrases a second time will not be allowed. valid phrase index values for the program once command range from 0x0000 to 0x0007. during execution of the program once command, any attempt to read addresses within p-flash block 0 will return invalid data. table 19-40. program p-flash command error handling register error bit error condition fstat accerr set if ccobix[2:0] != 101 at command launch set if command not available in current mode (see table 19-28 ) set if an invalid global address [22:0] is supplied set if a misaligned phrase address is supplied (global address [2:0] != 000) fpviol set if the global address [22:0] points to a protected area mgstat1 set if any errors have been encountered during the verify operation mgstat0 set if any non-correctable errors have been encountered during the verify operation table 19-41. program once command fccob requirements ccobix[2:0] fccob parameters 000 0x07 not required 001 program once phrase index (0x0000 - 0x0007) 010 program once word 0 value 011 program once word 1 value 100 program once word 2 value 101 program once word 3 value
128 kbyte flash module (s12xftmr128k1v1) s12xs family reference manual, rev. 1.10 freescale semiconductor 595 r, 19.4.2.7 erase all blocks command the erase all blocks operation will erase the entire p-flash and d-flash memory space. upon clearing ccif to launch the erase all blocks command, the memory controller will erase the entire flash memory space and verify that it is erased. if the memory controller veri?s that the entire flash memory space was properly erased, security will be released. during the execution of this command (ccif=0) the user must not write to any flash module register. the ccif ?g will set after the erase all blocks operation has completed. 19.4.2.8 erase flash block command the erase flash block operation will erase all addresses in a p-flash or d-flash block. table 19-42. program once command error handling register error bit error condition fstat accerr set if ccobix[2:0] != 101 at command launch set if command not available in current mode (see table 19-28 ) set if an invalid phrase index is supplied set if the requested phrase has already been programmed 1 1 if a program once phrase is initially programmed to 0xffff_ffff_ffff_ffff, the program once command will be allowed to execute again on that same phrase. fpviol none mgstat1 set if any errors have been encountered during the verify operation mgstat0 set if any non-correctable errors have been encountered during the verify operation table 19-43. erase all blocks command fccob requirements ccobix[2:0] fccob parameters 000 0x08 not required table 19-44. erase all blocks command error handling register error bit error condition fstat accerr set if ccobix[2:0] != 000 at command launch set if command not available in current mode (see table 19-28 ) fpviol set if any area of the p-flash or d-flash memory is protected mgstat1 set if any errors have been encountered during the verify operation mgstat0 set if any non-correctable errors have been encountered during the verify operation
128 kbyte flash module (s12xftmr128k1v1) s12xs family reference manual, rev. 1.10 596 freescale semiconductor upon clearing ccif to launch the erase flash block command, the memory controller will erase the selected flash block and verify that it is erased. the ccif ?g will set after the erase flash block operation has completed. 19.4.2.9 erase p-flash sector command the erase p-flash sector operation will erase all addresses in a p-flash sector. upon clearing ccif to launch the erase p-flash sector command, the memory controller will erase the selected flash sector and then verify that it is erased. the ccif ?g will be set after the erase p-flash sector operation has completed. table 19-45. erase flash block command fccob requirements ccobix[2:0] fccob parameters 000 0x09 global address [22:16] to identify flash block 001 global address [15:0] in flash block to be erased table 19-46. erase flash block command error handling register error bit error condition fstat accerr set if ccobix[2:0] != 001 at command launch set if command not available in current mode (see table 19-28 ) set if an invalid global address [22:16] is supplied set if the supplied p-flash address is not phrase-aligned or if the d-flash address is not word-aligned fpviol set if an area of the selected flash block is protected mgstat1 set if any errors have been encountered during the verify operation mgstat0 set if any non-correctable errors have been encountered during the verify operation table 19-47. erase p-flash sector command fccob requirements ccobix[2:0] fccob parameters 000 0x0a global address [22:16] to identify p-flash block to be erased 001 global address [15:0] anywhere within the sector to be erased. refer to section 19.1.2.1 for the p-flash sector size.
128 kbyte flash module (s12xftmr128k1v1) s12xs family reference manual, rev. 1.10 freescale semiconductor 597 19.4.2.10 unsecure flash command the unsecure flash command will erase the entire p-flash and d-flash memory space and, if the erase is successful, will release security. upon clearing ccif to launch the unsecure flash command, the memory controller will erase the entire p-flash and d-flash memory space and verify that it is erased. if the memory controller veri?s that the entire flash memory space was properly erased, security will be released. if the erase verify is not successful, the unsecure flash operation sets mgstat1 and terminates without changing the security state. during the execution of this command (ccif=0) the user must not write to any flash module register. the ccif ?g is set after the unsecure flash operation has completed. 19.4.2.11 verify backdoor access key command the verify backdoor access key command will only execute if it is enabled by the keyen bits in the fsec register (see table 19-9 ). the verify backdoor access key command releases security if user-supplied keys match those stored in the flash security bytes of the flash configuration field (see table 19-48. erase p-flash sector command error handling register error bit error condition fstat accerr set if ccobix[2:0] != 001 at command launch set if command not available in current mode (see table 19-28 ) set if an invalid global address [22:16] is supplied set if a misaligned phrase address is supplied (global address [2:0] != 000) fpviol set if the selected p-flash sector is protected mgstat1 set if any errors have been encountered during the verify operation mgstat0 set if any non-correctable errors have been encountered during the verify operation table 19-49. unsecure flash command fccob requirements ccobix[2:0] fccob parameters 000 0x0b not required table 19-50. unsecure flash command error handling register error bit error condition fstat accerr set if ccobix[2:0] != 000 at command launch set if command not available in current mode (see table 19-28 ) fpviol set if any area of the p-flash or d-flash memory is protected mgstat1 set if any errors have been encountered during the verify operation mgstat0 set if any non-correctable errors have been encountered during the verify operation
128 kbyte flash module (s12xftmr128k1v1) s12xs family reference manual, rev. 1.10 598 freescale semiconductor table 19-3 ). the verify backdoor access key command must not be executed from the flash block containing the backdoor comparison key to avoid code runaway. upon clearing ccif to launch the verify backdoor access key command, the memory controller will check the fsec keyen bits to verify that this command is enabled. if not enabled, the memory controller sets the accerr bit in the fstat register and terminates. if the command is enabled, the memory controller compares the key provided in fccob to the backdoor comparison key in the flash con?uration ?ld with key 0 compared to 0x7f_ff00, etc. if the backdoor keys match, security will be released. if the backdoor keys do not match, security is not released and all future attempts to execute the verify backdoor access key command are aborted (set accerr) until a reset occurs. the ccif flag is set after the verify backdoor access key operation has completed. 19.4.2.12 set user margin level command the set user margin level command causes the memory controller to set the margin level for future read operations of a specific p-flash or d-flash block. table 19-51. verify backdoor access key command fccob requirements ccobix[2:0] fccob parameters 000 0x0c not required 001 key 0 010 key 1 011 key 2 100 key 3 table 19-52. verify backdoor access key command error handling register error bit error condition fstat accerr set if ccobix[2:0] != 100 at command launch set if an incorrect backdoor key is supplied set if backdoor key access has not been enabled (keyen[1:0] != 10, see section 19.3.2.2 ) set if the backdoor key has mismatched since the last reset fpviol none mgstat1 none mgstat0 none table 19-53. set user margin level command fccob requirements ccobix[2:0] fccob parameters 000 0x0d global address [22:16] to identify the flash block 001 margin level setting
128 kbyte flash module (s12xftmr128k1v1) s12xs family reference manual, rev. 1.10 freescale semiconductor 599 upon clearing ccif to launch the set user margin level command, the memory controller will set the user margin level for the targeted block and then set the ccif ?g. valid margin level settings for the set user margin level command are de?ed in table 19-54 . note user margin levels can be used to check that flash memory contents have adequate margin for normal level read operations. if unexpected results are encountered when checking flash memory contents at user margin levels, a potential loss of information has been detected. 19.4.2.13 set field margin level command the set field margin level command, valid in special modes only, causes the memory controller to set the margin level specified for future read operations of a specific p-flash or d-flash block. table 19-54. valid set user margin level settings ccob (ccobix=001) level description 0x0000 return to normal level 0x0001 user margin-1 level 1 1 read margin to the erased state 0x0002 user margin-0 level 2 2 read margin to the programmed state table 19-55. set user margin level command error handling register error bit error condition fstat accerr set if ccobix[2:0] != 001 at command launch set if command not available in current mode (see table 19-28 ) set if an invalid global address [22:16] is supplied set if an invalid margin level setting is supplied fpviol none mgstat1 none mgstat0 none table 19-56. set field margin level command fccob requirements ccobix[2:0] fccob parameters 000 0x0e global address [22:16] to identify the flash block 001 margin level setting
128 kbyte flash module (s12xftmr128k1v1) s12xs family reference manual, rev. 1.10 600 freescale semiconductor upon clearing ccif to launch the set field margin level command, the memory controller will set the ?ld margin level for the targeted block and then set the ccif ?g. valid margin level settings for the set field margin level command are de?ed in table 19-57 . caution field margin levels must only be used during verify of the initial factory programming. note field margin levels can be used to check that flash memory contents have adequate margin for data retention at the normal level setting. if unexpected results are encountered when checking flash memory contents at ?ld margin levels, the flash memory contents should be erased and reprogrammed. 19.4.2.14 erase verify d-flash section command the erase verify d-flash section command will verify that a section of code in the d-flash is erased. the erase verify d-flash section command defines the starting point of the data to be verified and the number of words. table 19-57. valid set field margin level settings ccob (ccobix=001) level description 0x0000 return to normal level 0x0001 user margin-1 level 1 1 read margin to the erased state 0x0002 user margin-0 level 2 2 read margin to the programmed state 0x0003 field margin-1 level 1 0x0004 field margin-0 level 2 table 19-58. set field margin level command error handling register error bit error condition fstat accerr set if ccobix[2:0] != 001 at command launch set if command not available in current mode (see table 19-28 ) set if an invalid global address [22:16] is supplied set if an invalid margin level setting is supplied fpviol none mgstat1 none mgstat0 none
128 kbyte flash module (s12xftmr128k1v1) s12xs family reference manual, rev. 1.10 freescale semiconductor 601 upon clearing ccif to launch the erase verify d-flash section command, the memory controller will verify the selected section of d-flash memory is erased. the ccif ?g will set after the erase verify d-flash section operation has completed. 19.4.2.15 program d-flash command the program d-flash operation programs one to four previously erased words in the d-flash block. the program d-flash operation will confirm that the targeted location(s) were successfully programmed upon completion. caution a flash word must be in the erased state before being programmed. cumulative programming of bits within a flash word is not allowed. table 19-59. erase verify d-flash section command fccob requirements ccobix[2:0] fccob parameters 000 0x10 global address [22:16] to identify the d-flash block 001 global address [15:0] of the ?st word to be veri?d 010 number of words to be veri?d table 19-60. erase verify d-flash section command error handling register error bit error condition fstat accerr set if ccobix[2:0] != 010 at command launch set if command not available in current mode (see table 19-28 ) set if an invalid global address [22:0] is supplied set if a misaligned word address is supplied (global address [0] != 0) set if the requested section breaches the end of the d-flash block fpviol none mgstat1 set if any errors have been encountered during the read mgstat0 set if any non-correctable errors have been encountered during the read table 19-61. program d-flash command fccob requirements ccobix[2:0] fccob parameters 000 0x11 global address [22:16] to identify the d-flash block 001 global address [15:0] of word to be programmed 010 word 0 program value 011 word 1 program value, if desired 100 word 2 program value, if desired
128 kbyte flash module (s12xftmr128k1v1) s12xs family reference manual, rev. 1.10 602 freescale semiconductor upon clearing ccif to launch the program d-flash command, the user-supplied words will be transferred to the memory controller and be programmed if the area is unprotected. the ccobix index value at program d-flash command launch determines how many words will be programmed in the d-flash block. the ccif ?g is set when the operation has completed. 19.4.2.16 erase d-flash sector command the erase d-flash sector operation will erase all addresses in a sector of the d-flash block. upon clearing ccif to launch the erase d-flash sector command, the memory controller will erase the selected flash sector and verify that it is erased. the ccif ?g will set after the erase d-flash sector operation has completed. 101 word 3 program value, if desired table 19-62. program d-flash command error handling register error bit error condition fstat accerr set if ccobix[2:0] < 010 at command launch set if ccobix[2:0] > 101 at command launch set if command not available in current mode (see table 19-28 ) set if an invalid global address [22:0] is supplied set if a misaligned word address is supplied (global address [0] != 0) set if the requested group of words breaches the end of the d-flash block fpviol set if the selected area of the d-flash memory is protected mgstat1 set if any errors have been encountered during the verify operation mgstat0 set if any non-correctable errors have been encountered during the verify operation table 19-63. erase d-flash sector command fccob requirements ccobix[2:0] fccob parameters 000 0x12 global address [22:16] to identify d-flash block 001 global address [15:0] anywhere within the sector to be erased. see section 19.1.2.2 for d-flash sector size. table 19-61. program d-flash command fccob requirements ccobix[2:0] fccob parameters
128 kbyte flash module (s12xftmr128k1v1) s12xs family reference manual, rev. 1.10 freescale semiconductor 603 19.4.3 interrupts the flash module can generate an interrupt when a flash command operation has completed or when a flash command operation has detected an ecc fault. note vector addresses and their relative interrupt priority are determined at the mcu level. 19.4.3.1 description of flash interrupt operation the flash module uses the ccif ?g in combination with the ccie interrupt enable bit to generate the flash command interrupt request. the flash module uses the dfdif and sfdif ?gs in combination with the dfdie and sfdie interrupt enable bits to generate the flash error interrupt request. for a detailed description of the register bits involved, refer to section 19.3.2.5, ?lash configuration register (fcnfg) ? section 19.3.2.6, ?lash error configuration register (fercnfg) ? section 19.3.2.7, ?lash status register (fstat) ? and section 19.3.2.8, ?lash error status register (ferstat) ? the logic used for generating the flash module interrupts is shown in figure 19-27 . table 19-64. erase d-flash sector command error handling register error bit error condition fstat accerr set if ccobix[2:0] != 001 at command launch set if command not available in current mode (see table 19-28 ) set if an invalid global address [22:0] is supplied set if a misaligned word address is supplied (global address [0] != 0) fpviol set if the selected area of the d-flash memory is protected mgstat1 set if any errors have been encountered during the verify operation mgstat0 set if any non-correctable errors have been encountered during the verify operation table 19-65. flash interrupt sources interrupt source interrupt flag local enable global (ccr) mask flash command complete ccif (fstat register) ccie (fcnfg register) i bit ecc double bit fault on flash read dfdif (ferstat register) dfdie (fercnfg register) i bit ecc single bit fault on flash read sfdif (ferstat register) sfdie (fercnfg register) i bit
128 kbyte flash module (s12xftmr128k1v1) s12xs family reference manual, rev. 1.10 604 freescale semiconductor figure 19-27. flash module interrupts implementation 19.4.4 wait mode the flash module is not affected if the mcu enters wait mode. the flash module can recover the mcu from wait via the ccif interrupt (see section 19.4.3, ?nterrupts ). 19.4.5 stop mode if a flash command is active (ccif = 0) when the mcu requests stop mode, the current flash operation will be completed before the cpu is allowed to enter stop mode. 19.5 security the flash module provides security information to the mcu. the flash security state is de?ed by the sec bits of the fsec register (see table 19-10 ). during reset, the flash module initializes the fsec register using data read from the security byte of the flash con?uration ?ld at global address 0x7f_ff0f. the security state out of reset can be permanently changed by programming the security byte of the flash con?uration ?ld. this assumes that you are starting from a mode where the necessary p-flash erase and program commands are available and that the upper region of the p-flash is unprotected. if the flash security byte is successfully programmed, its new value will take affect after the next mcu reset. the following subsections describe these security-related subjects: unsecuring the mcu using backdoor key access unsecuring the mcu in special single chip mode using bdm mode and security effects on flash command availability 19.5.1 unsecuring the mcu using backdoor key access the mcu may be unsecured by using the backdoor key access feature which requires knowledge of the contents of the backdoor keys (four 16-bit words programmed at addresses 0x7f_ff00?x7f_ff07). if the keyen[1:0] bits are in the enabled state (see section 19.3.2.2 ), the verify backdoor access key command (see section 19.4.2.11 ) allows the user to present four prospective keys for comparison to the flash error interrupt request ccif ccie dfdif dfdie sfdif sfdie flash command interrupt request
128 kbyte flash module (s12xftmr128k1v1) s12xs family reference manual, rev. 1.10 freescale semiconductor 605 keys stored in the flash memory via the memory controller. if the keys presented in the verify backdoor access key command match the backdoor keys stored in the flash memory, the sec bits in the fsec register (see table 19-10 ) will be changed to unsecure the mcu. key values of 0x0000 and 0xffff are not permitted as backdoor keys. while the verify backdoor access key command is active, p-flash block 0 will not be available for read access and will return invalid data. the user code stored in the p-flash memory must have a method of receiving the backdoor keys from an external stimulus. this external stimulus would typically be through one of the on-chip serial ports. if the keyen[1:0] bits are in the enabled state (see section 19.3.2.2 ), the mcu can be unsecured by the backdoor key access sequence described below: 1. follow the command sequence for the verify backdoor access key command as explained in section 19.4.2.11 2. if the verify backdoor access key command is successful, the mcu is unsecured and the sec[1:0] bits in the fsec register are forced to the unsecure state of 10 the verify backdoor access key command is monitored by the memory controller and an illegal key will prohibit future use of the verify backdoor access key command. a reset of the mcu is the only method to re-enable the verify backdoor access key command. after the backdoor keys have been correctly matched, the mcu will be unsecured. after the mcu is unsecured, the sector containing the flash security byte can be erased and the flash security byte can be reprogrammed to the unsecure state, if desired. in the unsecure state, the user has full control of the contents of the backdoor keys by programming addresses 0x7f_ff00?x7f_ff07 in the flash con?uration ?ld. the security as de?ed in the flash security byte (0x7f_ff0f) is not changed by using the verify backdoor access key command sequence. the backdoor keys stored in addresses 0x7f_ff00?x7f_ff07 are unaffected by the verify backdoor access key command sequence. after the next reset of the mcu, the security state of the flash module is determined by the flash security byte (0x7f_ff0f). the verify backdoor access key command sequence has no effect on the program and erase protections de?ed in the flash protection register, fprot. 19.5.2 unsecuring the mcu in special single chip mode using bdm the mcu can be unsecured in special single chip mode by erasing the p-flash and d-flash memory by one of the following methods: reset the mcu into special single chip mode, delay while the erase test is performed by the bdm, send bdm commands to disable protection in the p-flash and d-flash memory, and execute the erase all blocks command write sequence to erase the p-flash and d-flash memory. reset the mcu into special expanded wide mode, disable protection in the p-flash and d-flash memory and run code from external memory to execute the erase all blocks command write sequence to erase the p-flash and d-flash memory. after the ccif ?g sets to indicate that the erase all blocks operation has completed, reset the mcu into special single chip mode. the bdm will execute the erase verify all blocks command write sequence to verify that the p-flash and d-flash memory is erased. if the p-flash and d-flash memory are verified as
128 kbyte flash module (s12xftmr128k1v1) s12xs family reference manual, rev. 1.10 606 freescale semiconductor erased the mcu will be unsecured. all bdm commands will be enabled and the flash security byte may be programmed to the unsecure state by the following method: send bdm commands to execute a ?rogram p-flash?command sequence to program the flash security byte to the unsecured state and reset the mcu. 19.5.3 mode and security effects on flash command availability the availability of flash module commands depends on the mcu operating mode and security state as shown in table 19-28 . 19.6 initialization on each system reset the flash module executes a reset sequence which establishes initial values for the flash block configuration parameters, the fprot and dfprot protection registers, and the fopt and fsec registers. the flash module reverts to built-in default values that leave the module in a fully protected and secured state if errors are encountered during execution of the reset sequence. if a double bit fault is detected during the reset sequence, both mgstat bits in the fstat register will be set. ccif remains clear throughout the reset sequence. the flash module holds off all cpu access for the initial portion of the reset sequence. while flash reads are possible when the hold is removed, writes to the fccobix, fccobhi, and fccoblo registers are ignored to prevent command activity while the memory controller remains busy. completion of the reset sequence is marked by setting ccif high which enables writes to the fccobix, fccobhi, and fccoblo registers to launch any available flash command. if a reset occurs while any flash command is in progress, that command will be immediately aborted. the state of the word being programmed or the sector/block being erased is not guaranteed.
s12xs family reference manual, rev. 1.10 freescale semiconductor 607 preliminary chapter 20 64 kbyte flash module (s12xftmr64k1v1) 20.1 introduction the ftmr64k1 module implements the following: 64 kbytes of p-flash (program flash) memory 4 kbytes of d-flash (data flash) memory the flash memory is ideal for single-supply applications allowing for ?ld reprogramming without requiring external high voltage sources for program or erase operations. the flash module includes a memory controller that executes commands to modify flash memory contents. the user interface to the memory controller consists of the indexed flash common command object (fccob) register which is written to with the command, global address, data, and any required command parameters. the memory controller must complete the execution of a command before the fccob register can be written to with a new command. table 20-1. revision history revision number revision date sections affected description of changes v01.04 03 jan 2008 - cosmetic changes v01.05 19 dec 2008 20.1/20-607 20.4.2.4/20-642 20.4.2.6/20-644 20.4.2.11/20-64 8 20.4.2.11/20-64 8 20.4.2.11/20-64 8 - clarify single bit fault correction for p-flash phrase - add statement concerning code runaway when executing read once, program once, and verify backdoor access key commands from flash block containing associated ?lds - relate key 0 to associated backdoor comparison key address - change ?ower down reset?to ?eset?in section 20.4.2.11 v01.06 25 sep 2009 20.3.2/20-615 20.3.2.1/20-617 20.4.1.2/20-636 20.6/20-656 the following changes were made to clarify module behavior related to flash register access during reset sequence and while flash commands are active: - add caution concerning register writes while command is active - writes to fclkdiv are allowed during reset sequence while ccif is clear - add caution concerning register writes while command is active - writes to fccobix, fccobhi, fccoblo registers are ignored during reset sequence
s12xs family reference manual, rev. 1.10 freescale semiconductor 608 preliminary caution a flash word or phrase must be in the erased state before being programmed. cumulative programming of bits within a flash word or phrase is not allowed. the flash memory may be read as bytes, aligned words, or misaligned words. read access time is one bus cycle for bytes and aligned words, and two bus cycles for misaligned words. for flash memory, an erased bit reads 1 and a programmed bit reads 0. it is not possible to read from a flash block while any command is executing on that speci? flash block. it is possible to read from a flash block while a command is executing on a different flash block. both p-flash and d-flash memories are implemented with error correction codes (ecc) that can resolve single bit faults and detect double bit faults. for p-flash memory, the ecc implementation requires that programming be done on an aligned 8 byte basis (a flash phrase). since p-flash memory is always read by phrase, only one single bit fault in the phrase containing the byte or word accessed will be corrected. 20.1.1 glossary command write sequence ?an mcu instruction sequence to execute built-in algorithms (including program and erase) on the flash memory. d-flash memory ?the d-flash memory constitutes the nonvolatile memory store for data. d-flash sector the d-flash sector is the smallest portion of the d-flash memory that can be erased. the d-flash sector consists of four 64 byte rows for a total of 256 bytes. nvm command mode an nvm mode using the cpu to setup the fccob register to pass parameters required for flash command execution. phrase an aligned group of four 16-bit words within the p-flash memory. each phrase includes eight ecc bits for single bit fault correction and double bit fault detection within the phrase. p-flash memory the p-flash memory constitutes the main nonvolatile memory store for applications. p-flash sector ?the p-flash sector is the smallest portion of the p-flash memory that can be erased. each p-flash sector contains 1024 bytes. program ifr ?nonvolatile information register located in the p-flash block that contains the device id, version id, and the program once ?ld. the program ifr is visible in the global memory map by setting the pgmifron bit in the mmcctl1 register.
64 kbyte flash module (s12xftmr64k1v1) s12xs family reference manual, rev. 1.10 freescale semiconductor 609 20.1.2 features 20.1.2.1 p-flash features 64 kbytes of p-flash memory composed of one 64 kbyte flash block divided into 64 sectors of 1024 bytes single bit fault correction and double bit fault detection within a 64-bit phrase during read operations automated program and erase algorithm with verify and generation of ecc parity bits fast sector erase and phrase program operation flexible protection scheme to prevent accidental program or erase of p-flash memory 20.1.2.2 d-flash features 4 kbytes of d-flash memory composed of one 4 kbyte flash block divided into 16 sectors of 256 bytes single bit fault correction and double bit fault detection within a word during read operations automated program and erase algorithm with verify and generation of ecc parity bits fast sector erase and word program operation protection scheme to prevent accidental program or erase of d-flash memory ability to program up to four words in a burst sequence 20.1.2.3 other flash module features no external high-voltage power supply required for flash memory program and erase operations interrupt generation on flash command completion and flash error detection security mechanism to prevent unauthorized access to the flash memory
64 kbyte flash module (s12xftmr64k1v1) s12xs family reference manual, rev. 1.10 610 freescale semiconductor 20.1.3 block diagram the block diagram of the flash module is shown in figure 20-1 . figure 20-1. ftmr64k1 block diagram 20.2 external signal description the flash module contains no signals that connect off-chip. oscillator clock divider clock (xtal) command interrupt request fclk protection security registers flash interface 16bit internal bus sector 0 sector 1 sector 63 8kx72 p-flash error interrupt request cpu d-flash 2kx22 sector 0 sector 1 sector 15 scratch ram 384x16bits memory controller
64 kbyte flash module (s12xftmr64k1v1) s12xs family reference manual, rev. 1.10 freescale semiconductor 611 20.3 memory map and registers this section describes the memory map and registers for the flash module. read data from unimplemented memory space in the flash module is unde?ed. write access to unimplemented or reserved memory space in the flash module will be ignored by the flash module. 20.3.1 module memory map the s12x architecture places the p-flash memory between global addresses 0x7f_0000 and 0x7f_ffff as shown in table 20-2 . the p-flash memory map is shown in figure 20-2 . the fprot register, described in section 20.3.2.9 , can be set to protect regions in the flash memory from accidental program or erase. three separate memory regions, one growing upward from global address 0x7f_8000 in the flash memory (called the lower region), one growing downward from global address 0x7f_ffff in the flash memory (called the higher region), and the remaining addresses in the flash memory, can be activated for protection. the flash memory addresses covered by these protectable regions are shown in the p-flash memory map. the higher address region is mainly targeted to hold the boot loader code since it covers the vector space. default protection settings as well as security information that allows the mcu to restrict access to the flash module are stored in the flash con?uration ?ld as described in table 20-3 . table 20-2. p-flash memory addressing global address size (bytes) description 0x7f_0000 ?0x7f_ffff 64 k p-flash block 0 contains flash con?uration field (see table 20-3 ) table 20-3. flash con?uration field 1 1 older versions may have swapped protection byte addresses global address size (bytes) description 0x7f_ff00 ?0x7f_ff07 8 backdoor comparison key refer to section 20.4.2.11, ?erify backdoor access key command , and section 20.5.1, ?nsecuring the mcu using backdoor key access 0x7f_ff08 0x7f_ff0b 2 4 reserved 0x7f_ff0c 2 1 p-flash protection byte . refer to section 20.3.2.9, ?-flash protection register (fprot) 0x7f_ff0d 2 1 d-flash protection byte . refer to section 20.3.2.10, ?-flash protection register (dfprot) 0x7f_ff0e 2 1 flash nonvolatile byte refer to section 20.3.2.15, ?lash option register (fopt) 0x7f_ff0f 2 1 flash security byte refer to section 20.3.2.2, ?lash security register (fsec)
64 kbyte flash module (s12xftmr64k1v1) s12xs family reference manual, rev. 1.10 612 freescale semiconductor 2 0x7ff08 - 0x7f_ff0f form a flash phrase and must be programmed in a single command write sequence. each byte in the 0x7f_ff08 - 0x7f_ff0b reserved ?ld should be programmed to 0xff.
64 kbyte flash module (s12xftmr64k1v1) s12xs family reference manual, rev. 1.10 freescale semiconductor 613 figure 20-2. p-flash memory map flash con?uration field 0x7f_c000 flash protected/unprotected lower region 1, 2, 4, 8 kbytes 0x7f_8000 0x7f_9000 0x7f_8400 0x7f_8800 0x7f_a000 p-flash end = 0x7f_ffff 0x7f_f800 0x7f_f000 0x7f_e000 flash protected/unprotected higher region 2, 4, 8, 16 kbytes flash protected/unprotected region 8 kbytes (up to 29 kbytes) 16 bytes (0x7f_ff00 - 0x7f_ff0f) flash protected/unprotected region 32 kbytes p-flash start = 0x7f_0000
64 kbyte flash module (s12xftmr64k1v1) s12xs family reference manual, rev. 1.10 614 freescale semiconductor table 20-4. program ifr fields global address (pgmifron) size (bytes) field description 0x40_0000 ?0x40_0007 8 device id 0x40_0008 ?0x40_00e7 224 reserved 0x40_00e8 ?0x40_00e9 2 version id 0x40_00ea ?0x40_00ff 22 reserved 0x40_0100 ?0x40_013f 64 program once field refer to section 20.4.2.6, ?rogram once command 0x40_0140 ?0x40_01ff 192 reserved table 20-5. d-flash and memory controller resource fields global address size (bytes) description 0x10_0000 ?0x10_0fff 4,096 d-flash memory 0x10_1000 ?0x11_ffff 126,976 reserved 0x12_0000 ?0x12_007f 128 d-flash nonvolatile information register (dfifron 1 = 1) 1 mmcctl1 register bit 0x12_0080 ?0x12_0fff 3,968 reserved 0x12_1000 ?0x12_1fff 4,096 reserved 0x12_2000 ?0x12_3cff 7,242 reserved 0x12_3d00 ?0x12_3fff 768 memory controller scratch ram (mgramon 1 = 1) 0x12_4000 ?0x12_e7ff 43,008 reserved 0x12_e800 ?0x12_ffff 6,144 reserved 0x13_0000 ?0x13_ffff 65,536 reserved
64 kbyte flash module (s12xftmr64k1v1) s12xs family reference manual, rev. 1.10 freescale semiconductor 615 figure 20-3. d-flash and memory controller resource memory map 20.3.2 register descriptions the flash module contains a set of 20 control and status registers located between flash module base + 0x0000 and 0x0013. a summary of the flash module registers is given in figure 20-4 with detailed descriptions in the following subsections. caution writes to any flash register must be avoided while a flash command is active (ccif=0) to prevent corruption of flash register contents and memory controller behavior. address & name 76543210 0x0000 fclkdiv r fdivld fdiv6 fdiv5 fdiv4 fdiv3 fdiv2 fdiv1 fdiv0 w 0x0001 fsec r keyen1 keyen0 rnv5 rnv4 rnv3 rnv2 sec1 sec0 w figure 20-4. ftmr64k1 register summary 0x12_ffff 0x12_4000 0x12_1000 memory controller scratch ram (mgramon) 768 bytes d-flash nonvolatile information register (dfifron) 128 bytes d-flash memory 4 kbytes d-flash start = 0x10_0000 0x12_0000 0x12_2000 0x12_e800 d-flash end = 0x10_0fff
64 kbyte flash module (s12xftmr64k1v1) s12xs family reference manual, rev. 1.10 616 freescale semiconductor 0x0002 fccobix r0 0 0 0 0 ccobix2 ccobix1 ccobix0 w 0x0003 feccrix r0 0 0 0 0 eccrix2 eccrix1 eccrix0 w 0x0004 fcnfg r ccie 00 ignsf 00 fdfd fsfd w 0x0005 fercnfg r 0 dfdie sfdie w 0x0006 fstat r ccif 0 accerr fpviol mgbusy rsvd mgstat1 mgstat0 w 0x0007 ferstat r0 0 0 0 0 0 dfdif sfdif w 0x0008 fprot r fpopen rnv6 fphdis fphs1 fphs0 fpldis fpls1 fpls0 w 0x0009 dfprot r dpopen 00 dps4 dps3 dps2 dps1 dps0 w 0x000a fccobhi r ccob15 ccob14 ccob13 ccob12 ccob11 ccob10 ccob9 ccob8 w 0x000b fccoblo r ccob7 ccob6 ccob5 ccob4 ccob3 ccob2 ccob1 ccob0 w 0x000c frsv0 r00000000 w 0x000d frsv1 r00000000 w 0x000e feccrhi r eccr15 eccr14 eccr13 eccr12 eccr11 eccr10 eccr9 eccr8 w 0x000f feccrlo r eccr7 eccr6 eccr5 eccr4 eccr3 eccr2 eccr1 eccr0 w address & name 76543210 figure 20-4. ftmr64k1 register summary (continued)
64 kbyte flash module (s12xftmr64k1v1) s12xs family reference manual, rev. 1.10 freescale semiconductor 617 20.3.2.1 flash clock divider register (fclkdiv) the fclkdiv register is used to control timed events in program and erase algorithms. all bits in the fclkdiv register are readable, bits 6? are write once and bit 7 is not writable. 0x0010 fopt r nv7 nv6 nv5 nv4 nv3 nv2 nv1 nv0 w 0x0011 frsv2 r00000000 w 0x0012 frsv3 r00000000 w 0x0013 frsv4 r00000000 w = unimplemented or reserved offset module base + 0x0000 76543210 r fdivld fdiv[6:0] w reset 00000000 = unimplemented or reserved figure 20-5. flash clock divider register (fclkdiv) table 20-6. fclkdiv field descriptions field description 7 fdivld clock divider loaded 0 fclkdiv register has not been written 1 fclkdiv register has been written since the last reset 6? fdiv[6:0] clock divider bits ?fdiv[6:0] must be set to effectively divide oscclk down to generate an internal flash clock, fclk, with a target frequency of 1 mhz for use by the flash module to control timed events during program and erase algorithms. table 20-7 shows recommended values for fdiv[6:0] based on oscclk frequency. please refer to section 20.4.1, ?lash command operations , for more information. address & name 76543210 figure 20-4. ftmr64k1 register summary (continued)
64 kbyte flash module (s12xftmr64k1v1) s12xs family reference manual, rev. 1.10 618 freescale semiconductor caution the fclkdiv register should never be written while a flash command is executing (ccif=0). the fclkdiv register is writable during the flash reset sequence even though ccif is clear.
64 kbyte flash module (s12xftmr64k1v1) s12xs family reference manual, rev. 1.10 freescale semiconductor 619 table 20-7. fdiv vs oscclk frequency oscclk frequency (mhz) fdiv[6:0] oscclk frequency (mhz) fdiv[6:0] min 1 1 fdiv shown generates an fclk frequency of >0.8 mhz max 2 2 fdiv shown generates an fclk frequency of 1.05 mhz min 1 max 2 1.60 2.10 0x01 33.60 34.65 0x20 2.40 3.15 0x02 34.65 35.70 0x21 3.20 4.20 0x03 35.70 36.75 0x22 4.20 5.25 0x04 36.75 37.80 0x23 5.25 6.30 0x05 37.80 38.85 0x24 6.30 7.35 0x06 38.85 39.90 0x25 7.35 8.40 0x07 39.90 40.95 0x26 8.40 9.45 0x08 40.95 42.00 0x27 9.45 10.50 0x09 42.00 43.05 0x28 10.50 11.55 0x0a 43.05 44.10 0x29 11.55 12.60 0x0b 44.10 45.15 0x2a 12.60 13.65 0x0c 45.15 46.20 0x2b 13.65 14.70 0x0d 46.20 47.25 0x2c 14.70 15.75 0x0e 47.25 48.30 0x2d 15.75 16.80 0x0f 48.30 49.35 0x2e 16.80 17.85 0x10 49.35 50.40 0x2f 17.85 18.90 0x11 18.90 19.95 0x12 19.95 21.00 0x13 21.00 22.05 0x14 22.05 23.10 0x15 23.10 24.15 0x16 24.15 25.20 0x17 25.20 26.25 0x18 26.25 27.30 0x19 27.30 28.35 0x1a 28.35 29.40 0x1b 29.40 30.45 0x1c 30.45 31.50 0x1d 31.50 32.55 0x1e 32.55 33.60 0x1f
64 kbyte flash module (s12xftmr64k1v1) s12xs family reference manual, rev. 1.10 620 freescale semiconductor 20.3.2.2 flash security register (fsec) the fsec register holds all bits associated with the security of the mcu and flash module. all bits in the fsec register are readable but not writable. during the reset sequence, the fsec register is loaded with the contents of the flash security byte in the flash configuration field at global address 0x7f_ff0f located in p-flash memory (see table 20-3 ) as indicated by reset condition f in figure 20-6 . if a double bit fault is detected while reading the p-flash phrase containing the flash security byte during the reset sequence, all bits in the fsec register will be set to leave the flash module in a secured state with backdoor key access disabled. offset module base + 0x0001 76543210 r keyen[1:0] rnv[5:2] sec[1:0] w reset f f ffffff = unimplemented or reserved figure 20-6. flash security register (fsec) table 20-8. fsec field descriptions field description 7? keyen[1:0] backdoor key security enable bits the keyen[1:0] bits de?e the enabling of backdoor key access to the flash module as shown in table 20-9 . 5? rnv[5:2} reserved nonvolatile bits ?the rnv bits should remain in the erased state for future enhancements. 1? sec[1:0] flash security bits ?the sec[1:0] bits de?e the security state of the mcu as shown in table 20-10 . if the flash module is unsecured using backdoor key access, the sec bits are forced to 10. table 20-9. flash keyen states keyen[1:0] status of backdoor key access 00 disabled 01 disabled 1 1 preferred keyen state to disable backdoor key access. 10 enabled 11 disabled table 20-10. flash security states sec[1:0] status of security 00 secured 01 secured 1 10 unsecured 11 secured
64 kbyte flash module (s12xftmr64k1v1) s12xs family reference manual, rev. 1.10 freescale semiconductor 621 the security function in the flash module is described in section 20.5 . 20.3.2.3 flash ccob index register (fccobix) the fccobix register is used to index the fccob register for flash memory operations. ccobix bits are readable and writable while remaining bits read 0 and are not writable. 20.3.2.4 flash eccr index register (feccrix) the feccrix register is used to index the feccr register for ecc fault reporting. eccrix bits are readable and writable while remaining bits read 0 and are not writable. 1 preferred sec state to set mcu to secured state. offset module base + 0x0002 76543210 r00000 ccobix[2:0] w reset 00000000 = unimplemented or reserved figure 20-7. fccob index register (fccobix) table 20-11. fccobix field descriptions field description 2? ccobix[1:0] common command register index the ccobix bits are used to select which word of the fccob register array is being read or written to. see section 20.3.2.11, ?lash common command object register (fccob) , for more details. offset module base + 0x0003 76543210 r00000 eccrix[2:0] w reset 00000000 = unimplemented or reserved figure 20-8. feccr index register (feccrix) table 20-12. feccrix field descriptions field description 2-0 eccrix[2:0] ecc error register index ?the eccrix bits are used to select which word of the feccr register array is being read. see section 20.3.2.14, ?lash ecc error results register (feccr) , for more details.
64 kbyte flash module (s12xftmr64k1v1) s12xs family reference manual, rev. 1.10 622 freescale semiconductor 20.3.2.5 flash con?uration register (fcnfg) the fcnfg register enables the flash command complete interrupt and forces ecc faults on flash array read access from the cpu or xgate. ccie, ignsf, fdfd, and fsfd bits are readable and writable while remaining bits read 0 and are not writable. 20.3.2.6 flash error con?uration register (fercnfg) the fercnfg register enables the flash error interrupts for the ferstat flags. offset module base + 0x0004 76543210 r ccie 00 ignsf 00 fdfd fsfd w reset 00000000 = unimplemented or reserved figure 20-9. flash con?uration register (fcnfg) table 20-13. fcnfg field descriptions field description 7 ccie command complete interrupt enable ?the ccie bit controls interrupt generation when a flash command has completed. 0 command complete interrupt disabled 1 an interrupt will be requested whenever the ccif ?g in the fstat register is set (see section 20.3.2.7 ) 4 ignsf ignore single bit fault ?the ignsf controls single bit fault reporting in the ferstat register (see section 20.3.2.8 ). 0 all single bit faults detected during array reads are reported 1 single bit faults detected during array reads are not reported and the single bit fault interrupt will not be generated 1 fdfd force double bit fault detect the fdfd bit allows the user to simulate a double bit fault during flash array read operations and check the associated interrupt routine. the fdfd bit is cleared by writing a 0 to fdfd. the feccr registers will not be updated during the flash array read operation with fdfd set unless an actual double bit fault is detected. 0 flash array read operations will set the dfdif ?g in the ferstat register only if a double bit fault is detected 1 any flash array read operation will force the dfdif ?g in the ferstat register to be set (see section 20.3.2.7 ) and an interrupt will be generated as long as the dfdie interrupt enable in the fercnfg register is set (see section 20.3.2.6 ) 0 fsfd force single bit fault detect the fsfd bit allows the user to simulate a single bit fault during flash array read operations and check the associated interrupt routine. the fsfd bit is cleared by writing a 0 to fsfd. the feccr registers will not be updated during the flash array read operation with fsfd set unless an actual single bit fault is detected. 0 flash array read operations will set the sfdif ?g in the ferstat register only if a single bit fault is detected 1 flash array read operation will force the sfdif ?g in the ferstat register to be set (see section 20.3.2.7 ) and an interrupt will be generated as long as the sfdie interrupt enable in the fercnfg register is set (see section 20.3.2.6 )
64 kbyte flash module (s12xftmr64k1v1) s12xs family reference manual, rev. 1.10 freescale semiconductor 623 all assigned bits in the fercnfg register are readable and writable. 20.3.2.7 flash status register (fstat) the fstat register reports the operational status of the flash module. ccif, accerr, and fpviol bits are readable and writable, mgbusy and mgstat bits are readable but not writable, while remaining bits read 0 and are not writable. offset module base + 0x0005 76543210 r 0 dfdie sfdie w reset 00000000 = unimplemented or reserved figure 20-10. flash error con?uration register (fercnfg) table 20-14. fercnfg field descriptions field description 1 dfdie double bit fault detect interrupt enable the dfdie bit controls interrupt generation when a double bit fault is detected during a flash block read operation. 0 dfdif interrupt disabled 1 an interrupt will be requested whenever the dfdif ?g is set (see section 20.3.2.8 ) 0 sfdie single bit fault detect interrupt enable the sfdie bit controls interrupt generation when a single bit fault is detected during a flash block read operation. 0 sfdif interrupt disabled whenever the sfdif ?g is set (see section 20.3.2.8 ) 1 an interrupt will be requested whenever the sfdif ?g is set (see section 20.3.2.8 ) offset module base + 0x0006 76543210 r ccif 0 accerr fpviol mgbusy rsvd mgstat[1:0] w reset 1000000 1 1 reset value can deviate from the value shown if a double bit fault is detected during the reset sequence (see section 20.6 ). 0 1 = unimplemented or reserved figure 20-11. flash status register (fstat)
64 kbyte flash module (s12xftmr64k1v1) s12xs family reference manual, rev. 1.10 624 freescale semiconductor 20.3.2.8 flash error status register (ferstat) the ferstat register re?cts the error status of internal flash operations. all ?gs in the ferstat register are readable and only writable to clear the ?g. table 20-15. fstat field descriptions field description 7 ccif command complete interrupt flag ?the ccif ?g indicates that a flash command has completed. the ccif ?g is cleared by writing a 1 to ccif to launch a command and ccif will stay low until command completion or command violation. 0 flash command in progress 1 flash command has completed 5 accerr flash access error flag ?the accerr bit indicates an illegal access has occurred to the flash memory caused by either a violation of the command write sequence (see section 20.4.1.2 ) or issuing an illegal flash command. while accerr is set, the ccif ?g cannot be cleared to launch a command. the accerr bit is cleared by writing a 1 to accerr. writing a 0 to the accerr bit has no effect on accerr. 0 no access error detected 1 access error detected 4 fpviol flash protection violation flag ?he fpviol bit indicates an attempt was made to program or erase an address in a protected area of p-flash or d-flash memory during a command write sequence. the fpviol bit is cleared by writing a 1 to fpviol. writing a 0 to the fpviol bit has no effect on fpviol. while fpviol is set, it is not possible to launch a command or start a command write sequence. 0 no protection violation detected 1 protection violation detected 3 mgbusy memory controller busy flag ?the mgbusy ?g re?cts the active state of the memory controller . 0 memory controller is idle 1 memory controller is busy executing a flash command (ccif = 0) 2 rsvd reserved bit ?this bit is reserved and always reads 0 . 1? mgstat[1:0] memory controller command completion status flag one or more mgstat ?g bits are set if an error is detected during execution of a flash command or during the flash reset sequence. see section 20.4.2, ?lash command description , and section 20.6, ?nitialization ?for details. offset module base + 0x0007 76543210 r000000 dfdif sfdif w reset 00000000 = unimplemented or reserved figure 20-12. flash error status register (ferstat)
64 kbyte flash module (s12xftmr64k1v1) s12xs family reference manual, rev. 1.10 freescale semiconductor 625 20.3.2.9 p-flash protection register (fprot) the fprot register defines which p-flash sectors are protected against program and erase operations. the (unreserved) bits of the fprot register are writable with the restriction that the size of the protected region can only be increased (see section 20.3.2.9.1, ?-flash protection restrictions , and table 20-21 ). during the reset sequence, the fprot register is loaded with the contents of the p-flash protection byte in the flash configuration field at global address 0x7f_ff0c located in p-flash memory (see table 20-3 ) as indicated by reset condition ??in figure 20-13 . to change the p-flash protection that will be loaded during the reset sequence, the upper sector of the p-flash memory must be unprotected, then the p-flash protection byte must be reprogrammed. if a double bit fault is detected while reading the p-flash phrase containing the p-flash protection byte during the reset sequence, the fpopen bit will be cleared and remaining bits in the fprot register will be set to leave the p-flash memory fully protected. trying to alter data in any protected area in the p-flash memory will result in a protection violation error and the fpviol bit will be set in the fstat register. the block erase of a p-flash block is not possible if any of the p-flash sectors contained in the same p-flash block are protected. table 20-16. ferstat field descriptions field description 1 dfdif double bit fault detect interrupt flag ?the setting of the dfdif ?g indicates that a double bit fault was detected in the stored parity and data bits during a flash array read operation or that a flash array read operation was attempted on a flash block that was under a flash command operation. the dfdif ?g is cleared by writing a 1 to dfdif. writing a 0 to dfdif has no effect on dfdif. 0 no double bit fault detected 1 double bit fault detected or an invalid flash array read operation attempted 0 sfdif single bit fault detect interrupt flag ?with the ignsf bit in the fcnfg register clear, the sfdif ?g indicates that a single bit fault was detected in the stored parity and data bits during a flash array read operation or that a flash array read operation was attempted on a flash block that was under a flash command operation. the sfdif ?g is cleared by writing a 1 to sfdif. writing a 0 to sfdif has no effect on sfdif. 0 no single bit fault detected 1 single bit fault detected and corrected or an invalid flash array read operation attempted offset module base + 0x0008 76543210 r fpopen rnv6 fphdis fphs[1:0] fpldis fpls[1:0] w reset f f ffffff = unimplemented or reserved figure 20-13. flash protection register (fprot)
64 kbyte flash module (s12xftmr64k1v1) s12xs family reference manual, rev. 1.10 626 freescale semiconductor table 20-17. fprot field descriptions field description 7 fpopen flash protection operation enable ?the fpopen bit determines the protection function for program or erase operations as shown in table 20-18 for the p-flash block. 0 when fpopen is clear, the fphdis and fpldis bits de?e unprotected address ranges as speci?d by the corresponding fphs and fpls bits 1 when fpopen is set, the fphdis and fpldis bits enable protection for the address range speci?d by the corresponding fphs and fpls bits 6 rnv[6] reserved nonvolatile bit ?the rnv bit should remain in the erased state for future enhancements. 5 fphdis flash protection higher address range disable ?the fphdis bit determines whether there is a protected/unprotected area in a speci? region of the p-flash memory ending with global address 0x7f_ffff. 0 protection/unprotection enabled 1 protection/unprotection disabled 4? fphs[1:0] flash protection higher address size the fphs bits determine the size of the protected/unprotected area in p-flash memory as shown in table 20-19 . the fphs bits can only be written to while the fphdis bit is set. 2 fpldis flash protection lower address range disable ?the fpldis bit determines whether there is a protected/unprotected area in a speci? region of the p-flash memory beginning with global address 0x7f_8000. 0 protection/unprotection enabled 1 protection/unprotection disabled 1? fpls[1:0] flash protection lower address size the fpls bits determine the size of the protected/unprotected area in p-flash memory as shown in table 20-20 . the fpls bits can only be written to while the fpldis bit is set. table 20-18. p-flash protection function fpopen fphdis fpldis function 1 1 for range sizes, refer to table 20-19 and table 20-20 . 1 1 1 no p-flash protection 1 1 0 protected low range 1 0 1 protected high range 1 0 0 protected high and low ranges 0 1 1 full p-flash memory protected 0 1 0 unprotected low range 0 0 1 unprotected high range 0 0 0 unprotected high and low ranges table 20-19. p-flash protection higher address range fphs[1:0] global address range protected size 00 0x7f_f800?x7f_ffff 2 kbytes 01 0x7f_f000?x7f_ffff 4 kbytes 10 0x7f_e000?x7f_ffff 8 kbytes 11 0x7f_c000?x7f_ffff 16 kbytes
64 kbyte flash module (s12xftmr64k1v1) s12xs family reference manual, rev. 1.10 freescale semiconductor 627 all possible p-flash protection scenarios are shown in figure 20-14 . although the protection scheme is loaded from the flash memory at global address 0x7f_ff0c during the reset sequence, it can be changed by the user. the p-flash protection scheme can be used by applications requiring reprogramming in single chip mode while providing as much protection as possible if reprogramming is not required. table 20-20. p-flash protection lower address range fpls[1:0] global address range protected size 00 0x7f_8000?x7f_83ff 1 kbyte 01 0x7f_8000?x7f_87ff 2 kbytes 10 0x7f_8000?x7f_8fff 4 kbytes 11 0x7f_8000?x7f_9fff 8 kbytes
64 kbyte flash module (s12xftmr64k1v1) s12xs family reference manual, rev. 1.10 628 freescale semiconductor figure 20-14. p-flash protection scenarios 7 6 5 4 fphs[1:0] fpls[1:0] 3 2 1 0 fphs[1:0] fpls[1:0] fphdis = 1 fpldis = 1 fphdis = 1 fpldis = 0 fphdis = 0 fpldis = 1 fphdis = 0 fpldis = 0 scenario scenario unprotected region protected region with size protected region protected region with size defined by fpls defined by fphs not defined by fpls, fphs 0x7f_8000 0x7f_ffff 0x7f_8000 0x7f_ffff flash start flash start fpopen = 1 fpopen = 0
64 kbyte flash module (s12xftmr64k1v1) s12xs family reference manual, rev. 1.10 freescale semiconductor 629 20.3.2.9.1 p-flash protection restrictions the general guideline is that p-flash protection can only be added and not removed. table 20-21 specifies all valid transitions between p-flash protection scenarios. any attempt to write an invalid scenario to the fprot register will be ignored. the contents of the fprot register reflect the active protection scenario. see the fphs and fpls bit descriptions for additional restrictions. 20.3.2.10 d-flash protection register (dfprot) the dfprot register de?es which d-flash sectors are protected against program and erase operations. the (unreserved) bits of the dfprot register are writable with the restriction that protection can be added but not removed. writes must increase the dps value and the dpoen bit can only be written from 1 (protection disabled) to 0 (protection enabled). if the dpopen bit is set, the state of the dps bits is irrelevant. during the reset sequence, the dfprot register is loaded with the contents of the d-flash protection byte in the flash configuration field at global address 0x7f_ff0d located in p-flash memory (see table 20-3 ) as indicated by reset condition f in figure 20-15 . to change the d-flash protection that will be loaded during the reset sequence, the p-flash sector containing the d-flash protection byte must be unprotected, then the d-flash protection byte must be programmed. if a double bit fault is detected while reading the table 20-21. p-flash protection scenario transitions from protection scenario to protection scenario 1 1 allowed transitions marked with x, see figure 20-14 for a de?ition of the scenarios. 01234567 0 xxxx 1 xx 2 xx 3 x 4 xx 5 xxxx 6 xxxx 7 xxxxxxxx offset module base + 0x0009 76543210 r dpopen 00 dps[4:0] w reset f 0 0 fffff = unimplemented or reserved figure 20-15. d-flash protection register (dfprot)
64 kbyte flash module (s12xftmr64k1v1) s12xs family reference manual, rev. 1.10 630 freescale semiconductor p-flash phrase containing the d-flash protection byte during the reset sequence, the dpopen bit will be cleared and dps bits will be set to leave the d-flash memory fully protected. trying to alter data in any protected area in the d-flash memory will result in a protection violation error and the fpviol bit will be set in the fstat register. block erase of the d-flash memory is not possible if any of the d-flash sectors are protected. 20.3.2.11 flash common command object register (fccob) the fccob is an array of six words addressed via the ccobix index found in the fccobix register. byte wide reads and writes are allowed to the fccob register. table 20-22. dfprot field descriptions field description 7 dpopen d-flash protection control 0 enables d-flash memory protection from program and erase with protected address range de?ed by dps bits 1 disables d-flash memory protection from program and erase 4? dps[4:0] d-flash protection size the dps[4:0] bits determine the size of the protected area in the d-flash memory as shown in table 20-23 . table 20-23. d-flash protection address range dps[4:0] global address range protected size 0_0000 0x10_0000 ?0x10_00ff 256 bytes 0_0001 0x10_0000 ?0x10_01ff 512 bytes 0_0010 0x10_0000 ?0x10_02ff 768 bytes 0_0011 0x10_0000 ?0x10_03ff 1024 bytes 0_0100 0x10_0000 ?0x10_04ff 1280 bytes 0_0101 0x10_0000 ?0x10_05ff 1536 bytes 0_0110 0x10_0000 ?0x10_06ff 1792 bytes 0_0111 0x10_0000 ?0x10_07ff 2048 bytes 0_1000 0x10_0000 ?0x10_08ff 2304 bytes 0_1001 0x10_0000 ?0x10_09ff 2560 bytes 0_1010 0x10_0000 ?0x10_0aff 2816 bytes 0_1011 0x10_0000 ?0x10_0bff 3072 bytes 0_1100 0x10_0000 ?0x10_0cff 3328 bytes 0_1101 0x10_0000 ?0x10_0dff 3584 bytes 0_1110 0x10_0000 ?0x10_0eff 3840 bytes 0_1111 0x10_0000 ?0x10_0fff 4096 bytes
64 kbyte flash module (s12xftmr64k1v1) s12xs family reference manual, rev. 1.10 freescale semiconductor 631 20.3.2.11.1 fccob - nvm command mode nvm command mode uses the indexed fccob register to provide a command code and its relevant parameters to the memory controller. the user first sets up all required fccob fields and then initiates the command? execution by writing a 1 to the ccif bit in the fstat register (a 1 written by the user clears the ccif command completion flag to 0). when the user clears the ccif bit in the fstat register all fccob parameter fields are locked and cannot be changed by the user until the command completes (as evidenced by the memory controller returning ccif to 1). some commands return information to the fccob register array. the generic format for the fccob parameter fields in nvm command mode is shown in table 20-24 . the return values are available for reading after the ccif flag in the fstat register has been returned to 1 by the memory controller. writes to the unimplemented parameter fields (ccobix = 110 and ccobix = 111) are ignored with reads from these fields returning 0x0000. table 20-24 shows the generic flash command format. the high byte of the first word in the ccob array contains the command code, followed by the parameters for this specific flash command. for details on the fccob settings required by each command, see the flash command descriptions in section 20.4.2 . offset module base + 0x000a 76543210 r ccob[15:8] w reset 00000000 figure 20-16. flash common command object high register (fccobhi) offset module base + 0x000b 76543210 r ccob[7:0] w reset 00000000 figure 20-17. flash common command object low register (fccoblo) table 20-24. fccob - nvm command mode (typical usage) ccobix[2:0] byte fccob parameter fields (nvm command mode) 000 hi fcmd[7:0] de?ing flash command lo 0, global address [22:16] 001 hi global address [15:8] lo global address [7:0] 010 hi data 0 [15:8] lo data 0 [7:0]
64 kbyte flash module (s12xftmr64k1v1) s12xs family reference manual, rev. 1.10 632 freescale semiconductor 20.3.2.12 flash reserved0 register (frsv0) this flash register is reserved for factory testing. all bits in the frsv0 register read 0 and are not writable. 20.3.2.13 flash reserved1 register (frsv1) this flash register is reserved for factory testing. all bits in the frsv1 register read 0 and are not writable. 20.3.2.14 flash ecc error results register (feccr) the feccr registers contain the result of a detected ecc fault for both single bit and double bit faults. the feccr register provides access to several ecc related fields as defined by the eccrix index bits in the feccrix register (see section 20.3.2.4 ). once ecc fault information has been stored, no other 011 hi data 1 [15:8] lo data 1 [7:0] 100 hi data 2 [15:8] lo data 2 [7:0] 101 hi data 3 [15:8] lo data 3 [7:0] offset module base + 0x000c 76543210 r00000000 w reset 00000000 = unimplemented or reserved figure 20-18. flash reserved0 register (frsv0) offset module base + 0x000d 76543210 r00000000 w reset 00000000 = unimplemented or reserved figure 20-19. flash reserved1 register (frsv1) table 20-24. fccob - nvm command mode (typical usage) ccobix[2:0] byte fccob parameter fields (nvm command mode)
64 kbyte flash module (s12xftmr64k1v1) s12xs family reference manual, rev. 1.10 freescale semiconductor 633 fault information will be recorded until the specific ecc fault flag has been cleared. in the event of simultaneous ecc faults the priority for fault recording is double bit fault over single bit fault. all feccr bits are readable but not writable. offset module base + 0x000e 76543210 r eccr[15:8] w reset 00000000 = unimplemented or reserved figure 20-20. flash ecc error results high register (feccrhi) offset module base + 0x000f 76543210 r eccr[7:0] w reset 00000000 = unimplemented or reserved figure 20-21. flash ecc error results low register (feccrlo) table 20-25. feccr index settings eccrix[2:0] feccr register content bits [15:8] bit[7] bits[6:0] 000 parity bits read from flash block 0 global address [22:16] 001 global address [15:0] 010 data 0 [15:0] 011 data 1 [15:0] (p-flash only) 100 data 2 [15:0] (p-flash only) 101 data 3 [15:0] (p-flash only) 110 not used, returns 0x0000 when read 111 not used, returns 0x0000 when read table 20-26. feccr index=000 bit descriptions field description 15:8 par[7:0] ecc parity bits ?contains the 8 parity bits from the 72 bit wide p-flash data word or the 6 parity bits, allocated to par[5:0], from the 22 bit wide d-flash word with par[7:6]=00. 6? gaddr[22:16] global address ?the gaddr[22:16] ?ld contains the upper seven bits of the global address having caused the error.
64 kbyte flash module (s12xftmr64k1v1) s12xs family reference manual, rev. 1.10 634 freescale semiconductor the p-flash word addressed by eccrix = 001 contains the lower 16 bits of the global address. the following four words addressed by eccrix = 010 to 101 contain the 64-bit wide data phrase. the four data words and the parity byte are the uncorrected data read from the p-flash block. the d-flash word addressed by eccrix = 001 contains the lower 16 bits of the global address. the uncorrected 16-bit data word is addressed by eccrix = 010. 20.3.2.15 flash option register (fopt) the fopt register is the flash option register. all bits in the fopt register are readable but are not writable. during the reset sequence, the fopt register is loaded from the flash nonvolatile byte in the flash configuration field at global address 0x7f_ff0e located in p-flash memory (see table 20-3 ) as indicated by reset condition f in figure 20-22 . if a double bit fault is detected while reading the p-flash phrase containing the flash nonvolatile byte during the reset sequence, all bits in the fopt register will be set. 20.3.2.16 flash reserved2 register (frsv2) this flash register is reserved for factory testing. all bits in the frsv2 register read 0 and are not writable. offset module base + 0x0010 76543210 r nv[7:0] w reset f f ffffff = unimplemented or reserved figure 20-22. flash option register (fopt) table 20-27. fopt field descriptions field description 7? nv[7:0] nonvolatile bits the nv[7:0] bits are available as nonvolatile bits. refer to the device user guide for proper use of the nv bits. offset module base + 0x0011 76543210 r00000000 w reset 00000000 = unimplemented or reserved figure 20-23. flash reserved2 register (frsv2)
64 kbyte flash module (s12xftmr64k1v1) s12xs family reference manual, rev. 1.10 freescale semiconductor 635 20.3.2.17 flash reserved3 register (frsv3) this flash register is reserved for factory testing. all bits in the frsv3 register read 0 and are not writable. 20.3.2.18 flash reserved4 register (frsv4) this flash register is reserved for factory testing. all bits in the frsv4 register read 0 and are not writable. 20.4 functional description 20.4.1 flash command operations flash command operations are used to modify flash memory contents. the next sections describe: how to write the fclkdiv register that is used to generate a time base (fclk) derived from oscclk for flash program and erase command operations the command write sequence used to set flash command parameters and launch execution valid flash commands available for execution offset module base + 0x0012 76543210 r00000000 w reset 00000000 = unimplemented or reserved figure 20-24. flash reserved3 register (frsv3) offset module base + 0x0013 76543210 r00000000 w reset 00000000 = unimplemented or reserved figure 20-25. flash reserved4 register (frsv4)
64 kbyte flash module (s12xftmr64k1v1) s12xs family reference manual, rev. 1.10 636 freescale semiconductor 20.4.1.1 writing the fclkdiv register prior to issuing any flash program or erase command after a reset, the user is required to write the fclkdiv register to divide oscclk down to a target fclk of 1 mhz. table 20-7 shows recommended values for the fdiv ?ld based on oscclk frequency. note programming or erasing the flash memory cannot be performed if the bus clock runs at less than 1 mhz. setting fdiv too high can destroy the flash memory due to overstress. setting fdiv too low can result in incomplete programming or erasure of the flash memory cells. when the fclkdiv register is written, the fdivld bit is set automatically. if the fdivld bit is 0, the fclkdiv register has not been written since the last reset. if the fclkdiv register has not been written, any flash program or erase command loaded during a command write sequence will not execute and the accerr bit in the fstat register will set. 20.4.1.2 command write sequence the memory controller will launch all valid flash commands entered using a command write sequence. before launching a command, the accerr and fpviol bits in the fstat register must be clear (see section 20.3.2.7 ) and the ccif flag should be tested to determine the status of the current command write sequence. if ccif is 0, the previous command write sequence is still active, a new command write sequence cannot be started, and all writes to the fccob register are ignored. caution writes to any flash register must be avoided while a flash command is active (ccif=0) to prevent corruption of flash register contents and memory controller behavior. 20.4.1.2.1 de?e fccob contents the fccob parameter ?lds must be loaded with all required parameters for the flash command being executed. access to the fccob parameter ?lds is controlled via the ccobix bits in the fccobix register (see section 20.3.2.3 ). the contents of the fccob parameter ?lds are transferred to the memory controller when the user clears the ccif command completion ?g in the fstat register (writing 1 clears the ccif to 0). the ccif ?g will remain clear until the flash command has completed. upon completion, the memory controller will return ccif to 1 and the fccob register will be used to communicate any results. the ?w for a generic command write sequence is shown in figure 20-26 .
64 kbyte flash module (s12xftmr64k1v1) s12xs family reference manual, rev. 1.10 freescale semiconductor 637 figure 20-26. generic flash command write sequence flowchart write to fccobix register write: fstat register (to launch command) clear ccif 0x80 clear accerr/fpviol 0x30 write: fstat register yes no access error and protection violation read: fstat register read: fstat register no start yes check ccif set? fccob accerr/ fpviol set? exit write: fclkdiv register read: fclkdiv register yes no clock register written check fdivld set? no bit polling for command completion check yes ccif set? to identify speci? command parameter to load. write to fccob register to load required command parameter. yes no more parameters? availability check results from previous command note: fclkdiv must be set after each reset
64 kbyte flash module (s12xftmr64k1v1) s12xs family reference manual, rev. 1.10 638 freescale semiconductor 20.4.1.3 valid flash module commands 20.4.1.4 p-flash commands table 20-29 summarizes the valid p-flash commands along with the effects of the commands on the p-flash block and other resources within the flash module. table 20-28. flash commands by mode fcmd command unsecured secured ns 1 1 unsecured normal single chip mode. nx 2 2 unsecured normal expanded mode. ss 3 3 unsecured special single chip mode. st 4 4 unsecured special mode. ns 5 5 secured normal single chip mode. nx 6 6 secured normal expanded mode. ss 7 7 secured special single chip mode. st 8 8 secured special mode. 0x01 erase verify all blocks ???????? 0x02 erase verify block ???????? 0x03 erase verify p-flash section ????? 0x04 read once ????? 0x06 program p-flash ????? 0x07 program once ????? 0x08 erase all blocks ?? ?? 0x09 erase flash block ????? 0x0a erase p-flash sector ????? 0x0b unsecure flash ?? ?? 0x0c verify backdoor access key ?? 0x0d set user margin level ????? 0x0e set field margin level ?? 0x10 erase verify d-flash section ????? 0x11 program d-flash ????? 0x12 erase d-flash sector ?????
64 kbyte flash module (s12xftmr64k1v1) s12xs family reference manual, rev. 1.10 freescale semiconductor 639 20.4.1.5 d-flash commands table 20-30 summarizes the valid d-flash commands along with the effects of the commands on the d-flash block. table 20-29. p-flash commands fcmd command function on p-flash memory 0x01 erase verify all blocks verify that all p-flash (and d-flash) blocks are erased. 0x02 erase verify block verify that a p-flash block is erased. 0x03 erase verify p-flash section verify that a given number of words starting at the address provided are erased. 0x04 read once read a dedicated 64 byte ?ld in the nonvolatile information register in p-flash block 0 that was previously programmed using the program once command. 0x06 program p-flash program a phrase in a p-flash block. 0x07 program once program a dedicated 64 byte ?ld in the nonvolatile information register in p-flash block 0 that is allowed to be programmed only once. 0x08 erase all blocks erase all p-flash (and d-flash) blocks. an erase of all flash blocks is only possible when the fpldis, fphdis, and fpopen bits in the fprot register and the dpopen bit in the dfprot register are set prior to launching the command. 0x09 erase flash block erase a p-flash (or d-flash) block. an erase of the full p-flash block is only possible when fpldis, fphdis and fpopen bits in the fprot register are set prior to launching the command. 0x0a erase p-flash sector erase all bytes in a p-flash sector. 0x0b unsecure flash supports a method of releasing mcu security by erasing all p-flash (and d-flash) blocks and verifying that all p-flash (and d-flash) blocks are erased. 0x0c verify backdoor access key supports a method of releasing mcu security by verifying a set of security keys. 0x0d set user margin level speci?s a user margin read level for all p-flash blocks. 0x0e set field margin level speci?s a ?ld margin read level for all p-flash blocks (special modes only). table 20-30. d-flash commands fcmd command function on d-flash memory 0x01 erase verify all blocks verify that all d-flash (and p-flash) blocks are erased. 0x02 erase verify block verify that the d-flash block is erased. 0x08 erase all blocks erase all d-flash (and p-flash) blocks. an erase of all flash blocks is only possible when the fpldis, fphdis, and fpopen bits in the fprot register and the dpopen bit in the dfprot register are set prior to launching the command. 0x09 erase flash block erase a d-flash (or p-flash) block. an erase of the full d-flash block is only possible when dpopen bit in the dfprot register is set prior to launching the command.
64 kbyte flash module (s12xftmr64k1v1) s12xs family reference manual, rev. 1.10 640 freescale semiconductor 20.4.2 flash command description this section provides details of all available flash commands launched by a command write sequence. the accerr bit in the fstat register will be set during the command write sequence if any of the following illegal steps are performed, causing the command not to be processed by the memory controller: starting any command write sequence that programs or erases flash memory before initializing the fclkdiv register writing an invalid command as part of the command write sequence for additional possible errors, refer to the error handling table provided for each command if a flash block is read during execution of an algorithm (ccif = 0) on that same block, the read operation will return invalid data. if the sfdif or dfdif flags were not previously set when the invalid read operation occurred, both the sfdif and dfdif flags will be set and the feccr registers will be loaded with the global address used in the invalid read operation with the data and parity fields set to all 0. if the accerr or fpviol bits are set in the fstat register, the user must clear these bits before starting any command write sequence (see section 20.3.2.7 ). caution a flash word or phrase must be in the erased state before being programmed. cumulative programming of bits within a flash word or phrase is not allowed. 20.4.2.1 erase verify all blocks command the erase verify all blocks command will verify that all p-flash and d-flash blocks have been erased. 0x0b unsecure flash supports a method of releasing mcu security by erasing all d-flash (and p-flash) blocks and verifying that all d-flash (and p-flash) blocks are erased. 0x0d set user margin level speci?s a user margin read level for the d-flash block. 0x0e set field margin level speci?s a ?ld margin read level for the d-flash block (special modes only). 0x10 erase verify d-flash section verify that a given number of words starting at the address provided are erased. 0x11 program d-flash program up to four words in the d-flash block. 0x12 erase d-flash sector erase all bytes in a sector of the d-flash block. table 20-31. erase verify all blocks command fccob requirements ccobix[2:0] fccob parameters 000 0x01 not required table 20-30. d-flash commands fcmd command function on d-flash memory
64 kbyte flash module (s12xftmr64k1v1) s12xs family reference manual, rev. 1.10 freescale semiconductor 641 upon clearing ccif to launch the erase verify all blocks command, the memory controller will verify that the entire flash memory space is erased. the ccif ?g will set after the erase verify all blocks operation has completed. 20.4.2.2 erase verify block command the erase verify block command allows the user to verify that an entire p-flash or d-flash block has been erased. the fccob upper global address bits determine which block must be veri?d. upon clearing ccif to launch the erase verify block command, the memory controller will verify that the selected p-flash or d-flash block is erased. the ccif ?g will set after the erase verify block operation has completed. 20.4.2.3 erase verify p-flash section command the erase verify p-flash section command will verify that a section of code in the p-flash memory is erased. the erase verify p-flash section command defines the starting point of the code to be verified and the number of phrases. the section to be verified cannot cross a 128 kbyte boundary in the p-flash memory space. table 20-32. erase verify all blocks command error handling register error bit error condition fstat accerr set if ccobix[2:0] != 000 at command launch fpviol none mgstat1 set if any errors have been encountered during the read 1 1 as found in the memory map for ftmr128k1. mgstat0 set if any non-correctable errors have been encountered during the read 1 table 20-33. erase verify block command fccob requirements ccobix[2:0] fccob parameters 000 0x02 global address [22:16] of the flash block to be veri?d . table 20-34. erase verify block command error handling register error bit error condition fstat accerr set if ccobix[2:0] != 000 at command launch set if an invalid global address [22:16] is supplied 1 1 as de?ed by the memory map for ftmr128k1. fpviol none mgstat1 set if any errors have been encountered during the read 2 2 as found in the memory map for ftmr128k1. mgstat0 set if any non-correctable errors have been encountered during the read 2
64 kbyte flash module (s12xftmr64k1v1) s12xs family reference manual, rev. 1.10 642 freescale semiconductor upon clearing ccif to launch the erase verify p-flash section command, the memory controller will verify the selected section of flash memory is erased. the ccif ?g will set after the erase verify p-flash section operation has completed. 20.4.2.4 read once command the read once command provides read access to a reserved 64 byte field (8 phrases) located in the nonvolatile information register of p-flash block 0. the read once field is programmed using the program once command described in section 20.4.2.6 . the read once command must not be executed from the flash block containing the program once reserved field to avoid code runaway. table 20-35. erase verify p-flash section command fccob requirements ccobix[2:0] fccob parameters 000 0x03 global address [22:16] of a p-flash block 001 global address [15:0] of the ?st phrase to be veri?d 010 number of phrases to be veri?d table 20-36. erase verify p-flash section command error handling register error bit error condition fstat accerr set if ccobix[2:0] != 010 at command launch set if command not available in current mode (see table 20-28 ) set if an invalid global address [22:0] is supplied 1 1 as de?ed by the memory map for ftmr128k1. set if a misaligned phrase address is supplied (global address [2:0] != 000) set if the requested section crosses a 128 kbyte boundary fpviol none mgstat1 set if any errors have been encountered during the read 2 2 as found in the memory map for ftmr128k1. mgstat0 set if any non-correctable errors have been encountered during the read 2 table 20-37. read once command fccob requirements ccobix[2:0] fccob parameters 000 0x04 not required 001 read once phrase index (0x0000 - 0x0007) 010 read once word 0 value 011 read once word 1 value 100 read once word 2 value 101 read once word 3 value
64 kbyte flash module (s12xftmr64k1v1) s12xs family reference manual, rev. 1.10 freescale semiconductor 643 upon clearing ccif to launch the read once command, a read once phrase is fetched and stored in the fccob indexed register. the ccif ?g will set after the read once operation has completed. valid phrase index values for the read once command range from 0x0000 to 0x0007. during execution of the read once command, any attempt to read addresses within p-flash block will return invalid data. 20.4.2.5 program p-flash command the program p-flash operation will program a previously erased phrase in the p-flash memory using an embedded algorithm. caution a p-flash phrase must be in the erased state before being programmed. cumulative programming of bits within a flash phrase is not allowed. upon clearing ccif to launch the program p-flash command, the memory controller will program the data words to the supplied global address and will then proceed to verify the data words read back as expected. the ccif ?g will set after the program p-flash operation has completed. table 20-38. read once command error handling register error bit error condition fstat accerr set if ccobix[2:0] != 001 at command launch set if command not available in current mode (see table 20-28 ) set if an invalid phrase index is supplied fpviol none mgstat1 set if any errors have been encountered during the read mgstat0 set if any non-correctable errors have been encountered during the read table 20-39. program p-flash command fccob requirements ccobix[2:0] fccob parameters 000 0x06 global address [22:16] to identify p-flash block 001 global address [15:0] of phrase location to be programmed 1 1 global address [2:0] must be 000 010 word 0 program value 011 word 1 program value 100 word 2 program value 101 word 3 program value
64 kbyte flash module (s12xftmr64k1v1) s12xs family reference manual, rev. 1.10 644 freescale semiconductor 20.4.2.6 program once command the program once command restricts programming to a reserved 64 byte field (8 phrases) in the nonvolatile information register located in p-flash block 0. the program once reserved field can be read using the read once command as described in section 20.4.2.4 . the program once command must only be issued once since the nonvolatile information register in p-flash block 0 cannot be erased. the program once command must not be executed from the flash block containing the program once reserved field to avoid code runaway. upon clearing ccif to launch the program once command, the memory controller ?st veri?s that the selected phrase is erased. if erased, then the selected phrase will be programmed and then veri?d with read back. the ccif ?g will remain clear, setting only after the program once operation has completed. the reserved nonvolatile information register accessed by the program once command cannot be erased and any attempt to program one of these phrases a second time will not be allowed. valid phrase index values for the program once command range from 0x0000 to 0x0007. during execution of the program once command, any attempt to read addresses within p-flash block 0 will return invalid data. table 20-40. program p-flash command error handling register error bit error condition fstat accerr set if ccobix[2:0] != 101 at command launch set if command not available in current mode (see table 20-28 ) set if an invalid global address [22:0] is supplied 1 1 as de?ed by the memory map for ftmr128k1. set if a misaligned phrase address is supplied (global address [2:0] != 000) fpviol set if the global address [22:0] points to a protected area mgstat1 set if any errors have been encountered during the verify operation mgstat0 set if any non-correctable errors have been encountered during the verify operation table 20-41. program once command fccob requirements ccobix[2:0] fccob parameters 000 0x07 not required 001 program once phrase index (0x0000 - 0x0007) 010 program once word 0 value 011 program once word 1 value 100 program once word 2 value 101 program once word 3 value
64 kbyte flash module (s12xftmr64k1v1) s12xs family reference manual, rev. 1.10 freescale semiconductor 645 r, 20.4.2.7 erase all blocks command the erase all blocks operation will erase the entire p-flash and d-flash memory space. upon clearing ccif to launch the erase all blocks command, the memory controller will erase the entire flash memory space and verify that it is erased. if the memory controller veri?s that the entire flash memory space was properly erased, security will be released. during the execution of this command (ccif=0) the user must not write to any flash module register. the ccif ?g will set after the erase all blocks operation has completed. 20.4.2.8 erase flash block command the erase flash block operation will erase all addresses in a p-flash or d-flash block. table 20-42. program once command error handling register error bit error condition fstat accerr set if ccobix[2:0] != 101 at command launch set if command not available in current mode (see table 20-28 ) set if an invalid phrase index is supplied set if the requested phrase has already been programmed 1 1 if a program once phrase is initially programmed to 0xffff_ffff_ffff_ffff, the program once command will be allowed to execute again on that same phrase. fpviol none mgstat1 set if any errors have been encountered during the verify operation mgstat0 set if any non-correctable errors have been encountered during the verify operation table 20-43. erase all blocks command fccob requirements ccobix[2:0] fccob parameters 000 0x08 not required table 20-44. erase all blocks command error handling register error bit error condition fstat accerr set if ccobix[2:0] != 000 at command launch set if command not available in current mode (see table 20-28 ) fpviol set if any area of the p-flash or d-flash memory is protected mgstat1 set if any errors have been encountered during the verify operation 1 1 as found in the memory map for ftmr128k1. mgstat0 set if any non-correctable errors have been encountered during the verify operation 1
64 kbyte flash module (s12xftmr64k1v1) s12xs family reference manual, rev. 1.10 646 freescale semiconductor upon clearing ccif to launch the erase flash block command, the memory controller will erase the selected flash block and verify that it is erased. the ccif ?g will set after the erase flash block operation has completed. 20.4.2.9 erase p-flash sector command the erase p-flash sector operation will erase all addresses in a p-flash sector. upon clearing ccif to launch the erase p-flash sector command, the memory controller will erase the selected flash sector and then verify that it is erased. the ccif ?g will be set after the erase p-flash sector operation has completed. table 20-45. erase flash block command fccob requirements ccobix[2:0] fccob parameters 000 0x09 global address [22:16] to identify flash block 001 global address [15:0] in flash block to be erased table 20-46. erase flash block command error handling register error bit error condition fstat accerr set if ccobix[2:0] != 001 at command launch set if command not available in current mode (see table 20-28 ) set if an invalid global address [22:16] is supplied 1 1 as de?ed by the memory map for ftmr128k1. set if the supplied p-flash address is not phrase-aligned or if the d-flash address is not word-aligned fpviol set if an area of the selected flash block is protected mgstat1 set if any errors have been encountered during the verify operation 2 2 as found in the memory map for ftmr128k1. mgstat0 set if any non-correctable errors have been encountered during the verify operation 2 table 20-47. erase p-flash sector command fccob requirements ccobix[2:0] fccob parameters 000 0x0a global address [22:16] to identify p-flash block to be erased 001 global address [15:0] anywhere within the sector to be erased. refer to section 20.1.2.1 for the p-flash sector size.
64 kbyte flash module (s12xftmr64k1v1) s12xs family reference manual, rev. 1.10 freescale semiconductor 647 20.4.2.10 unsecure flash command the unsecure flash command will erase the entire p-flash and d-flash memory space and, if the erase is successful, will release security. upon clearing ccif to launch the unsecure flash command, the memory controller will erase the entire p-flash and d-flash memory space and verify that it is erased. if the memory controller veri?s that the entire flash memory space was properly erased, security will be released. if the erase verify is not successful, the unsecure flash operation sets mgstat1 and terminates without changing the security state. during the execution of this command (ccif=0) the user must not write to any flash module register. the ccif ?g is set after the unsecure flash operation has completed. table 20-48. erase p-flash sector command error handling register error bit error condition fstat accerr set if ccobix[2:0] != 001 at command launch set if command not available in current mode (see table 20-28 ) set if an invalid global address [22:16] is supplied 1 1 as de?ed by the memory map for ftmr128k1. set if a misaligned phrase address is supplied (global address [2:0] != 000) fpviol set if the selected p-flash sector is protected mgstat1 set if any errors have been encountered during the verify operation mgstat0 set if any non-correctable errors have been encountered during the verify operation table 20-49. unsecure flash command fccob requirements ccobix[2:0] fccob parameters 000 0x0b not required table 20-50. unsecure flash command error handling register error bit error condition fstat accerr set if ccobix[2:0] != 000 at command launch set if command not available in current mode (see table 20-28 ) fpviol set if any area of the p-flash or d-flash memory is protected mgstat1 set if any errors have been encountered during the verify operation 1 1 as found in the memory map for ftmr128k1. mgstat0 set if any non-correctable errors have been encountered during the verify operation 1
64 kbyte flash module (s12xftmr64k1v1) s12xs family reference manual, rev. 1.10 648 freescale semiconductor 20.4.2.11 verify backdoor access key command the verify backdoor access key command will only execute if it is enabled by the keyen bits in the fsec register (see table 20-9 ). the verify backdoor access key command releases security if user-supplied keys match those stored in the flash security bytes of the flash configuration field (see table 20-3 ). the verify backdoor access key command must not be executed from the flash block containing the backdoor comparison key to avoid code runaway. upon clearing ccif to launch the verify backdoor access key command, the memory controller will check the fsec keyen bits to verify that this command is enabled. if not enabled, the memory controller sets the accerr bit in the fstat register and terminates. if the command is enabled, the memory controller compares the key provided in fccob to the backdoor comparison key in the flash con?uration ?ld with key 0 compared to 0x7f_ff00, etc. if the backdoor keys match, security will be released. if the backdoor keys do not match, security is not released and all future attempts to execute the verify backdoor access key command are aborted (set accerr) until a reset occurs. the ccif flag is set after the verify backdoor access key operation has completed. 20.4.2.12 set user margin level command the set user margin level command causes the memory controller to set the margin level for future read operations of a specific p-flash or d-flash block. table 20-51. verify backdoor access key command fccob requirements ccobix[2:0] fccob parameters 000 0x0c not required 001 key 0 010 key 1 011 key 2 100 key 3 table 20-52. verify backdoor access key command error handling register error bit error condition fstat accerr set if ccobix[2:0] != 100 at command launch set if an incorrect backdoor key is supplied set if backdoor key access has not been enabled (keyen[1:0] != 10, see section 20.3.2.2 ) set if the backdoor key has mismatched since the last reset fpviol none mgstat1 none mgstat0 none
64 kbyte flash module (s12xftmr64k1v1) s12xs family reference manual, rev. 1.10 freescale semiconductor 649 upon clearing ccif to launch the set user margin level command, the memory controller will set the user margin level for the targeted block and then set the ccif ?g. valid margin level settings for the set user margin level command are de?ed in table 20-54 . note user margin levels can be used to check that flash memory contents have adequate margin for normal level read operations. if unexpected results are encountered when checking flash memory contents at user margin levels, a potential loss of information has been detected. table 20-53. set user margin level command fccob requirements ccobix[2:0] fccob parameters 000 0x0d global address [22:16] to identify the flash block 001 margin level setting table 20-54. valid set user margin level settings ccob (ccobix=001) level description 0x0000 return to normal level 0x0001 user margin-1 level 1 1 read margin to the erased state 0x0002 user margin-0 level 2 2 read margin to the programmed state table 20-55. set user margin level command error handling register error bit error condition fstat accerr set if ccobix[2:0] != 001 at command launch set if command not available in current mode (see table 20-28 ) set if an invalid global address [22:16] is supplied 1 1 as de?ed by the memory map for ftmr128k1. set if an invalid margin level setting is supplied fpviol none mgstat1 none mgstat0 none
64 kbyte flash module (s12xftmr64k1v1) s12xs family reference manual, rev. 1.10 650 freescale semiconductor 20.4.2.13 set field margin level command the set field margin level command, valid in special modes only, causes the memory controller to set the margin level specified for future read operations of a specific p-flash or d-flash block. upon clearing ccif to launch the set field margin level command, the memory controller will set the ?ld margin level for the targeted block and then set the ccif ?g. valid margin level settings for the set field margin level command are de?ed in table 20-57 . caution field margin levels must only be used during verify of the initial factory programming. table 20-56. set field margin level command fccob requirements ccobix[2:0] fccob parameters 000 0x0e global address [22:16] to identify the flash block 001 margin level setting table 20-57. valid set field margin level settings ccob (ccobix=001) level description 0x0000 return to normal level 0x0001 user margin-1 level 1 1 read margin to the erased state 0x0002 user margin-0 level 2 2 read margin to the programmed state 0x0003 field margin-1 level 1 0x0004 field margin-0 level 2 table 20-58. set field margin level command error handling register error bit error condition fstat accerr set if ccobix[2:0] != 001 at command launch set if command not available in current mode (see table 20-28 ) set if an invalid global address [22:16] is supplied 1 1 as de?ed by the memory map for ftmr128k1. set if an invalid margin level setting is supplied fpviol none mgstat1 none mgstat0 none
64 kbyte flash module (s12xftmr64k1v1) s12xs family reference manual, rev. 1.10 freescale semiconductor 651 note field margin levels can be used to check that flash memory contents have adequate margin for data retention at the normal level setting. if unexpected results are encountered when checking flash memory contents at ?ld margin levels, the flash memory contents should be erased and reprogrammed. 20.4.2.14 erase verify d-flash section command the erase verify d-flash section command will verify that a section of code in the d-flash is erased. the erase verify d-flash section command defines the starting point of the data to be verified and the number of words. upon clearing ccif to launch the erase verify d-flash section command, the memory controller will verify the selected section of d-flash memory is erased. the ccif ?g will set after the erase verify d-flash section operation has completed. 20.4.2.15 program d-flash command the program d-flash operation programs one to four previously erased words in the d-flash block. the program d-flash operation will confirm that the targeted location(s) were successfully programmed upon completion. table 20-59. erase verify d-flash section command fccob requirements ccobix[2:0] fccob parameters 000 0x10 global address [22:16] to identify the d-flash block 001 global address [15:0] of the ?st word to be veri?d 010 number of words to be veri?d table 20-60. erase verify d-flash section command error handling register error bit error condition fstat accerr set if ccobix[2:0] != 010 at command launch set if command not available in current mode (see table 20-28 ) set if an invalid global address [22:0] is supplied set if a misaligned word address is supplied (global address [0] != 0) set if the requested section breaches the end of the d-flash block fpviol none mgstat1 set if any errors have been encountered during the read mgstat0 set if any non-correctable errors have been encountered during the read
64 kbyte flash module (s12xftmr64k1v1) s12xs family reference manual, rev. 1.10 652 freescale semiconductor caution a flash word must be in the erased state before being programmed. cumulative programming of bits within a flash word is not allowed. upon clearing ccif to launch the program d-flash command, the user-supplied words will be transferred to the memory controller and be programmed if the area is unprotected. the ccobix index value at program d-flash command launch determines how many words will be programmed in the d-flash block. the ccif ?g is set when the operation has completed. 20.4.2.16 erase d-flash sector command the erase d-flash sector operation will erase all addresses in a sector of the d-flash block. table 20-61. program d-flash command fccob requirements ccobix[2:0] fccob parameters 000 0x11 global address [22:16] to identify the d-flash block 001 global address [15:0] of word to be programmed 010 word 0 program value 011 word 1 program value, if desired 100 word 2 program value, if desired 101 word 3 program value, if desired table 20-62. program d-flash command error handling register error bit error condition fstat accerr set if ccobix[2:0] < 010 at command launch set if ccobix[2:0] > 101 at command launch set if command not available in current mode (see table 20-28 ) set if an invalid global address [22:0] is supplied set if a misaligned word address is supplied (global address [0] != 0) set if the requested group of words breaches the end of the d-flash block fpviol set if the selected area of the d-flash memory is protected mgstat1 set if any errors have been encountered during the verify operation mgstat0 set if any non-correctable errors have been encountered during the verify operation table 20-63. erase d-flash sector command fccob requirements ccobix[2:0] fccob parameters 000 0x12 global address [22:16] to identify d-flash block
64 kbyte flash module (s12xftmr64k1v1) s12xs family reference manual, rev. 1.10 freescale semiconductor 653 upon clearing ccif to launch the erase d-flash sector command, the memory controller will erase the selected flash sector and verify that it is erased. the ccif ?g will set after the erase d-flash sector operation has completed. 20.4.3 interrupts the flash module can generate an interrupt when a flash command operation has completed or when a flash command operation has detected an ecc fault. note vector addresses and their relative interrupt priority are determined at the mcu level. 20.4.3.1 description of flash interrupt operation the flash module uses the ccif ?g in combination with the ccie interrupt enable bit to generate the flash command interrupt request. the flash module uses the dfdif and sfdif ?gs in combination with 001 global address [15:0] anywhere within the sector to be erased. see section 20.1.2.2 for d-flash sector size. table 20-64. erase d-flash sector command error handling register error bit error condition fstat accerr set if ccobix[2:0] != 001 at command launch set if command not available in current mode (see table 20-28 ) set if an invalid global address [22:0] is supplied set if a misaligned word address is supplied (global address [0] != 0) fpviol set if the selected area of the d-flash memory is protected mgstat1 set if any errors have been encountered during the verify operation mgstat0 set if any non-correctable errors have been encountered during the verify operation table 20-65. flash interrupt sources interrupt source interrupt flag local enable global (ccr) mask flash command complete ccif (fstat register) ccie (fcnfg register) i bit ecc double bit fault on flash read dfdif (ferstat register) dfdie (fercnfg register) i bit ecc single bit fault on flash read sfdif (ferstat register) sfdie (fercnfg register) i bit table 20-63. erase d-flash sector command fccob requirements ccobix[2:0] fccob parameters
64 kbyte flash module (s12xftmr64k1v1) s12xs family reference manual, rev. 1.10 654 freescale semiconductor the dfdie and sfdie interrupt enable bits to generate the flash error interrupt request. for a detailed description of the register bits involved, refer to section 20.3.2.5, ?lash configuration register (fcnfg) ? section 20.3.2.6, ?lash error configuration register (fercnfg) ? section 20.3.2.7, ?lash status register (fstat) ? and section 20.3.2.8, ?lash error status register (ferstat) ? the logic used for generating the flash module interrupts is shown in figure 20-27 . figure 20-27. flash module interrupts implementation 20.4.4 wait mode the flash module is not affected if the mcu enters wait mode. the flash module can recover the mcu from wait via the ccif interrupt (see section 20.4.3, ?nterrupts ). 20.4.5 stop mode if a flash command is active (ccif = 0) when the mcu requests stop mode, the current flash operation will be completed before the cpu is allowed to enter stop mode. 20.5 security the flash module provides security information to the mcu. the flash security state is de?ed by the sec bits of the fsec register (see table 20-10 ). during reset, the flash module initializes the fsec register using data read from the security byte of the flash con?uration ?ld at global address 0x7f_ff0f. the security state out of reset can be permanently changed by programming the security byte of the flash con?uration ?ld. this assumes that you are starting from a mode where the necessary p-flash erase and program commands are available and that the upper region of the p-flash is unprotected. if the flash security byte is successfully programmed, its new value will take affect after the next mcu reset. the following subsections describe these security-related subjects: unsecuring the mcu using backdoor key access unsecuring the mcu in special single chip mode using bdm mode and security effects on flash command availability flash error interrupt request ccif ccie dfdif dfdie sfdif sfdie flash command interrupt request
64 kbyte flash module (s12xftmr64k1v1) s12xs family reference manual, rev. 1.10 freescale semiconductor 655 20.5.1 unsecuring the mcu using backdoor key access the mcu may be unsecured by using the backdoor key access feature which requires knowledge of the contents of the backdoor keys (four 16-bit words programmed at addresses 0x7f_ff00?x7f_ff07). if the keyen[1:0] bits are in the enabled state (see section 20.3.2.2 ), the verify backdoor access key command (see section 20.4.2.11 ) allows the user to present four prospective keys for comparison to the keys stored in the flash memory via the memory controller. if the keys presented in the verify backdoor access key command match the backdoor keys stored in the flash memory, the sec bits in the fsec register (see table 20-10 ) will be changed to unsecure the mcu. key values of 0x0000 and 0xffff are not permitted as backdoor keys. while the verify backdoor access key command is active, p-flash block 0 will not be available for read access and will return invalid data. the user code stored in the p-flash memory must have a method of receiving the backdoor keys from an external stimulus. this external stimulus would typically be through one of the on-chip serial ports. if the keyen[1:0] bits are in the enabled state (see section 20.3.2.2 ), the mcu can be unsecured by the backdoor key access sequence described below: 1. follow the command sequence for the verify backdoor access key command as explained in section 20.4.2.11 2. if the verify backdoor access key command is successful, the mcu is unsecured and the sec[1:0] bits in the fsec register are forced to the unsecure state of 10 the verify backdoor access key command is monitored by the memory controller and an illegal key will prohibit future use of the verify backdoor access key command. a reset of the mcu is the only method to re-enable the verify backdoor access key command. after the backdoor keys have been correctly matched, the mcu will be unsecured. after the mcu is unsecured, the sector containing the flash security byte can be erased and the flash security byte can be reprogrammed to the unsecure state, if desired. in the unsecure state, the user has full control of the contents of the backdoor keys by programming addresses 0x7f_ff00?x7f_ff07 in the flash con?uration ?ld. the security as de?ed in the flash security byte (0x7f_ff0f) is not changed by using the verify backdoor access key command sequence. the backdoor keys stored in addresses 0x7f_ff00?x7f_ff07 are unaffected by the verify backdoor access key command sequence. after the next reset of the mcu, the security state of the flash module is determined by the flash security byte (0x7f_ff0f). the verify backdoor access key command sequence has no effect on the program and erase protections de?ed in the flash protection register, fprot. 20.5.2 unsecuring the mcu in special single chip mode using bdm the mcu can be unsecured in special single chip mode by erasing the p-flash and d-flash memory by one of the following methods: reset the mcu into special single chip mode, delay while the erase test is performed by the bdm, send bdm commands to disable protection in the p-flash and d-flash memory, and execute the erase all blocks command write sequence to erase the p-flash and d-flash memory.
64 kbyte flash module (s12xftmr64k1v1) s12xs family reference manual, rev. 1.10 656 freescale semiconductor reset the mcu into special expanded wide mode, disable protection in the p-flash and d-flash memory and run code from external memory to execute the erase all blocks command write sequence to erase the p-flash and d-flash memory. after the ccif ?g sets to indicate that the erase all blocks operation has completed, reset the mcu into special single chip mode. the bdm will execute the erase verify all blocks command write sequence to verify that the p-flash and d-flash memory is erased. if the p-flash and d-flash memory are verified as erased the mcu will be unsecured. all bdm commands will be enabled and the flash security byte may be programmed to the unsecure state by the following method: send bdm commands to execute a ?rogram p-flash?command sequence to program the flash security byte to the unsecured state and reset the mcu. 20.5.3 mode and security effects on flash command availability the availability of flash module commands depends on the mcu operating mode and security state as shown in table 20-28 . 20.6 initialization on each system reset the flash module executes a reset sequence which establishes initial values for the flash block configuration parameters, the fprot and dfprot protection registers, and the fopt and fsec registers. the flash module reverts to built-in default values that leave the module in a fully protected and secured state if errors are encountered during execution of the reset sequence. if a double bit fault is detected during the reset sequence, both mgstat bits in the fstat register will be set. ccif remains clear throughout the reset sequence. the flash module holds off all cpu access for the initial portion of the reset sequence. while flash reads are possible when the hold is removed, writes to the fccobix, fccobhi, and fccoblo registers are ignored to prevent command activity while the memory controller remains busy. completion of the reset sequence is marked by setting ccif high which enables writes to the fccobix, fccobhi, and fccoblo registers to launch any available flash command. if a reset occurs while any flash command is in progress, that command will be immediately aborted. the state of the word being programmed or the sector/block being erased is not guaranteed.
s12xs family reference manual, rev. 1.10 freescale semiconductor 657 appendix a electrical characteristics a.1 general note the electrical characteristics given in this section should be used as a guide only. values cannot be guaranteed by freescale and are subject to change without notice. data are currently based on characterization data of 9s12xs128 material only unless marked differently. this supplement contains the most accurate electrical information for the s12xs family microcontroller available at the time of publication. this introduction is intended to give an overview on several common topics like power supply, current injection etc. a.1.1 parameter classi?ation the electrical parameters shown in this supplement are guaranteed by various methods. to give the customer a better understanding the following classi?ation is used and the parameters are tagged accordingly in the tables where appropriate. note this classi?ation is shown in the column labeled ??in the parameter tables where appropriate. p: those parameters are guaranteed during production testing on each individual device. c: those parameters are achieved by the design characterization by measuring a statistically relevant sample size across process variations. t: those parameters are achieved by design characterization on a small sample size from typical devices under typical conditions unless otherwise noted. all values shown in the typical column are within this category. d: those parameters are derived mainly from simulations. a.1.2 power supply the s12xs family utilizes several pins to supply power to the i/o ports, a/d converter, oscillator, and pll as well as the digital core. the vdda, vssa pin pairs supply the a/d converter and parts of the internal voltage regulator.
electrical characteristics s12xs family reference manual, rev. 1.10 658 freescale semiconductor the vddx, vssx pin pairs [2:1] supply the i/o pins. vddr supplies the internal voltage regulator. vddpll, vsspll pin pair supply the oscillator and the pll. vss1, vss2 and vss3 are internally connected by metal. all vddx pins are internally connected by metal. all vssx pins are internally connected by metal. vdda is connected to all vddx pins by diodes for esd protection such that vddx must not exceed vdda by more than a diode voltage drop. vdda can exceed vddx by more than a diode drop in order to support applications with a 5v a/d converter range and 3.3v i/o pin range. vssa and vssx are connected by anti-parallel diodes for esd protection. note in the following context v dd35 is used for either vdda, vddr, and vddx; v ss35 is used for either vssa and vssx unless otherwise noted. i dd35 denotes the sum of the currents ?wing into the vdda and vddr pins. the run mode current in the vddx domain is external load dependent. v dd is used for vdd, v ss is used for vss1, vss2 and vss3. v ddpll is used for vddpll, v sspll is used for vsspll i dd is used for the sum of the currents ?wing into vdd, vddf and vddpll. a.1.3 pins there are four groups of functional pins. a.1.3.1 i/o pins the i/o pins have a level in the range of 3.13v to 5.5v. this class of pins is comprised of all port i/o pins, the analog inputs, bkgd and the reset pins. some functionality may be disabled. for example the bkgd pin pull up is always enabled. a.1.3.2 analog reference this group is made up by the v rh and v rl pins. a.1.3.3 oscillator the pins extal, xtal dedicated to the oscillator have a nominal 1.8v level. they are supplied by vddpll.
electrical characteristics s12xs family reference manual, rev. 1.10 freescale semiconductor 659 a.1.3.4 test this pin is used for production testing only. the test pin must be tied to v ss in all applications. a.1.4 current injection power supply must maintain regulation within operating v dd35 or v dd range during instantaneous and operating maximum current conditions. if positive injection current (v in > v dd35 ) is greater than i dd35 , the injection current may ?w out of v dd35 and could result in external power supply going out of regulation. ensure external v dd35 load will shunt current greater than maximum injection current. this will be the greatest risk when the mcu is not consuming power; e.g., if no system clock is present, or if clock rate is very low which would reduce overall power consumption. a.1.5 absolute maximum ratings absolute maximum ratings are stress ratings only. a functional operation under or outside those maxima is not guaranteed. stress beyond those limits may affect the reliability or cause permanent damage of the device. this device contains circuitry protecting against damage due to high static voltage or electrical ?lds; however, it is advised that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (e.g., either v ss35 or v dd35 ).
electrical characteristics s12xs family reference manual, rev. 1.10 660 freescale semiconductor a.1.6 esd protection and latch-up immunity all esd testing is in conformity with cdf-aec-q100 stress test quali?ation for automotive grade integrated circuits. during the device quali?ation esd stresses were performed for the human body model (hbm) and the charge device model. a device will be de?ed as a failure if after exposure to esd pulses the device no longer meets the device speci?ation. complete dc parametric and functional testing is performed per the applicable device speci?ation at room temperature followed by hot temperature, unless speci?d otherwise in the device speci?ation. table a-1. absolute maximum ratings 1 1 beyond absolute maximum ratings device might be damaged. num rating symbol min max unit 1 i/o, regulator and analog supply voltage v dd35 ?.3 6.0 v 2 digital logic supply voltage 2 2 the device contains an internal voltage regulator to generate the logic and pll supply out of the i/o supply. the absolute maximum ratings apply when the device is powered from an external source. v dd ?.3 2.16 v 3 pll supply voltage 2 v ddpll ?.3 2.16 v 4 nvm supply voltage 2 v ddf ?.3 3.6 v 5 voltage difference v ddx to v dda ? vddx ?.0 0.3 v 6 voltage difference v ssx to v ssa ? vssx ?.3 0.3 v 7 digital i/o input voltage v in ?.3 6.0 v 8 analog reference v rh, v rl ?.3 6.0 v 9 extal, xtal v ilv ?.3 2.16 v 11 instantaneous maximum current single pin limit for all digital i/o pins 3 3 all digital i/o pins are internally clamped to v ssx and v ddx , or v ssa and v dda . i d ?5 +25 ma 12 instantaneous maximum current single pin limit for extal, xtal 4 4 those pins are internally clamped to v sspll and v ddpll . i dl ?5 +25 ma 14 maximum current single pin limit for power supply pins i dv ?00 +100 ma 15 storage temperature range t stg ?5 155 c
electrical characteristics s12xs family reference manual, rev. 1.10 freescale semiconductor 661 a.1.7 operating conditions this section describes the operating conditions of the device. unless otherwise noted those conditions apply to all the following data. note please refer to the temperature rating of the device (c, v, m) with regards to the ambient temperature t a and the junction temperature t j . for power dissipation calculations refer to section a.1.8, ?ower dissipation and thermal characteristics . table a-2. esd and latch-up test conditions model description symbol value unit human body series resistance r1 1500 ohm storage capacitance c 100 pf number of pulse per pin positive negative 1 1 charged device number of pulse per pin positive negative 3 3 latch-up minimum input voltage limit ?.5 v maximum input voltage limit 7.5 v table a-3. esd and latch-up protection characteristics num c rating symbol min max unit 1 c human body model (hbm) v hbm 2000 v 2 c charge device model (cdm) corner pins charge device model (cdm) edge pins v cdm 750 500 v 3 c latch-up current at t a = 125 c positive negative i lat +100 ?00 ma 4 c latch-up current at t a = 27 c positive negative i lat +200 ?00 ma table a-4. operating conditions rating symbol min typ max unit i/o, regulator and analog supply voltage v dd35 3.13 5 5.5 v nvm logic supply voltage 1 v ddf 2.7 2.8 2.9 v voltage difference v ddx to v dda ? vddx refer to table a-14
electrical characteristics s12xs family reference manual, rev. 1.10 662 freescale semiconductor note using the internal voltage regulator, operation is guaranteed in a power down until a low voltage reset assertion. a.1.8 power dissipation and thermal characteristics power dissipation and thermal characteristics are closely related. the user must assure that the maximum operating junction temperature is not exceeded. the average chip-junction temperature (t j ) in c can be obtained from: voltage difference v ddr to v ddx ? vddr -0.1 0 0.1 v voltage difference v ssx to v ssa ? vssx refer to table a-14 voltage difference v ss1 , v ss2 , v ss3 , v sspll to v ssx ? vss -0.1 0 0.1 v digital logic supply voltage 1 v dd 1.72 1.8 1.98 v pll supply voltage v ddpll 1.72 1.8 1.98 v oscillator 2 (loop controlled pierce) (full swing pierce) f osc 4 2 16 40 mhz bus frequency 3 f bus 0.5 40 mhz temperature option c operating junction temperature range operating ambient temperature range 4 t j t a ?0 ?0 27 110 85 c temperature option v operating junction temperature range operating ambient temperature range 4 t j t a ?0 ?0 27 130 105 c temperature option m operating junction temperature range operating ambient temperature range 4 t j t a ?0 ?0 27 150 125 c 1 the device contains an internal voltage regulator to generate the logic and pll supply out of the i/o supply. 2 this refers to the oscillator base frequency. typical crystal & resonator tolerances are supported. 3 please refer to table a-24 for maximum bus frequency limits with frequency modulation enabled 4 please refer to section a.1.8, ?ower dissipation and thermal characteristics for more details about the relation between ambient temperature t a and device junction temperature t j . table a-4. operating conditions t j t a p d ja ? () + = t j junction temperature, [ c ] = t a ambient temperature, [ c ] = p d total chip power dissipation, [w] = ja package thermal resistance, [ c/w] =
electrical characteristics s12xs family reference manual, rev. 1.10 freescale semiconductor 663 the total power dissipation can be calculated from: p io is the sum of all output currents on i/o ports associated with v ddx , whereby two cases with internal voltage regulator enabled and disabled must be considered: 1. internal voltage regulator disabled 2. internal voltage regulator enabled p d p int p io + = p int chip internal power dissipation, [w] = p io r dson i i io i 2 ? = r dson v ol i ol ------------ for outputs driven low ; = r dson v dd 35 v oh i oh -------------------------------------- for outputs driven high ; = p int i dd v dd ? i ddpll v ddpll ? i dda +v dda ? + = p int i ddr v ddr ? i dda v dda ? + =
electrical characteristics s12xs family reference manual, rev. 1.10 664 freescale semiconductor table a-5. thermal package characteristics (9s12xs256) 1 1 the values for thermal resistance are achieved by package simulations num c rating symbol min typ max unit lqfp 112 1 d thermal resistance lqfp 112, single sided pcb 2 2 junction to ambient thermal resistance, ja was simulated to be equivalent to the jedec speci?ation jesd51-2 in a horizontal con?uration in natural convection. ja 62 c/w 2 d thermal resistance lqfp 112, double sided pcb with 2 internal planes 3 3 junction to ambient thermal resistance, ja was simulated to be equivalent to the jedec speci?ation jesd51-7 in a horizontal con?uration in natural convection. ja 51 c/w 3 d junction to board lqfp 112 jb 39 c/w 4 d junction to case lqfp 112 4 jc 16 c/w 5 d junction to package top lqfp 112 5 jt 3 c/w qfp 80 6 d thermal resistance qfp 80, single sided pcb 2 ja 57 c/w 7 d thermal resistance qfp 80, double sided pcb with 2 internal planes 3 ja 45 c/w 8 d junction to board qfp 80 jb 29 c/w 9 d junction to case qfp 80 4 4 junction to case thermal resistance was simulated to be equivalent to the measured values using the cold plate technique with the cold plate temperature used as the ?ase temperature. this basic cold plate measurement technique is described by mil- std 883d, method 1012.1. this is the correct thermal metric to use to calculate thermal performance when the package is being used with a heat sink. jc 20 c/w 10 d junction to package top qfp 80 5 5 thermal characterization parameter jt is the ?esistance from junction to reference point thermocouple on top center of the case as de?ed in jesd51-2. jt is a useful value to use to estimate junction temperature in a steady state customer enviroment. jt 5 c/w lqfp 64 11 d thermal resistance lqfp 64, single sided pcb 2 ja 68 c/w 12 d thermal resistance lqfp 64, double sided pcb with 2 internal planes 3 ja 50 c/w 13 d junction to board lqfp 64 jb 32 c/w 14 d junction to case lqfp 64 4 jc 15 c/w 15 d junction to package top lqfp 64 5 jt 3 c/w
electrical characteristics s12xs family reference manual, rev. 1.10 freescale semiconductor 665 table a-6. thermal package characteristics (9s12xs128) 1 num c rating symbol min typ max unit lqfp 112 1 d thermal resistance lqfp 112, single sided pcb 2 ja 58 c/w 2 d thermal resistance lqfp 112, double sided pcb with 2 internal planes 3 ja 48 c/w 3 d junction to board lqfp 112 jb 36 c/w 4 d junction to case lqfp 112 4 jc 14 c/w 5 d junction to package top lqfp 112 5 jt 2 c/w qfp 80 6 d thermal resistance qfp 80, single sided pcb 2 ja 56 c/w 7 d thermal resistance qfp 80, double sided pcb with 2 internal planes 3 ja 43 c/w 8 d junction to board qfp 80 jb 28 c/w 9 d junction to case qfp 80 4 jc 19 c/w 10 d junction to package top qfp 80 5 jt 5 c/w lqfp 64 11 d thermal resistance lqfp 64, single sided pcb 2 ja 64 c/w 12 d thermal resistance lqfp 64, double sided pcb with 2 internal planes 3 ja 46 c/w 13 d junction to board lqfp 64 jb 28 c/w 14 d junction to case lqfp 64 4 jc 13 c/w 15 d junction to package top lqfp 64 5 jt 2 c/w 1 the values for thermal resistance are achieved by package simulations 2 junction to ambient thermal resistance, ja was simulated to be equivalent to the jedec speci?ation jesd51-2 in a horizontal con?uration in natural convection. 3 junction to ambient thermal resistance, ja was simulated to be equivalent to the jedec speci?ation jesd51-7 in a horizontal con?uration in natural convection. 4 junction to case thermal resistance was simulated to be equivalent to the measured values using the cold plate technique with the cold plate temperature used as the ?ase temperature. this basic cold plate measurement technique is described by mil- std 883d, method 1012.1. this is the correct thermal metric to use to calculate thermal performance when the package is being used with a heat sink. 5 thermal characterization parameter jt is the ?esistance from junction to reference point thermocouple on top center of the case as de?ed in jesd51-2. jt is a useful value to use to estimate junction temperature in a steady state customer enviroment.
electrical characteristics s12xs family reference manual, rev. 1.10 666 freescale semiconductor a.1.9 i/o characteristics this section describes the characteristics of all i/o pins except extal, xtal, test and supply pins. table a-7. 3.3-v i/o characteristics conditions are 3.13 v < v dd35 < 3.6 v junction temperature from ?0 c to +150 c, unless otherwise noted i/o characteristics for all i/o pins except extal, xtal,test and supply pins. num c rating symbol min typ max unit 1 p input high voltage v ih 0.65*v dd35 v t input high voltage v ih v dd35 + 0.3 v 2 p input low voltage v il 0.35*v dd35 v t input low voltage v il v ss35 ?0.3 v 3 t input hysteresis v hys 250 mv 4a p input leakage current (pins in high impedance input mode) 1 v in = v dd35 or v ss35 m temperature range -40 c to 150 c v temperature range -40 c to 130 c c temperature range -40 c to 110 c i in ? ?.75 ?.5 1 0.75 0.5 a 4b c input leakage current (pins in high impedance input mode) v in = v dd35 or v ss35 ? 40 c 27 c 70 c 85 c 100 c 105 c 110 c 120 c 125 c 130 c 150 c i in 1 1 8 14 26 32 40 60 74 92 240 ?a 5 c output high voltage (pins in output mode) partial drive i oh = ?.75 ma v oh v dd35 ?0.4 v 6 p output high voltage (pins in output mode) full drive i oh = ? ma v oh v dd35 ?0.4 v 7 c output low voltage (pins in output mode) partial drive i ol = +0.9 ma v ol 0.4 v 8 p output low voltage (pins in output mode) full drive i ol = +4.75 ma v ol 0.4 v 9 p internal pull up resistance v ih min > input voltage > v il max r pul 25 50 k ? 10 p internal pull down resistance v ih min > input voltage > v il max r pdh 25 50 k ? 11 d input capacitance c in ?pf 12 t injection current 2 single pin limit total device limit, sum of all injected currents i ics i icp ?.5 ?5 2.5 25 ma
electrical characteristics s12xs family reference manual, rev. 1.10 freescale semiconductor 667 13 p port h, j, p interrupt input pulse ?tered (stop) 3 t pulse 3 s 14 p port h, j, p interrupt input pulse passed (stop) 3 t pulse 10 s 15 d port h, j, p interrupt input pulse ?tered ( st op) t pulse 3 tcyc 16 d port h, j, p interrupt input pulse passed ( st op) t pulse 4 tcyc 17 d irq pulse width, edge-sensitive mode ( st op) pw irq 1 tcyc 18 d xirq pulse width with x-bit set (stop) pw xirq 4 tosc 1 maximum leakage current occurs at maximum operating temperature. 2 refer to section a.1.4, ?urrent injection for more details 3 parameter only applies in stop or pseudo stop mode. table a-7. 3.3-v i/o characteristics conditions are 3.13 v < v dd35 < 3.6 v junction temperature from ?0 c to +150 c, unless otherwise noted i/o characteristics for all i/o pins except extal, xtal,test and supply pins.
electrical characteristics s12xs family reference manual, rev. 1.10 668 freescale semiconductor table a-8. 5-v i/o characteristics conditions are 4.5 v < v dd35 < 5.5 v junction temperature from ?0 c to +150 c, unless otherwise noted i/o characteristics for all i/o pins except extal, xtal,test and supply pins. num c rating symbol min typ max unit 1 p input high voltage v ih 0.65*v dd35 v t input high voltage v ih v dd35 + 0.3 v 2 p input low voltage v il 0.35*v dd35 v t input low voltage v il v ss35 ?0.3 v 3 t input hysteresis v hys 250 mv 4a p input leakage current (pins in high impedance input mode) 1 v in = v dd35 or v ss35 m temperature range -40 c to 150 c v temperature range -40 c to 130 c c temperature range -40 c to 110 c i in ? ?.75 ?.5 1 0.75 0.5 a 4b c input leakage current (pins in high impedance input mode) v in = v dd35 or v ss35 ? 40 c 27 c 70 c 85 c 100 c 105 c 110 c 120 c 125 c 130 c 150 c i in 1 1 8 14 26 32 40 60 74 92 240 ?a 5 c output high voltage (pins in output mode) partial drive i oh = ? ma v oh v dd35 ?0.8 v 6 p output high voltage (pins in output mode) full drive i oh = ?0 ma v oh v dd35 ?0.8 v 7 c output low voltage (pins in output mode) partial drive i ol = +2 ma v ol 0.8 v 8 p output low voltage (pins in output mode) full drive i ol = +10 ma v ol 0.8 v 9 p internal pull up resistance v ih min > input voltage > v il max r pul 25 50 k ? 10 p internal pull down resistance v ih min > input voltage > v il max r pdh 25 50 k ? 11 d input capacitance c in ?pf 12 t injection current 2 single pin limit total device limit, sum of all injected currents i ics i icp ?.5 ?5 2.5 25 ma 13 p port h, j, p interrupt input pulse ?tered (stop) 3 t pulse 3 s 14 p port h, j, p interrupt input pulse passed (stop) 3 t pulse 10 s 15 d port h, j, p interrupt input pulse ?tered ( st op) t pulse 3 tcyc
electrical characteristics s12xs family reference manual, rev. 1.10 freescale semiconductor 669 a.1.10 supply currents this section describes the current consumption characteristics of the device as well as the conditions for the measurements. a.1.10.1 typical run current measurement conditions since the current consumption of the output drivers is load dependent, all measurements are without output loads and with minimum i/o activity. the currents are measured in single chip mode, s12xcpu code is executed from flash. v dd35 =5v, internal voltage regulator is enabled and the bus frequency is 40mhz using a 4mhz oscillator in loop controlled pierce mode. since the dbg and bdm modules are typically not used in the end application, the supply current values for these modules is not speci?d. an overhead of current consumption exists independent of the listed modules, due to voltage regulation and clock logic that is not dedicated to a speci? module. this is listed in the table row named ?verhead? table a-9 shows the con?uration of the peripherals for typical run current. a.1.10.2 maximum run current measurement conditions currents are measured in single chip mode, s12xcpu with v dd35 =5.5v, internal voltage regulator enabled and a 40mhz bus frequency from a 4mhz input. characterized parameters are derived using a 16 d port h, j, p interrupt input pulse passed ( st op) t pulse 4 tcyc 17 d irq pulse width, edge-sensitive mode ( st op) pw irq 1 tcyc 18 d xirq pulse width with x-bit set (stop) pw xirq 4 tosc 1 maximum leakage current occurs at maximum operating temperature. 2 refer to section a.1.4, ?urrent injection for more details 3 parameter only applies in stop or pseudo stop mode. table a-9. module con?urations for typical run supply (vddr+vdda) current v dd35 =5v peripheral con?uration s12xcpu 420 cycle loop: 384 dbne cycles plus subroutine entry to stimulate stacking (ram access) mscan con?ured to loop-back mode using a bit rate of 500kbit/s spi con?ured to master mode, continuously transmit data (0x55 or 0xaa) at 2mbit/s sci con?ured into loop mode, continuously transmit data (0x55) at speed of 19200 baud pwm con?ured to toggle its pins at the rate of 1khz tim the peripheral shall be con?ured in output compare mode. pulse accumulator and modulus counter enabled. atd the peripheral is con?ured to operate at its maximum speci?d frequency and to continuously convert voltages on all input channels in sequence. overhead vreg supplying 1.8v from a 5v input voltage, pll on table a-8. 5-v i/o characteristics conditions are 4.5 v < v dd35 < 5.5 v junction temperature from ?0 c to +150 c, unless otherwise noted i/o characteristics for all i/o pins except extal, xtal,test and supply pins.
electrical characteristics s12xs family reference manual, rev. 1.10 670 freescale semiconductor 4mhz loop controlled pierce oscillator. production test parameters are tested with a 4mhz square wave oscillator. table a-10 shows the con?uration of the peripherals for maximum run current a.1.10.3 stop current conditions unbonded ports must be correctly initialized to prevent current consumption due to ?ating inputs. typical stop current is measured with v dd35 =5v, maximum stop current is measured with v dd35 =5.5v. pseudo stop currents are measured with the oscillator con?ured for 4mhz lcp mode. production test parameters are tested with a 4mhz square wave oscillator. a.1.10.4 measurement results table a-11. module run supply currents table a-10. module con?urations for maximum run supply (vddr+vdda) current v dd35 =5.5v peripheral con?uration s12xcpu 420 cycle loop: 384 dbne cycles plus subroutine entry to stimulate stacking (ram access) mscan con?ured to loop-back mode using a bit rate of 1mbit/s spi con?ured to master mode, continuously transmit data (0x55 or 0xaa) at 4mbit/s sci con?ured into loop mode, continuously transmit data (0x55) at speed of 57600 baud pwm con?ured to toggle its pins at the rate of 40khz tim the peripheral shall be con?ured in output compare mode. pulse accumulator and modulus counter enabled. atd the peripheral is con?ured to operate at its maximum speci?d frequency and to continuously convert voltages on all input channels in sequence. overhead vreg supplying 1.8v from a 5v input voltage, pll on conditions are shown in table a-9 at ambient temperature unless otherwise noted num c rating min typ max unit 1 t s12xcpu 1.1 ma 2 t mscan 0.5 3 t spi 0.4 4 t sci 0.6 5 t pwm 0.9 6 t tim 0.3 7 t atd 1.7 8 t overhead 13.6
electrical characteristics s12xs family reference manual, rev. 1.10 freescale semiconductor 671 table a-12. run and wait current characteristics conditions are shown in table a-4 unless otherwise noted num c rating symbol min typ max unit run supply current (no external load, peripheral con?uration see table a-10.) 1 p peripheral set 1 f osc =4mhz, f bus =40mhz i dd35 32 ma 1a p peripheral set 1 device 9s12xs256 f osc =4mhz, f bus =40mhz i dd35 35 ma run supply current (no external load, peripheral con?uration see table a-9.) 2 c t t peripheral set 1 f osc =4mhz, f bus =40mhz f osc =4mhz, f bus =20mhz f osc =4mhz, f bus =8mhz 1 the following peripherals are on: atd0/tim/pwm/spi0/sci0-sci1/can0 i dd35 22 12.5 7 ma 3 t t t peripheral set 2 f osc =4mhz, f bus =40mhz f osc =4mhz, f bus =20mhz f osc =4mhz, f bus =8mhz 2 the following peripherals are on: atd0/tim/pwm/spi0/sci0-sci1 21 12 7 4 t t t peripheral set 3 f osc =4mhz, f bus =40mhz f osc =4mhz, f bus =20mhz f osc =4mhz, f bus =8mhz 3 the following peripherals are on: atd0/tim/pwm/spi0 21 11 6 5 t t t peripheral set 4 f osc =4mhz, f bus =40mhz f osc =4mhz, f bus =20mhz f osc =4mhz, f bus =8mhz 4 the following peripherals are on: atd0/tim/pwm 21 11 6 6 t t t peripheral set 5 f osc =4mhz, f bus =40mhz f osc =4mhz, f bus =20mhz f osc =4mhz, f bus =8mhz 5 the following peripherals are on: atd0/tim 21 11 5 wait supply current 7 p peripheral set 1 ,pll on i ddw ?122ma 7a p peripheral set 1 ,pll on, device 9s12xs256 16 24 8 t t peripheral set 2 f osc =4mhz, f bus =40mhz f osc =4mhz, f bus =8mhz 10 5.4 9 c all modules disabled, rti enabled, pll off 1.8 4
electrical characteristics s12xs family reference manual, rev. 1.10 672 freescale semiconductor table a-13. pseudo stop and full stop current conditions are shown in table a-4 unless otherwise noted num c rating symbol min typ max unit pseudo stop current (api, rti, and cop disabled) pll off, lcp mode 10a c c c c c c c c ?0 c 27 c 70 c 85 c 105 c 110 c 130 c 150 c i ddps 155 171 199 216 233 270 350 452 300 400 a pseudo stop current (api, rti, and cop disabled) pll off, fsp mode 10b p p p p p ?0 c 27 c 110 c 130 c 150 c i ddps 60 70 160 210 400 80 100 2400 2400 2400 a pseudo stop current (api, rti, and cop enabled) pll off, lcp mode 11 c c c c c c 27 c 70 c 85 c 105 c 125 c 150 c i ddps 186 209 245 270 383 487 a stop current 12 p p c c c c c c p ?0 c 27 c 70 c 85 c 105 c 110 c 125 c 130 c 150 c i dds 20 25 40 65 80 95 220 250 380 60 80 2000 a stop current (api active) 13 t t t t t ?0 c 27 c 85 c 110 c 130 c i dds 25 40 70 100 255 a stop current (atd active) 14 t t t 27 c 85 c 125 c i dds 190 230 400 a
electrical characteristics s12xs family reference manual, rev. 1.10 freescale semiconductor 673 a.2 atd characteristics this section describes the characteristics of the analog-to-digital converter. a.2.1 atd operating characteristics the table a-14 and table a-15 show conditions under which the atd operates. the following constraints exist to obtain full-scale, full range results: v ssa v rl v in v rh v dda . this constraint exists since the sample buffer ampli?r can not drive beyond the power supply levels that it ties to. if the input level goes outside of this range it will effectively be clipped. table a-14. atd operating characteristics a.2.2 factors in?encing accuracy source resistance, source capacitance and current injection have an in?ence on the accuracy of the atd. a further factor is that portad pins that are con?ured as output drivers switching. a.2.2.1 port ad output drivers switching portad output drivers switching can adversely affect the atd accuracy whilst converting the analog voltage on other portad pins because the output drivers are supplied from the vdda/vssa atd supply pins. although internal design measures are implemented to minimize the affect of output driver noise, it conditions are shown in table a-4 unless otherwise noted, supply voltage 3.13 v < v dda < 5.5 v num c rating symbol min typ max unit 1 d reference potential low high v rl v rh v ssa v dda /2 v dda /2 v dda v v 2 d voltage difference v ddx to v dda ? vddx ?.35 0 0.1 v 3 d voltage difference v ssx to v ssa ? vssx ?.1 0 0.1 v 4 c differential reference voltage 1 1 full accuracy is not guaranteed when differential voltage is less than 4.50 v v rh -v rl 3.13 5.0 5.5 v 5 c atd clock frequency (derived from bus clock via the prescaler bus) f atdclk 0.25 8.3 mhz 6 p atd clock frequency in stop mode (internal generated temperature and voltage dependent clock, iclk) 0.6 1 1.7 mhz 7 d adc conversion in stop, recovery time 2 2 when converting in stop mode (iclkstp=1) an atd stop recovery time tatdstprcv is required to switch back to bus clock based atdclk when leaving stop mode. do not access atd registers during this time. t atdstprcv 1.5 s 8d atd conversion period 3 12 bit resolution: 10 bit resolution: 8 bit resolution: 3 the minimum time assumes a sample time of 4 atd clock cycles. the maximum time assumes a sample time of 24 atd clock cycles and the discharge feature (smp_dis) enabled, which adds 2 atd clock cycles. n conv12 n conv10 n conv8 20 19 17 42 41 39 at d clock cycles
electrical characteristics s12xs family reference manual, rev. 1.10 674 freescale semiconductor is recommended to con?ure portad pins as outputs only for low frequency, low load outputs. the impact on atd accuracy is load dependent and not speci?d. the values speci?d are valid under condition that no portad output drivers switch during conversion. a.2.2.2 source resistance due to the input pin leakage current as speci?d in table a-7 and table a-8 in conjunction with the source resistance there will be a voltage drop from the signal source to the atd input. the maximum source resistance r s speci?s results in an error (10-bit resolution) of less than 1/2 lsb (2.5 mv) at the maximum leakage current. if device or operating conditions are less than worst case or leakage-induced error is acceptable, larger values of source resistance of up to 10kohm are allowed. a.2.2.3 source capacitance when sampling an additional internal capacitor is switched to the input. this can cause a voltage drop due to charge sharing with the external and the pin capacitance. for a maximum sampling error of the input voltage 1lsb (10-bit resilution), then the external ?ter capacitor, c f 1024 * (c ins ? inn ). a.2.2.4 current injection there are two cases to consider. 1. a current is injected into the channel being converted. the channel being stressed has conversion values of $3ff (in 10-bit mode) for analog inputs greater than v rh and $000 for values less than v rl unless the current is higher than speci?d as disruptive condition. 2. current is injected into pins in the neighborhood of the channel being converted. a portion of this current is picked up by the channel (coupling ratio k), this additional current impacts the accuracy of the conversion depending on the source resistance. the additional input voltage error on the converted channel can be calculated as: v err = k * r s * i inj with i inj being the sum of the currents injected into the two pins adjacent to the converted channel.
electrical characteristics s12xs family reference manual, rev. 1.10 freescale semiconductor 675 a.2.3 atd accuracy table a-16 and table a-17 specifies the atd conversion performance excluding any errors due to current injection, input capacitance and source resistance. table a-15. atd electrical characteristics conditions are shown in table a-4 unless otherwise noted num c rating symbol min typ max unit 1 c max input source resistance 1 1 refer to a.2.2.2 for further information concerning source resistance r s 1k ? 2 d total input capacitance non sampling total input capacitance sampling c inn c ins 10 16 pf 3 d input internal resistance r ina 5 15 k ? 4 c disruptive analog input current i na ?.5 2.5 ma 5 c coupling ratio positive current injection k p 1e-4 a/a 6 c coupling ratio negative current injection k n 3e-3 a/a
electrical characteristics s12xs family reference manual, rev. 1.10 676 freescale semiconductor a.2.3.1 atd accuracy de?itions for the following de?itions see also figure a-1 . differential non-linearity (dnl) is de?ed as the difference between two adjacent switching steps. the integral non-linearity (inl) is de?ed as the sum of all dnls: dnl i () v i v i1 1lsb -------------------------- - 1 = inl n () dnl i () i1 = n v n v 0 1lsb -------------------- - n ==
electrical characteristics s12xs family reference manual, rev. 1.10 freescale semiconductor 677 figure a-1. atd accuracy de?itions note figure a-1 shows only de?itions, for speci?ation values refer to table a- 16 and table a-17 . 1 5 vin mv 10 15 20 25 30 35 40 85 90 95 100 105 110 115 120 65 70 75 80 60 0 3 2 5 4 7 6 45 $3f7 $3f9 $3f8 $3fb $3fa $3fd $3fc $3fe $3ff $3f4 $3f6 $3f5 8 9 1 2 $ff $fe $fd $3f3 10-bit resolution 8-bit resolution ideal transfer curve 10-bit transfer curve 8-bit transfer curve 55 10-bit absolute error boundary 8-bit absolute error boundary lsb vi-1 vi dnl 5000 +
electrical characteristics s12xs family reference manual, rev. 1.10 678 freescale semiconductor table a-16. atd conversion performance 5v range table a-17. atd conversion performance 3.3v range conditions are shown in table a-4. unless otherwise noted. v ref = v rh - v rl = 5.12v. f atdclk = 8.0mhz the values are tested to be valid with no portad output drivers switching simultaneous with conversions. num c rating 1 , 2 1 the 8-bit and 10-bit mode operation is structurally tested in production test. absolute values are tested in 12-bit mode. 2 better performance is possible using specially designed multi-layer pcbs or averaging techniques. symbol min typ max unit 1 p resolution 12-bit lsb 1.25 mv 2 p differential nonlinearity 12-bit dnl -4 2 4 counts 3 p integral nonlinearity 12-bit inl -5 2.5 5 counts 4 p absolute error 3 3 these values include the quantization error which is inherently 1/2 count for any a/d converter. 12-bit ae -7 4 7 counts 5 c resolution 10-bit lsb 5 mv 6 c differential nonlinearity 10-bit dnl -1 0.5 1 counts 7 c integral nonlinearity 10-bit inl -2 1 2 counts 8 c absolute error 3 10-bit ae -3 2 3 counts 9 c resolution 8-bit lsb 20 mv 10 c differential nonlinearity 8-bit dnl -0.5 0.3 0.5 counts 11 c integral nonlinearity 8-bit inl -1 0.5 1 counts 12 c absolute error 3 8-bit ae -1.5 1 1.5 counts conditions are shown in table a-4. unless otherwise noted. v ref = v rh - v rl = 3.3v. f atdclk = 8.0mhz the values are tested to be valid with no portad output drivers switching simultaneous with conversions. num c rating 1 , 2 1 the 8-bit and 10-bit mode operation is structurally tested in production test. absolute values are tested in 12-bit mode. 2 better performance is possible using specially designed multi-layer pcbs or averaging techniques. symbol min typ max unit 1 p resolution 12-bit lsb 0.80 mv 2 p differential nonlinearity 12-bit dnl -6 3 6 counts 3 p integral nonlinearity 12-bit inl -7 3 7 counts 4 p absolute error 3 3 these values include the quantization error which is inherently 1/2 count for any a/d converter. 12-bit ae -8 4 8 counts 5 c resolution 10-bit lsb 3.22 mv 6 c differential nonlinearity 10-bit dnl -1.5 1 1.5 counts 7 c integral nonlinearity 10-bit inl -2 1 2 counts 8 c absolute error 3 10-bit ae -3 2 3 counts 9 c resolution 8-bit lsb 12.89 mv 10 c differential nonlinearity 8-bit dnl -0.5 0.3 0.5 counts 11 c integral nonlinearity 8-bit inl -1 0.5 1 counts 12 c absolute error 3 8-bit ae -1.5 1 1.5 counts
electrical characteristics s12xs family reference manual, rev. 1.10 freescale semiconductor 679 a.3 nvm, flash a.3.1 timing parameters the time base for all nvm program or erase operations is derived from the oscillator. a minimum oscillator frequency f nvmosc is required for performing program or erase operations. the nvm modules do not have any means to monitor the frequency and will not prevent program or erase operation at frequencies above or below the speci?d minimum. when attempting to program or erase the nvm modules at a lower frequency, a full program or erase transition is not assured. the program and erase operations are timed using a clock derived from the oscillator using the fclkdiv register. the frequency of this clock must be set within the limits speci?d as f nvmop . the minimum program and erase times shown in table a-18 are calculated for maximum f nvmop and maximum f nvmbus unless otherwise shown. the maximum times are calculated for minimum f nvmop a.3.1.1 erase verify all blocks (blank check) (fcmd=0x01) the time it takes to perform a blank check is dependant on the location of the ?st non-blank word starting at relative address zero. it takes one bus cycle per phrase to verify plus a setup of the command. assuming that no non blank location is found, then the erase verify all blocks is given by. a.3.1.2 erase verify block (blank check) (fcmd=0x02) the time it takes to perform a blank check is dependant on the location of the ?st non-blank word starting at relative address zero. it takes one bus cycle per phrase to verify plus a setup of the command. assuming that no non blank location is found, then the erase verify time for a single 256k nvm array is given by for a 128k nvm or d-flash array the erase verify time is given by a.3.1.3 erase verify p-flash section (fcmd=0x03) the maximum time depends on the number of phrases being veri?d (n vp ) t check 33500 1 f nvmbus --------------------- ? = t check 33500 1 f nvmbus --------------------- ? = t check 17200 1 f nvmbus --------------------- ? = t check 752 n vp + () 1 f nvmbus --------------------- ? =
electrical characteristics s12xs family reference manual, rev. 1.10 680 freescale semiconductor a.3.1.4 read once (fcmd=0x04) the maximum read once time is given by a.3.1.5 program p-flash (fcmd=0x06) the programming time for a single phrase of four p-flash words + associated eight ecc bits is dependant on the bus frequency as a well as on the frequency f nvmop and can be calculated according to the following formulas. the typical phrase programming time can be calculated using the following equation the maximum phrase programming time can be calculated using the following equation a.3.1.6 p-flash program once (fcmd=0x07) the maximum p-flash program once time is given by a.3.1.7 erase all blocks (fcmd=0x08) erasing all blocks takes: t 400 () 1 f nvmbus --------------------- ? = t bwpgm 128 1 f nvmop ------------------------- 1725 1 f nvmbus ---------------------------- - ? + ? = t bwpgm 130 1 f nvmop ------------------------- 2125 1 f nvmbus ---------------------------- - ? + ? = t bwpgm 162 1 f nvmop ------------------------ - 2400 1 f nvmbus ---------------------------- ? + ? t mass 100100 1 f nvmop ------------------------ - 35000 1 f nvmbus ---------------------------- ? + ?
electrical characteristics s12xs family reference manual, rev. 1.10 freescale semiconductor 681 a.3.1.8 erase p-flash block (fcmd=0x09) erasing a 256k nvm block takes erasing a 128k nvm block takes a.3.1.9 erase p-flash sector (fcmd=0x0a) the typical time to erase a1024-byte p-flash sector can be calculated using the maximum time to erase a1024-byte p-flash sector can be calculated using a.3.1.10 unsecure flash (fcmd=0x0b) the maximum time for unsecuring the ?sh is given by a.3.1.11 verify backdoor access key (fcmd=0x0c) the maximum verify backdoor access key time is given by a.3.1.12 set user margin level (fcmd=0x0d) the maximum set user margin level time is given by a.3.1.13 set field margin level (fcmd=0x0e) the maximum set ?ld margin level time is given by t mass 100100 1 f nvmop ------------------------ - 70000 1 f nvmbus ---------------------------- ? + ? t mass 100100 1 f nvmop ------------------------ - 35000 1 f nvmbus ---------------------------- ? + ? t era 20020 1 f nvmop ------------------ - ? ?? ?? 700 1 f nvmbus --------------------- ? ?? ?? + = t era 20020 1 f nvmop ------------------ - ? ?? ?? 1100 1 f nvmbus --------------------- ? ?? ?? + = t uns 100100 1 f nvmop ------------------------ - 70000 1 f nvmbus ---------------------------- ? + ? ?? ?? = t 400 1 f nvmbus ---------------------------- ? = t 350 1 f nvmbus ---------------------------- ? =
electrical characteristics s12xs family reference manual, rev. 1.10 682 freescale semiconductor a.3.1.14 erase verify d-flash section (fcmd=0x10) erase verify d-flash for a given number of words n w is given by . a.3.1.15 d-flash programming (fcmd=0x11) d-flash programming time is dependent on the number of words being programmed and their location with respect to a row boundary, because programming across a row boundary requires extra steps. the d- flash programming time is speci?d for different cases (1,2,3,4 words and 4 words across a row boundary) at a 40mhz bus frequency. the typical programming time can be calculated using the following equation, whereby n w denotes the number of words; bc=0 if no boundary is crossed and bc=1 if a boundary is crossed. the maximum programming time can be calculated using the following equation a.3.1.16 erase d-flash sector (fcmd=0x12) typical d-flash sector erase times are those expected on a new device, where no margin verify fails occur. they can be calculated using the following equation. maximum d-fash sector erase times can be calculated using the following equation. the d-flash sector erase time on a new device is ~5ms and can extend to 20ms as the ?sh is cycled. t 350 1 f nvmbus ---------------------------- ? = t check 840 n w + () 1 f nvmbus ---------------------------- ? t dpgm 15 54 n w ? () 16 bc ? () ++ () 1 f nvmop ------------------ - ? ?? ?? 460 640 n w ? () 500 bc ? () ++ () 1 f nvmbus --------------------- ? ?? ?? + = t dpgm 15 56 n w ? () 16 bc ? () ++ () 1 f nvmop ------------------ - ? ?? ?? 460 840 n w ? () 500 bc ? () ++ () 1 f nvmbus --------------------- ? ?? ?? + = t eradf 5025 1 f nvmop ------------------------ - 700 1 f nvmbus ---------------------------- ? + ? t eradf 20100 1 f nvmop ------------------------ - 3300 1 f nvmbus ---------------------------- ? + ?
electrical characteristics s12xs family reference manual, rev. 1.10 freescale semiconductor 683 table a-18. nvm timing characteristics a.3.2 nvm reliability parameters the reliability of the nvm blocks is guaranteed by stress test during quali?ation, constant process monitors and burn-in to screen early life failures. the data retention and program/erase cycling failure rates are speci?d at the operating conditions noted. the program/erase cycle count on the sector is incremented every time a sector or mass erase event is executed. the standard shipping condition for both the d-flash and p-flash memory is erased with security disabled. however it is recommended that each block or sector is erased before factory programming to ensure that the full data retention capability is achieved. data retention time is measured from the last erase operation. conditions are as shown in table a-4 , with 40mhz bus and f nvmop = 1mhz unless otherwise noted. num c rating symbol min typ max unit 1 d external oscillator clock f nvmosc 240 1 1 restrictions for oscillator in crystal mode apply. mhz 2 d bus frequency for programming or erase operations f nvmbus 1 40 mhz 3 d operating frequency f nvmop 800 1050 khz 4 d p-flash phrase programming t bwpgm 171 183 s 6 p p-flash sector erase time t era ?021ms 7 p erase all blocks (mass erase) time t mass 101 102 ms 7a d unsecure flash t uns 101 102 ms 8 d p-flash erase verify (blank check) time 2 2 valid for both ?rase verify all?or ?rase verify block?on 256k block without failing locations t check 33500 2 t cyc 9a d d-flash word programming 1 word t dpgm 97 104 s 9b d d-flash word programming 2 words t dpgm 167 181 s 9c d d-flash word programming 3 words t dpgm 237 258 s 9d d d-flash word programming 4 words t dpgm 307 335 s 9e d d-flash word programming 4 words crossing row boundary t dpgm 335 363 s 10 d d-flash sector erase time t eradf 5.2 3 3 this is a typical value for a new device 21 ms 11 d d-flash erase verify (blank check) time t check 17500 t cyc
electrical characteristics s12xs family reference manual, rev. 1.10 684 freescale semiconductor table a-19. nvm reliability characteristics conditions are shown in table a-4 unless otherwise noted num c rating symbol min typ max unit p-flash array 1 c data retention at an average junction temperature of t javg = 85 c 1 after up to 10,000 program/erase cycles 1 t javg does not exceed 85 c in a typical temperature pro?e over the lifetime of a consumer, industrial or automotive application. t pnvmret 15 100 2 2 typical data retention values are based on intrinsic capability of the technology measured at high temperature and de-rated to 25 c using the arrhenius equation. for additional information on how freescale de?es typical data retention, please refer to engineering bulletin eb618 years 2 c data retention at an average junction temperature of t javg = 85 c 3 after less than 100 program/erase cycles 3 t javg does not exceed 85 c in a typical temperature pro?e over the lifetime of a consumer, industrial or automotive application. t pnvmret 20 100 2 years 3 c p-flash number of program/erase cycles (-40 c tj 150 c ) n pflpe 10k 100k 3 cycles d-flash array 4 c data retention at an average junction temperature of t javg = 85 c 3 after up to 50,000 program/erase cycles t dnvmret 5 100 2 years 5 c data retention at an average junction temperature of t javg = 85 c 3 after less than 10,000 program/erase cycles t dnvmret 10 100 2 years 6 c data retention at an average junction temperature of t javg = 85 c 3 after less than 100 program/erase cycles t dnvmret 20 100 2 years 7 c d-flash number of program/erase cycles (-40 c tj 150 c ) n dflpe 50k 500k 3 cycles
electrical characteristics s12xs family reference manual, rev. 1.10 685 freescale semiconductor a.4 voltage regulator table a-20. voltage regulator electrical characteristics conditions are shown in table a-4 unless otherwise noted num c characteristic symbol min typical max unit 1 p input voltages v vddr,a 3.13 5.50 v 2p output voltage core full performance mode reduced power mode (mcu stop mode) v dd 1.72 1.84 1.60 1.98 v v 3p output voltage flash full performance mode reduced power mode (mcu stop mode) v ddf 2.60 2.82 2.20 2.90 v v 4p output voltage pll full performance mode reduced power mode (mcu stop mode) v ddpll 1.72 1.84 1.60 1.98 v v 5p low voltage interrupt 1 assert level deassert level 1 monitors vdda, active only in full performance mode. indicates i/o & adc performance degradation due to low supply voltage. v lvia v lvid 4.04 4.19 4.23 4.38 4.40 4.49 v v 6p vddx low voltage reset 23 assert level deassert level 2 device functionality is guaranteed on power down to the lvr assert level 3 monitors vddx, active only in full performance mode. mcu is monitored by the por in rpm (see figure a-2 ) v lvrxa v lvrxd 3.02 3.13 v v 7c trimmed api internal clock 4 ? f / f nominal 4 the api trimming bits must be set that the minimum period equals to 0.2 ms. df api -5 +5 % 8d the first period after enabling the counter by apife might be reduced by api start up delay t sdel 100 s 9 t temperature sensor slope dv ts 5.05 5.25 5.45 mv/ o c 10 t high temperature interrupt assert 5 assert (vreghttr=$88) deassert (vreghttr=$88) 5 a hysteresis is guaranteed by design t htia t htid 120 110 132 122 144 134 o c o c 11 p bandgap reference voltage v bg 1.13 1.21 1.32 v
electrical characteristics s12xs family reference manual, rev. 1.10 686 freescale semiconductor a.5 output loads a.5.1 resistive loads the voltage regulator is intended to supply the internal logic and oscillator. it allows no external dc loads. a.5.2 capacitive loads the capacitive loads are speci?d in table a-21 . ceramic capacitors with x7r dielectricum are required. a.5.3 chip power-up and voltage drops lvi (low voltage interrupt), por (power-on reset) and lvrs (low voltage reset) handle chip power-up or drops of the supply voltage. their function is shown in figure a-2 . figure a-2. s12xs family - chip power-up and voltage drops (not scaled) table a-21. s12xs family - capacitive loads num characteristic symbol min recommended max unit 1 vdd/vddf external capacitive load c ddext 176 220 264 nf 3 vddpll external capacitive load c ddpllext 80 220 264 nf v lvid v lvia v lvrxd v lvrxa v pord lvi por lvrx t v v ddx lvi enabled lvi disabled due to lvr v dd
electrical characteristics s12xs family reference manual, rev. 1.10 freescale semiconductor 687 figure a-3. s12xs family power sequencing during power sequencing v dda can be powered up before v ddr , v ddx . v ddr and v ddx must be powered up together adhering to the operating conditions differential. v rh power up must follow v dda to avoid current injection. v ddr, v dda t v v ddx >= 0
electrical characteristics s12xs family reference manual, rev. 1.10 688 freescale semiconductor a.6 reset, oscillator and pll this section summarizes the electrical characteristics of the various startup scenarios for oscillator and phase-locked loop (pll). a.6.1 startup table a-22 summarizes several startup characteristics explained in this section. detailed description of the startup behavior can be found in the clock and reset generator (crg) block description a.6.1.1 por the release level v porr and the assert level v pora are derived from the v dd supply. they are also valid if the device is powered externally. after releasing the por reset the oscillator and the clock quality check are started. if after a time t cqout no valid oscillation is detected, the mcu will start using the internal self clock. the fastest startup time possible is given by n uposc . a.6.1.2 sram data retention provided an appropriate external reset signal is applied to the mcu, preventing the cpu from executing code when v dd35 is out of speci?ation limits, the sram contents integrity is guaranteed if after the reset the porf bit in the crg ?gs register has not been set. a.6.1.3 external reset when external reset is asserted for a time greater than pw rstl the crg module generates an internal reset, and the cpu starts fetching the reset vector without doing a clock quality check, if there was an oscillation before reset. a.6.1.4 stop recovery out of stop the controller can be woken up by an external interrupt. a clock quality check as after por is performed before releasing the clocks to the system. if the mcu is woken-up by an interrupt and the fast wake-up feature is enabled (fstwkp = 1 and scme = 1), the system will resume operation in self-clock mode after t fws . table a-22. startup characteristics conditions are shown in table a-4 unless otherwise noted num c rating symbol min typ max unit 1 d reset input pulse width, minimum input time pw rstl 2t osc 2 d startup from reset n rst 192 196 n osc 3 d wait recovery startup time t wrs 14 t cyc 4 d fast wakeup from stop 1 1 including voltage regulator startup; v dd /v ddf ?ter capacitors 220 nf, v dd35 = 5 v, t= 25 c t fws 50 100 s
electrical characteristics s12xs family reference manual, rev. 1.10 freescale semiconductor 689 a.6.1.5 pseudo stop and wait recovery the recovery from pseudo stop and wait is essentially the same since the oscillator is not stopped in both modes. the controller can be woken up by internal or external interrupts. after t wrs the cpu starts fetching the interrupt vector.
electrical characteristics s12xs family reference manual, rev. 1.10 690 freescale semiconductor a.6.2 oscillator table a-23. oscillator characteristics conditions are shown in table a-4. unless otherwise noted num c rating symbol min typ max unit 1a c crystal oscillator range (loop controlled pierce) f osc 4.0 16 mhz 1b c crystal oscillator range (full swing pierce) 1,2 1 depending on the crystal a damping series resistor might be necessary 2 only valid if full swing pierce oscillator/external clock mode is selected f osc 2.0 40 mhz 2 p startup current i osc 100 a 3a c oscillator start-up time (lcp, 4mhz) 3 3 these values apply for carefully designed pcb layouts with capacitors that match the crystal/resonator requirements.. t uposc 2.2 10 ms 3b c oscillator start-up time (lcp, 8mhz) 3 t uposc 1.1 8 ms 3c c oscillator start-up time (lcp, 16mhz) 3 t uposc 0.75 5 ms 4a c oscillator start-up time (full swing pierce, 2mhz) 3 t uposc 5.2 40 ms 4b c oscillator start-up time (full swing pierce, 4mhz) 3 t uposc 3 20 ms 4c c oscillator start-up time (full swing pierce, 8mhz) 3 t uposc 1.8 10 ms 4d c oscillator start-up time (full swing pierce, 16mhz) 3 t uposc 1.2 5 ms 4e c oscillator start-up time (full swing pierce, 40mhz) 3 t uposc ? 4ms 5 d clock quality check time-out t cqout 0.45 2.5 s 6 p clock monitor failure assert frequency f cmfa 200 400 800 khz 7 p external square wave input frequency f ext 2.0 50 mhz 8 d external square wave pulse width low t extl 9.5 ns 9 d external square wave pulse width high t exth 9.5 ns 10 d external square wave rise time t extr 1ns 11 d external square wave fall time t extf 1ns 12 d input capacitance (extal, xtal pins) c in ?pf 13 p extal pin input high voltage v ih,extal 0.75*v ddpll v t extal pin input high voltage ,4 4 only applies if extal is externally driven v ih,extal v ddpll + 0.3 v 14 p extal pin input low voltage v il,extal 0.25*v ddpll v t extal pin input low voltage ,4 v il,extal v sspll - 0.3 v 15 c extal pin input hysteresis v hys,extal 180 mv 16 c extal pin oscillation amplitude (loop controlled pierce) v pp,extal 0.9 v
electrical characteristics s12xs family reference manual, rev. 1.10 freescale semiconductor 691 a.6.3 phase locked loop a.6.3.1 jitter information with each transition of the clock f cmp , the deviation from the reference clock f ref is measured and input voltage to the vco is adjusted accordingly.the adjustment is done continuously with no abrupt changes in the clock output frequency. noise, voltage, temperature and other factors cause slight variations in the control loop resulting in a clock jitter. this jitter affects the real minimum and maximum clock periods as illustrated in figure a-4 . figure a-4. jitter de?itions the relative deviation of t nom is at its maximum for one clock period, and decreases towards zero for larger number of clock periods (n). de?ing the jitter as: 2 3 n-1 n 1 0 t nom t max1 t min1 t maxn t minn jn () max 1 t max n () nt nom ? ---------------------- - 1 t min n () nt nom ? ---------------------- - , ?? ?? ?? =
electrical characteristics s12xs family reference manual, rev. 1.10 692 freescale semiconductor for n < 1000, the following equation is a good ? for the maximum jitter: figure a-5. maximum bus clock jitter approximation note on timers and serial modules a prescaler will eliminate the effect of the jitter to a large extent. table a-24. ipll characteristics conditions are shown in table a-4 unless otherwise noted num c rating symbol min typ max unit 1p self clock mode frequency 1 1 bus frequency is equivalent to f scm /2 f scm 1 4 mhz 2 t vco locking range f vco 32 120 mhz 3 t reference clock f ref 1 40 mhz 4 d lock detection |? lock | 0 1.5 % 2 2 % deviation from target frequency 5 d un-lock detection |? unl | 0.5 2.5 % 2 7 c time to lock t lock 214 150 + 256/f ref s 8c jitter ? parameter 1 3 3 f osc =4mhz, f bus =40mhz equivalent f pll =80mhz: refdiv=$00, refrq=01, syndiv=$09, vcofrq=01, postdiv=$00 j 1 1.2 % 9c jitter ? parameter 2 3 j 2 0% 10 c bus frequency for fm1=1, fm0=1 (frequency modulation in pllctl register of s12xe_crg) f bus 38 mhz 11 c bus frequency for fm1=1, fm0=0 (frequency modulation in pllctl register of s12xe_crg) f bus 39 mhz 12 c bus frequency for fm1=0, fm0=1 (frequency modulation in pllctl register of s12xe_crg) f bus 39 mhz jn () j 1 n -------- j 2 + = 1 5 10 20 n j(n)
electrical characteristics s12xs family reference manual, rev. 1.10 freescale semiconductor 693 a.7 mscan table a-25. mscan wake-up pulse characteristics conditions are shown in table a-4 unless otherwise noted num c rating symbol min typ max unit 1 p mscan wakeup dominant pulse ?tered t wup 1.5 s 2 p mscan wakeup dominant pulse pass t wup 5 s
electrical characteristics s12xs family reference manual, rev. 1.10 694 freescale semiconductor a.8 spi timing this section provides electrical parametrics and ratings for the spi. in table a-26 the measurement conditions are listed. a.8.1 master mode in figure a-6 the timing diagram for master mode with transmission format cpha = 0 is depicted. figure a-6. spi master timing (cpha = 0) table a-26. measurement conditions description value unit drive mode full drive mode load capacitance c load 1 , on all outputs 1 timing speci?d for equal load on all spi output pins. avoid asymmetric load. 50 pf thresholds for delay measurement points (20% / 80%) v ddx v sck (output) sck (output) miso (input) mosi (output) ss (output) 1 9 5 6 msb in2 bit msb-1. . . 1 lsb in msb out2 lsb out bit msb-1. . . 1 11 4 4 2 10 (cpol = 0) (cpol = 1) 3 13 13 1. if con?ured as an output. 2. lsbf = 0. for lsbf = 1, bit order is lsb, bit 1, bit 2... msb. 12 12
electrical characteristics s12xs family reference manual, rev. 1.10 freescale semiconductor 695 in figure a-7 the timing diagram for master mode with transmission format cpha=1 is depicted. figure a-7. spi master timing (cpha = 1) in table a-27 the timing characteristics for master mode are listed. table a-27. spi master mode timing characteristics num c characteristic symbol min typ max unit 1 d sck frequency f sck 1/2048 1 / 2 1 1 see figure a-8 . f bus 1 d sck period t sck 2 2048 t bus 2 d enable lead time t lead 1/2 t sck 3 d enable lag time t lag 1/2 t sck 4 d clock (sck) high or low time t wsck 1/2 t sck 5 d data setup time (inputs) t su 8ns 6 d data hold time (inputs) t hi 8ns 9 d data valid after sck edge t vsck 29 ns 10 d data valid after ss fall (cpha = 0) t vss 15 ns 11 d data hold time (outputs) t ho 20 ns 12 d rise and fall time inputs t r 8 ns 13 d rise and fall time outputs t rfo 8 ns sck (output) sck (output) miso (input) mosi (output) 1 5 6 msb in2 bit msb-1. . . 1 lsb in master msb out2 master lsb out bit msb-1. . . 1 4 4 9 12 13 11 port data (cpol = 0) (cpol = 1) port data ss (output) 2 12 13 3 1.if con?ured as output 2. lsbf = 0. for lsbf = 1, bit order is lsb, bit 1,bit 2... msb.
electrical characteristics s12xs family reference manual, rev. 1.10 696 freescale semiconductor figure a-8. d erating of maximum f sck to f bus ratio in master mode a.8.2 slave mode in figure a-9 the timing diagram for slave mode with transmission format cpha = 0 is depicted. figure a-9. spi slave timing (cpha = 0) 1/2 1/4 f sck /f bus f bus [mhz] 10 20 30 40 15 25 35 5 sck (input) sck (input) mosi (input) miso (output) ss (input) 1 9 5 6 msb in bit msb-1 . . . 1 lsb in slave msb slave lsb out bit msb-1. . . 1 11 4 4 2 7 (cpol = 0) (cpol = 1) 3 13 note: not de?ed 12 12 11 see 13 note 8 10 see note
electrical characteristics s12xs family reference manual, rev. 1.10 freescale semiconductor 697 in figure a-10 the timing diagram for slave mode with transmission format cpha = 1 is depicted. figure a-10. spi slave timing (cpha = 1) in table a-28 the timing characteristics for slave mode are listed. table a-28. spi slave mode timing characteristics num c characteristic symbol min typ max unit 1 d sck frequency f sck dc 1 / 4f bus 1 d sck period t sck 4 t bus 2 d enable lead time t lead 4 t bus 3 d enable lag time t lag 4 t bus 4 d clock (sck) high or low time t wsck 4 t bus 5 d data setup time (inputs) t su 8 ns 6 d data hold time (inputs) t hi 8 ns 7 d slave access time (time to data active) t a 20 ns 8 d slave miso disable time t dis 22 ns 9 d data valid after sck edge t vsck 29 + 0.5 ? t bus 1 1 0.5 t bus added due to internal synchronization delay ns 10 d data valid after ss fall t vss 29 + 0.5 ? t bus 1 ns 11 d data hold time (outputs) t ho 20 ns 12 d rise and fall time inputs t r 8 ns 13 d rise and fall time outputs t rfo 8 ns sck (input) sck (input) mosi (input) miso (output) 1 5 6 msb in bit msb-1 . . . 1 lsb in msb out slave lsb out bit msb-1 . . . 1 4 4 9 12 13 11 (cpol = 0) (cpol = 1) ss (input) 2 12 13 3 note: not de?ed slave 7 8 see note
package information s12xs family reference manual, rev. 1.10 698 freescale semiconductor appendix b package information this section provides the physical dimensions of the s12xs family packages.
package information s12xs family reference manual, rev. 1.10 freescale semiconductor 699 b.1 112-pin lqfp mechanical dimensions figure b-1. 112-pin lqfp (case no. 987) - page 1
package information s12xs family reference manual, rev. 1.10 700 freescale semiconductor figure b-2. 112-pin lqfp (case no. 987) - page 2
package information s12xs family reference manual, rev. 1.10 freescale semiconductor 701 figure b-3. 112-pin lqfp (case no. 987) - page 3
package information s12xs family reference manual, rev. 1.10 702 freescale semiconductor b.2 80-pin qfp mechanical dimensions figure b-4. 80-pin qfp (case no. 841b) - page 1
package information s12xs family reference manual, rev. 1.10 freescale semiconductor 703 figure b-5. 80-pin qfp (case no. 841b) - page 2
package information s12xs family reference manual, rev. 1.10 704 freescale semiconductor figure b-6. 80-pin qfp (case no. 841b) - page 3
package information s12xs family reference manual, rev. 1.10 freescale semiconductor 705 b.3 64-pin lqfp mechanical dimensions
package information s12xs family reference manual, rev. 1.10 706 freescale semiconductor figure b-7. 64-pin lqfp (case no. 840f) - page 2
package information s12xs family reference manual, rev. 1.10 freescale semiconductor 707 figure b-8. 64-pin lqfp (case no. 840f) - page 3
pcb layout guidelines s12xs family reference manual, rev. 1.10 708 freescale semiconductor appendix c pcb layout guidelines c.1 general the pcb must be carefully laid out to ensure proper operation of the voltage regulator as well as of the mcu itself. the following rules must be observed: every supply pair must be decoupled by a ceramic capacitor connected as near as possible to the corresponding pins . central point of the ground star should be the vss3 pin. use low ohmic low inductance connections between vss1, vss2 and vss3. vsspll must be directly connected to vss3. keep traces of vsspll, extal, and xtal as short as possible and occupied board area for c7, c8, and q1 as small as possible. do not place other signals or supplies underneath area occupied by c7, c8, and q1 and the connection area to the mcu. central power input should be fed in at the vdda/vssa pins. example layouts are illustrated on the following pages. table c-1. recommended decoupling capacitor choice component purpose type value c1 v ddf ?ter capacitor ceramic x7r 220 nf c2 n/a c3 v ddx2 ?ter capacitor x7r/tantalum >=100 nf c4 v ddpll ?ter capacitor ceramic x7r 220 nf c5 osc load capacitor from crystal manufacturer c6 osc load capacitor c7 v ddr ?ter capacitor x7r/tantalum >=100 nf c8 n/a c9 v dd ?ter capacitor ceramic x7r 220 nf c10 v dda1 ?ter capacitor ceramic x7r >=100 nf c11 v ddx1 ?ter capacitor x7r/tantalum >=100 nf q1 quartz
pcb layout guidelines s12xs family reference manual, rev. 1.10 freescale semiconductor 709 c.1.1 112-pin lqfp recommended pcb layout figure c-1. 112-pin lqfp recommended pcb layout (loop controlled pierce oscillator)
pcb layout guidelines s12xs family reference manual, rev. 1.10 710 freescale semiconductor c.1.2 80-pin qfp recommended pcb layout figure c-2. 80-pin qfp recommended pcb layout (loop controlled pierce oscillator)
pcb layout guidelines s12xs family reference manual, rev. 1.10 freescale semiconductor 711 c.1.3 64-pin lqfp recommended pcb layout figure c-3. 64-pin lqfp recommended pcb layout (loop controlled pierce oscillator) tbd
derivative differences s12xs family reference manual, rev. 1.10 712 freescale semiconductor appendix d derivative differences d.1 memory sizes and package options s12xs family note for the 80qfp and 64lqfp package options, several peripheral functions can be routed under software control to different pins. not all functions are available simultaneously. for details see table 1-5. table d-1. package and memory options of s12xs family device package flash ram data flash 9s12xs256 112 lqfp 256k 12k 8k 80 qfp 64 lqfp 9s12xs128 112 lqfp 128k 8k 8k 80 qfp 64 lqfp 9s12xs64 112 lqfp 64k 4k 4k 80 qfp 64 lqfp table d-2. peripheral options of s12xs family members device package can sci spi tim pit a/d pwm 9s12xs256 112 lqfp 1 2 1 8ch 4ch 16ch 8ch 80 qfp 1 2 1 8ch 4ch 8ch 8ch 64 lqfp 1 2 1 8ch 4ch 8ch 8ch 9s12xs128 112 lqfp 1 2 1 8ch 4ch 16ch 8ch 80 qfp 1 2 1 8ch 4ch 8ch 8ch 64 lqfp 1 2 1 8ch 4ch 8ch 8ch 9s12xs64 112 lqfp 1 2 1 8ch 4ch 16ch 8ch 80 qfp 1 2 1 8ch 4ch 8ch 8ch 64 lqfp 1 2 1 8ch 4ch 8ch 8ch
detailed register address map s12xs family reference manual, rev. 1.10 freescale semiconductor 713 appendix e detailed register address map e.1 detailed register map the following tables show the detailed register map of the s12xs family. 0x0000?x0009 port integration module (pim) map 1 of 5 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x0000 porta r pa7 pa6 pa5 pa4 pa3 pa2 pa1 pa 0 w 0x0001 portb r pb7 pb6 pb5 pb4 pb3 pb2 pb1 pb0 w 0x0002 ddra r ddra7 ddra6 ddra5 ddra4 ddra3 ddra2 ddra1 ddra0 w 0x0003 ddrb r ddrb7 ddrb6 ddrb5 ddrb4 ddrb3 ddrb2 ddrb1 ddrb0 w 0x0004 reserved r00000000 w 0x0005 reserved r00000000 w 0x0006 reserved r00000000 w 0x0007 reserved r00000000 w 0x0008 porte r pe7 pe6 pe5 pe4 pe3 pe2 pe1 pe0 w 0x0009 ddre r ddre7 ddre6 ddre5 ddre4 ddre3 ddre2 00 w 0x000a?x000b module mapping control (s12xmmc) map 1 of 2 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x000a reserved r00000000 w 0x000b mode r modc 0000000 w 0x000c?x000d port integration module (pim) map 2 of 5 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x000c pucr r pupke bkpue 0 pupee 00 pupbe pupae w 0x000d rdriv r rdpk 00 rdpe 00 rdpb rdpa w
detailed register address map s12xs family reference manual, rev. 1.10 714 freescale semiconductor 0x000e?x000f reserved register space address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x000e reserved r00000000 w 0x000f reserved r00000000 w 0x0010?x0017 module mapping control (s12xmmc) map 2 of 2 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x0010 gpage r0 gp6 gp5 gp4 gp3 gp2 gp1 gp0 w 0x0011 direct r dp15 dp14 dp13 dp12 dp11 dp10 dp9 dp8 w 0x0012 reserved r00000000 w 0x0013 mmcctl1 r mgramo n 0 dfifron pgmifro n 0000 w 0x0014 reserved r00000000 w 0x0015 ppage r pix7 pix6 pix5 pix4 pix3 pix2 pix1 pix0 w 0x0016 rpage r rp7 rp6 rp5 rp4 rp3 rp2 rp1 rp0 w 0x0017 epage r ep7 ep6 ep5 ep4 ep3 ep2 ep1 ep0 w 0x0018?x001b miscellaneous peripheral address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x0018 reserved r00000000 w 0x0019 reserved r00000000 w 0x001a partidh r partidh w 0x001b partidl r partidl w 0x001c?x001d port integration module (pim) map 3 of 5 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x001c eclkctl r neclk nclkx2 div16 ediv4 ediv3 ediv2 ediv1 ediv0 w 0x001d reserved r00000000 w
detailed register address map s12xs family reference manual, rev. 1.10 freescale semiconductor 715 0x001e?x001f port integration module (pim) map 3 of 5 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x001e irqcr r irqe irqen 000000 w 0x001f reserved r00000000 w 0x0020?x002f debug module (s12xdbg) map address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x0020 dbgc1 r arm 0 reserved bdm dbgbrk reserved comrv w trig 0x0021 dbgsr r tbf 0 0 0 0 ssf2 ssf1 ssf0 w 0x0022 dbgtcr r reserved tsource trange trcmod talign w 0x0023 dbgc2 r0 0 0 0 cdcm abcm w 0x0024 dbgtbh r bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 w 0x0025 dbgtbl r bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 w 0x0026 dbgcnt r 0 cnt w 0x0027 dbgscrx r0 0 0 0 sc3 sc2 sc1 sc0 w 0x0027 dbgmfr r 0 0 0 0 mc3 mc2 mc1 mc0 w 0x0028 1 dbgxctl (compa/c) r0 ndb tag brk rw rwe reserved compe w 0x0028 2 dbgxctl (compb/d) r sze sz tag brk rw rwe reserved compe w 0x0029 dbgxah r0 bit 22 21 20 19 18 17 bit 16 w 0x002a dbgxam r bit 15 14 13 12 11 10 9 bit 8 w 0x002b dbgxal r bit 7 6 54321 bit 0 w 0x002c dbgxdh r bit 15 14 13 12 11 10 9 bit 8 w 0x002d dbgxdl r bit 7 6 54321 bit 0 w 0x002e dbgxdhm r bit 15 14 13 12 11 10 9 bit 8 w 0x002f dbgxdlm r bit 7 6 54321 bit 0 w 1 this represents the contents if the comparator a or c control register is blended into this address 2 this represents the contents if the comparator b or d control register is blended into this address
detailed register address map s12xs family reference manual, rev. 1.10 716 freescale semiconductor 0x0030?x0031 reserved register space address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x0030 reserved r00000000 w 0x0031 reserved r00000000 w 0x0032?x0033 port integration module (pim) map 4 of 5 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x0032 portk r pk7 0 pk5 pk4 pk3 pk2 pk1 pk0 w 0x0033 ddrk r ddrk7 0 ddrk5 ddrk4 ddrk3 ddrk2 ddrk1 ddrk0 w 0x0034?x003f clock and reset generator (crg) map address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x0034 synr r vcofrq[1:0] syndiv[5:0] w 0x0035 refdv r reffrq[1:0] refdiv[5:0] w 0x0036 postdiv r0 0 0 postdiv[4:0] w 0x0037 crgflg r rtif porf lvrf lockif lock ilaf scmif scm w 0x0038 crgint r rtie 00 lockie 00 scmie 0 w 0x0039 clksel r pllsel pstp xclks 0 pllwai 0 rtiwai copwai w 0x003a pllctl r cme pllon fm1 fm0 fstwkp pre pce scme w 0x003b rtictl r rtdec rtr6 rtr5 rtr4 rtr3 rtr2 rtr1 rtr0 w 0x003c copctl r wcop rsbck 000 cr2 cr1 cr0 w wrtmas k 0x003d forbyp r00000000 w reserved for factory test 0x003e ctctl r0000 000 w reserved for factory test 0x003f armcop r00000000 w bit 7 6 54321 bit 0
detailed register address map s12xs family reference manual, rev. 1.10 freescale semiconductor 717 0x0040?x006f timer module (tim) map address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x0040 tios r ios7 ios6 ios5 ios4 ios3 ios2 ios1 ios0 w 0x0041 cforc r00000000 w foc7 foc6 foc5 foc4 foc3 foc2 foc1 foc0 0x0042 oc7m r oc7m7 oc7m6 oc7m5 oc7m4 oc7m3 oc7m2 oc7m1 oc7m0 w 0x0043 oc7d r oc7d7 oc7d6 oc7d5 oc7d4 oc7d3 oc7d2 oc7d1 oc7d0 w 0x0044 tcnth r bit 15 14 13 12 11 10 9 bit 8 w 0x0045 tcntl r bit 7 6 5 4 3 2 1 bit 0 w 0x0046 tscr1 r ten tswai tsfrz tffca prnt 000 w 0x0047 ttov r tov7 tov6 tov5 tov4 tov3 tov2 tov1 tov0 w 0x0048 tctl1 r om7 ol7 om6 ol6 om5 ol5 om4 ol4 w 0x0049 tctl2 r om3 ol3 om2 ol2 om1 ol1 om0 ol0 w 0x004a tctl3 r edg7b edg7a edg6b edg6a edg5b edg5a edg4b edg4a w 0x004b tctl4 r edg3b edg3a edg2b edg2a edg1b edg1a edg0b edg0a w 0x004c tie r c7i c6i c5i c4i c3i c2i c1i c0i w 0x004d tscr2 r toi 000 tcre pr2 pr1 pr0 w 0x004e tflg1 r c7f c6f c5f c4f c3f c2f c1f c0f w 0x004f tflg2 r tof 0000000 w 0x0050 tc0h r bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 w 0x0051 tc0l r bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 w 0x0052 tc1h r bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 w 0x0053 tc1l r bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 w 0x0054 tc2h r bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 w 0x0055 tc2l r bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 w 0x0056 tc3h r bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 w
detailed register address map s12xs family reference manual, rev. 1.10 718 freescale semiconductor 0x0057 tc3l r bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 w 0x0058 tc4h r bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 w 0x0059 tc4l r bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 w 0x005a tc5h r bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 w 0x005b tc5l r bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 w 0x005c tc6h r bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 w 0x005d tc6l r bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 w 0x005e tc7h r bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 w 0x005f tc7l r bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 w 0x0060 pactl r0 paen pamod pedge clk1 clk0 paovi pai w 0x0061 paflg r000000 paovf paif w 0x0062 pacnth r pacnt15 pacnt14 pacnt13 pacnt12 pacnt11 pacnt10 pacnt9 pacnt8 w 0x0063 pacntl r pacnt7 pacnt6 pacnt5 pacnt4 pacnt3 pacnt2 pacnt1 pacnt0 w 0x0064 0x006b reserved r00000000 w 0x006c ocpd r ocpd7 ocpd6 ocpd5 ocpd4 ocpd3 ocpd2 ocpd1 ocpd0 w 0x006d reserved r w 0x006e ptpsr r ptps7 ptps6 ptps5 ptps4 ptps3 ptps2 ptps1 ptps0 w 0x006f reserved r00000000 w 0x0070?x00c7 reserved register space address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x0070- 0x00c7 reserved r00000000 w 0x0040?x006f timer module (tim) map address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
detailed register address map s12xs family reference manual, rev. 1.10 freescale semiconductor 719 0x00c8?x00cf asynchronous serial interface (sci0) map address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x00c8 sci0bdh 1 r iren tnp1 tnp0 sbr12 sbr11 sbr10 sbr9 sbr8 w 0x00c9 sci0bdl 1 r sbr7 sbr6 sbr5 sbr4 sbr3 sbr2 sbr1 sbr0 w 0x00ca sci0cr1 1 r loops sciswai rsrc m wake ilt pe pt w 0x00c8 sci0asr1 2 r rxedgif 0000 berrv berrif bkdif w 0x00c9 sci0acr1 2 r rxedgie 00000 berrie bkdie w 0x00ca sci0acr2 2 r00000 berrm1 berrm0 bkdfe w 0x00cb sci0cr2 r tie tcie rie ilie te re rwu sbk w 0x00cc sci0sr1 r tdre tc rdrf idle or nf fe pf w 0x00cd sci0sr2 r amap 00 txpol rxpol brk13 txdir raf w 0x00ce sci0drh rr8 t8 000000 w 0x00cf sci0drl rr7r6r5r4r3r2r1r0 wt7t6t5t4t3t2t1t0 1 those registers are accessible if the amap bit in the sci0sr2 register is set to zero 2 those registers are accessible if the amap bit in the sci0sr2 register is set to one 0x00d0?x00d7 asynchronous serial interface (sci1) map address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x00d0 sci1bdh 1 r iren tnp1 tnp0 sbr12 sbr11 sbr10 sbr9 sbr8 w 0x00d1 sci1bdl 1 r sbr7 sbr6 sbr5 sbr4 sbr3 sbr2 sbr1 sbr0 w 0x00d2 sci1cr1 1 r loops sciswai rsrc m wake ilt pe pt w 0x00d0 sci1asr1 2 r rxedgif 0000 berrv berrif bkdif w 0x00d1 sci1acr1 2 r rxedgie 00000 berrie bkdie w 0x00d2 sci1acr2 2 r00000 berrm1 berrm0 bkdfe w 0x00d3 sci1cr2 r tie tcie rie ilie te re rwu sbk w 0x00d4 sci1sr1 r tdre tc rdrf idle or nf fe pf w
detailed register address map s12xs family reference manual, rev. 1.10 720 freescale semiconductor 0x00d5 sci1sr2 r amap 00 txpol rxpol brk13 txdir raf w 0x00d6 sci1drh rr8 t8 000000 w 0x00d7 sci1drl rr7r6r5r4r3r2r1r0 wt7t6t5t4t3t2t1t0 1 those registers are accessible if the amap bit in the sci1sr2 register is set to zero 2 those registers are accessible if the amap bit in the sci1sr2 register is set to one 0x00d8?x00df serial peripheral interface (spi0) map address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x00d8 spi0cr1 r spie spe sptie mstr cpol cpha ssoe lsbfe w 0x00d9 spi0cr2 r0 xfrw 0 modfen bidiroe 0 spiswai spc0 w 0x00da spi0br r0 sppr2 sppr1 sppr0 0 spr2 spr1 spr0 w 0x00db spi0sr r spif 0 sptef modf 0 0 0 0 w 0x00dc spi0drh r r15 r14 r13 r12 r11 r10 r9 r8 w t15 t14 t13 t12 t11 t10 t9 t8 0x00dd spi0drl rr7r6r5r4r3r2r1r0 wt7t6t5t4t3t2t1t0 0x00de reserved r00000000 w 0x00df reserved r00000000 w 0x00e0?x00ff reserved register space address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x00e0- 0x00ff reserved r00000000 w 0x0100?x0113 nvm control register (ftmr) map address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x0100 fclkdiv r fdivld fdiv6 fdiv5 fdiv4 fdiv3 fdiv2 fdiv1 fdiv0 w 0x0101 fsec r keyen1 keyen0 rnv5 rnv4 rnv3 rnv2 sec1 sec0 w 0x0102 fccobix r0 0 0 0 0 ccobix2 ccobix1 ccobix0 w 0x0103 feccrix r0 0 0 0 0 eccrix2 eccrix1 eccrix0 w 0x00d0?x00d7 asynchronous serial interface (sci1) map (continued) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
detailed register address map s12xs family reference manual, rev. 1.10 freescale semiconductor 721 0x0104 fcnfg r ccie 00 ignsf 00 fdfd fsfd w 0x0105 fercnfg r0 0 0 0 0 0 dfdie sfdie w 0x0106 fstat r ccif 0 accerr fpviol mgbusy rsvd mgstat1 mgstat0 w 0x0107 ferstat r0 0 0 0 0 0 dfdif sfdif w 0x0108 fprot r fpopen rnv6 fphdis fphs1 fphs0 fpldis fpls1 fpls0 w 0x0109 dfprot r dpopen 00 dps4 dps3 dps2 dps1 dps0 w 0x010a fccobhi r ccob15 ccob14 ccob13 ccob12 ccob11 ccob10 ccob9 ccob8 w 0x010b fccoblo r ccob7 ccob6 ccob5 ccob4 ccob3 ccob2 ccob1 ccob0 w 0x010c reserved r00000000 w 0x010d reserved r00000000 w 0x010e feccrhi r eccr15 eccr14 eccr13 eccr12 eccr11 eccr10 eccr9 eccr8 w 0x010f feccrlo r eccr7 eccr6 eccr5 eccr4 eccr3 eccr2 eccr1 eccr0 w 0x0110 fopt r nv7 nv6 nv5 nv4 nv3 nv2 nv1 nv0 w 0x0111 reserved r00000000 w 0x0112 reserved r00000000 w 0x0113 reserved r00000000 w 0x0114?x011f reserved register space address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x0114- 0x011f reserved r00000000 w 0x0100?x0113 nvm control register (ftmr) map (continued) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
detailed register address map s12xs family reference manual, rev. 1.10 722 freescale semiconductor 0x0120?x012f interrupt module (s12xint) map address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x0120 reserved r00000000 w 0x0121 ivbr r ivb_addr[7:0] w 0x0122 reserved r00000000 w 0x0123 reserved r00000000 w 0x0124 reserved r00000000 w 0x0125 reserved r00000000 w 0x0126 int_xgprio r00000 xilvl[2:0] w 0x0127 int_cfaddr r int_cfaddr[7:4] 0000 w 0x0128 int_cfdata0 r rqst 0000 priolvl[2:0] w 0x0129 int_cfdata1 r rqst 0000 priolvl[2:0] w 0x012a int_cfdata2 r rqst 0000 priolvl[2:0] w 0x012b int_cfdata3 r rqst 0000 priolvl[2:0] w 0x012c int_cfdata4 r rqst 0000 priolvl[2:0] w 0x012d int_cfdata5 r rqst 0000 priolvl[2:0] w 0x012e int_cfdata6 r rqst 0000 priolvl[2:0] w 0x012f int_cfdata7 r rqst 0000 priolvl[2:0] w 0x00130?x013f reserved register space address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x0130- 0x013f reserved r00000000 w 0x0140?x017f mscan (can0) map address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x0140 can0ctl0 r rxfrm rxact cswai synch time wupe slprq initrq w 0x0141 can0ctl1 r cane clksrc loopb listen borm wupm slpak initak w
detailed register address map s12xs family reference manual, rev. 1.10 freescale semiconductor 723 0x0142 can0btr0 r sjw1 sjw0 brp5 brp4 brp3 brp2 brp1 brp0 w 0x0143 can0btr1 r samp tseg22 tseg21 tseg20 tseg13 tseg12 tseg11 tseg10 w 0x0144 can0rflg r wupif cscif rstat1 rstat0 tstat1 tstat0 ovrif rxf w 0x0145 can0rier r wupie cscie rstate1 rstate0 tstate1 tstate0 ovrie rxfie w 0x0146 can0tflg r00000 txe2 txe1 txe0 w 0x0147 can0tier r00000 txeie2 txeie1 txeie0 w 0x0148 can0tarq r00000 abtrq2 abtrq1 abtrq0 w 0x0149 can0taak r 0 0 0 0 0 abtak2 abtak1 abtak0 w 0x014a can0tbsel r00000 tx2 tx1 tx0 w 0x014b can0idac r0 0 idam1 idam0 0 idhit2 idhit1 idhit0 w 0x014c reserved r00000000 w 0x014d can0misc r0000000 bohold w 0x014e can0rxerr r rxerr7 rxerr6 rxerr5 rxerr4 rxerr3 rxerr2 rxerr1 rxerr0 w 0x014f can0txerr r txerr7 txerr6 txerr5 txerr4 txerr3 txerr2 txerr1 txerr0 w 0x0150- 0x0153 can0idar0- can0idar3 r ac7 ac6 ac5 ac4 ac3 ac2 ac1 ac0 w 0x0154- 0x0157 can0idmr0- can0idmr3 r am7 am6 am5 am4 am3 am2 am1 am0 w 0x0158- 0x015b can0idar4- can0idar7 r ac7 ac6 ac5 ac4 ac3 ac2 ac1 ac0 w 0x015c- 0x015f can0idmr4- can0idmr7 r am7 am6 am5 am4 am3 am2 am1 am0 w 0x0160- 0x016f can0rxfg r foreground receive buffer (see detailed mscan foreground receive and transmit buffer layout ) w 0x0170- 0x017f can0txfg r foreground transmit buffer (see detailed mscan foreground receive and transmit buffer layout ) w 0x0140?x017f mscan (can0) map (continued) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
detailed register address map s12xs family reference manual, rev. 1.10 724 freescale semiconductor detailed mscan foreground receive and transmit buffer layout address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0xxxx0 extended id r id28 id27 id26 id25 id24 id23 id22 id21 standard id r id10 id9 id8 id7 id6 id5 id4 id3 canxridr0 w 0xxxx1 extended id r id20 id19 id18 srr=1 ide=1 id17 id16 id15 standard id r id2 id1 id0 rtr ide=0 canxridr1 w 0xxxx2 extended id r id14 id13 id12 id11 id10 id9 id8 id7 standard id r canxridr2 w 0xxxx3 extended id r id6 id5 id4 id3 id2 id1 id0 rtr standard id r canxridr3 w 0xxxx4- 0xxxxb canxrdsr0- canxrdsr7 r db7 db6 db5 db4 db3 db2 db1 db0 w 0xxxxc canrxdlr r dlc3 dlc2 dlc1 dlc0 w 0xxxxd reserved r w 0xxxxe canxrtsrh r tsr15 tsr14 tsr13 tsr12 tsr11 tsr10 tsr9 tsr8 w 0xxxxf canxrtsrl r tsr7 tsr6 tsr5 tsr4 tsr3 tsr2 tsr1 tsr0 w 0xxx10 extended id r id28 id27 id26 id25 id24 id23 id22 id21 canxtidr0 w standard id r id10 id9 id8 id7 id6 id5 id4 id3 w 0xxx0x xx10 extended id r id20 id19 id18 srr=1 ide=1 id17 id16 id15 canxtidr1 w standard id r id2 id1 id0 rtr ide=0 w 0xxx12 extended id r id14 id13 id12 id11 id10 id9 id8 id7 canxtidr2 w standard id r w 0xxx13 extended id r id6 id5 id4 id3 id2 id1 id0 rtr canxtidr3 w standard id r w 0xxx14- 0xxx1b canxtdsr0 canxtdsr7 r db7 db6 db5 db4 db3 db2 db1 db0 w 0xxx1c canxtdlr r dlc3 dlc2 dlc1 dlc0 w 0xxx1d canxttbpr r prio7 prio6 prio5 prio4 prio3 prio2 prio1 prio0 w 0xxx1e canxttsrh r tsr15 tsr14 tsr13 tsr12 tsr11 tsr10 tsr9 tsr8 w
detailed register address map s12xs family reference manual, rev. 1.10 freescale semiconductor 725 0xxx1f canxttsrl r tsr7 tsr6 tsr5 tsr4 tsr3 tsr2 tsr1 tsr0 w 0x0180?x023f reserved register space address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x0180- 0x023f reserved r00000000 w 0x0240?x027f port integration module (pim) map 5 of 5 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x0240 ptt r ptt7 ptt6 ptt5 ptt4 ptt3 ptt2 ptt1 ptt0 w 0x0241 ptit r ptit7 ptit6 ptit5 ptit4 ptit3 ptit2 ptit1 ptit0 w 0x0242 ddrt r ddrt7 ddrt6 ddrt5 ddrt4 ddrt3 ddrt2 ddrt1 ddrt0 w 0x0243 rdrt r rdrt7 rdrt6 rdrt5 rdrt4 rdrt3 rdrt2 rdrt1 rdrt0 w 0x0244 pert r pert7 pert6 pert5 pert4 pert3 pert2 pert1 pert0 w 0x0245 ppst r ppst7 ppst6 ppst5 ppst4 ppst3 ppst2 ppst1 ppst0 w 0x0246 reserved r00000000 w 0x0247 pttrr r pttrr7 pttrr6 pttrr5 pttrr4 0 pttrr2 pttrr1 pttrr0 w detailed mscan foreground receive and transmit buffer layout (continued) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
detailed register address map s12xs family reference manual, rev. 1.10 726 freescale semiconductor 0x0248 pts r pts7 pts6 pts5 pts4 pts3 pts2 pts1 pts0 w 0x0249 ptis r ptis7 ptis6 ptis5 ptis4 ptis3 ptis2 ptis1 ptis0 w 0x024a ddrs r ddrs7 ddrs6 ddrs5 ddrs4 ddrs3 ddrs2 ddrs1 ddrs0 w 0x024b rdrs r rdrs7 rdrs6 rdrs5 rdrs4 rdrs3 rdrs2 rdrs1 rdrs0 w 0x024c pers r pers7 pers6 pers5 pers4 pers3 pers2 pers1 pers0 w 0x024d ppss r ppss7 ppss6 ppss5 ppss4 ppss3 ppss2 ppss1 ppss0 w 0x024e woms r woms7 woms6 woms5 woms4 woms3 woms2 woms1 woms0 w 0x024f reserved r00000000 w 0x0250 ptm r ptm7 ptm6 ptm5 ptm4 ptm3 ptm2 ptm1 ptm0 w 0x0251 ptim r ptim7 ptim6 ptim5 ptim4 ptim3 ptim2 ptim1 ptim0 w 0x0252 ddrm r ddrm7 ddrm6 ddrm5 ddrm4 ddrm3 ddrm2 ddrm1 ddrm0 w 0x0253 rdrm r rdrm7 rdrm6 rdrm5 rdrm4 rdrm3 rdrm2 rdrm1 rdrm0 w 0x0254 perm r perm7 perm6 perm5 perm4 perm3 perm2 perm1 perm0 w 0x0255 ppsm r ppsm7 ppsm6 ppsm5 ppsm4 ppsm3 ppsm2 ppsm1 ppsm0 w 0x0256 womm r womm7 womm6 womm5 womm4 womm3 womm2 womm1 womm0 w 0x0257 modrr r modrr7 modrr6 0 modrr4 0000 w 0x0258 ptp r ptp7 ptp6 ptp5 ptp4 ptp3 ptp2 ptp1 ptp0 w 0x0259 ptip r ptip7 ptip6 ptip5 ptip4 ptip3 ptip2 ptip1 ptip0 w 0x025a ddrp r ddrp7 ddrp6 ddrp5 ddrp4 ddrp3 ddrp2 ddrp1 ddrp0 w 0x025b rdrp r rdrp7 rdrp6 rdrp5 rdrp4 rdrp3 rdrp2 rdrp1 rdrp0 w 0x025c perp r perp7 perp6 perp5 perp4 perp3 perp2 perp1 perp0 w 0x025d ppsp r ppsp7 ppsp6 ppsp5 ppsp4 ppsp3 ppsp2 ppsp1 ppss0 w 0x025e piep r piep7 piep6 piep5 piep4 piep3 piep2 piep1 piep0 w 0x025f pifp r pifp7 pifp6 pifp5 pifp4 pifp3 pifp2 pifp1 pifp0 w 0x0240?x027f port integration module (pim) map 5 of 5 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
detailed register address map s12xs family reference manual, rev. 1.10 freescale semiconductor 727 0x0260 pth r pth7 pth6 pth5 pth4 pth3 pth2 pth1 pth0 w 0x0261 ptih r ptih7 ptih6 ptih5 ptih4 ptih3 ptih2 ptih1 ptih0 w 0x0262 ddrh r ddrh7 ddrh6 ddrh5 ddrh4 ddrh3 ddrh2 ddrh1 ddrh0 w 0x0263 rdrh r rdrh7 rdrh6 rdrh5 rdrh4 rdrh3 rdrh2 rdrh1 rdrh0 w 0x0264 perh r perh7 perh6 perh5 perh4 perh3 perh2 perh1 perh0 w 0x0265 ppsh r ppsh7 ppsh6 ppsh5 ppsh4 ppsh3 ppsh2 ppsh1 ppsh0 w 0x0266 pieh r pieh7 pieh6 pieh5 pieh4 pieh3 pieh2 pieh1 pieh0 w 0x0267 pifh r pifh7 pifh6 pifh5 pifh4 pifh3 pifh2 pifh1 pifh0 w 0x0268 ptj r ptj7 ptj6 0000 ptj1 ptj0 w 0x0269 ptij r ptij7 ptij6 0000 ptij1 ptij0 w 0x026a ddrj r ddrj7 ddrj6 0000 ddrj1 ddrj0 w 0x026b rdrj r rdrj7 rdrj6 0000 rdrj1 rdrj0 w 0x026c perj r perj7 perj6 0000 perj1 perj0 w 0x026d ppsj r ppsj7 ppsj6 0000 ppsj1 ppsj0 w 0x026e piej r piej7 piej6 0000 piej1 piej0 w 0x026f pifj r pifj7 pifj6 0000 pifj1 pifj0 w 0x0270 pt0ad0 r pt0ad0 7 pt0ad0 6 pt0ad0 5 pt0ad0 4 pt0ad0 3 pt0ad0 2 pt0ad0 1 pt0ad0 0 w 0x0271 pt1ad0 r pt1ad0 7 pt1ad0 6 pt1ad0 5 pt1ad0 4 pt1ad0 3 pt1ad0 2 pt1ad0 1 pt1ad0 0 w 0x0272 ddr0ad0 r ddr0ad0 7 ddr0ad0 6 ddr0ad0 5 ddr0ad0 4 ddr0ad0 3 ddr0ad0 2 ddr0ad0 1 ddr0ad0 0 w 0x0273 ddr1ad0 r ddr1ad0 7 ddr1ad0 6 ddr1ad0 5 ddr1ad0 4 ddr1ad0 3 ddr1ad0 2 ddr1ad0 1 ddr1ad0 0 w 0x0274 rdr0ad0 r rdr0ad0 7 rdr0ad0 6 rdr0ad0 5 rdr0ad0 4 rdr0ad0 3 rdr0ad0 2 rdr0ad0 1 rdr0ad0 0 w 0x0275 rdr1ad0 r rdr1ad0 7 rdr1ad0 6 rdr1ad0 5 rdr1ad0 4 rdr1ad0 3 rdr1ad0 2 rdr1ad0 1 rdr1ad0 0 w 0x0240?x027f port integration module (pim) map 5 of 5 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
detailed register address map s12xs family reference manual, rev. 1.10 728 freescale semiconductor 0x0276 per0ad0 r per0ad0 7 per0ad0 6 per0ad0 5 per0ad0 4 per0ad0 3 per0ad0 2 per0ad0 1 per0ad0 0 w 0x0277 per1ad0 r per1ad0 7 per1ad0 6 per1ad0 5 per1ad0 4 per1ad0 3 per1ad0 2 per1ad0 1 per1ad0 0 w 0x0278- 0x027f reserved r00000000 w 0x0280?x02bf reserved register space address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x0280- 0x02bf reserved r00000000 w 0x02c0?x02ef analog-to-digital converter 12-bit 16-channel (atd0) map address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x02c0 atd0ctl0 r0 0 0 0 wrap3 wrap2 wrap1 wrap0 w 0x02c1 atd0ctl1 r etrig sel sres1 sres0 smp_dis etrig ch3 etrig ch2 etrig ch1 etrig ch0 w 0x02c2 atd0ctl2 r0 affc iclkstp etrigle etrigp etrige ascie acmpie w 0x02c3 atd0ctl3 r djm s8c s4c s2c s1c fifo frz1 frz0 w 0x02c4 atd0ctl4 r smp2 smp1 smp0 prs4 prs3 prs2 prs1 prs0 w 0x02c5 atd0ctl5 r0 sc scan mult cd cc cb ca w 0x02c6 atd0stat0 r scf 0 etorf fifor cc3 cc2 cc1 cc0 w 0x02c7 reserved r00000000 w 0x02c8 atd0cmpeh r cmpe15 cmpe14 cmpe13 cmpe12 cmpe11 cmpe10 cmpe9 cmpe8 w 0x02c9 atd0cmpel r cmpe7 cmpe6 cmpe5 cmpe4 cmpe3 cmpe2 cmpe1 cmpe0 w 0x02ca atd0stat2h r ccf15 ccf14 ccf13 ccf12 ccf11 ccf10 ccf9 ccf8 w 0x02cb atd0stat2l r ccf7 ccf6 ccf5 ccf4 ccf3 ccf2 ccf1 ccf0 w 0x02cc atd0dienh r ien15 ien14 ien13 ien12 ien11 ien10 ien9 ien8 w 0x02cd atd0dienl r ien7 ien6 ien5 ien4 ien3 ien2 ien1 ien0 w 0x02ce atd0cmphth r cmpht15 cmpht14 cmpht13 cmpht12 cmpht11 cmpht10 cmpht9 cmpht8 w 0x0240?x027f port integration module (pim) map 5 of 5 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
detailed register address map s12xs family reference manual, rev. 1.10 freescale semiconductor 729 0x02cf atd0cmphtl r cmpht7 cmpht6 cmpht5 cmpht4 cmpht3 cmpht2 cmpht1 cmpht0 w 0x02d0 atd0dr0h r bit15 14 13 12 11 10 9 bit8 w 0x02d1 atd0dr0l r bit7 bit6 000000 w 0x02d2 atd0dr1h r bit15 14 13 12 11 10 9 bit8 w 0x02d3 atd0dr1l r bit7 bit6 000000 w 0x02d4 atd0dr2h r bit15 14 13 12 11 10 9 bit8 w 0x02d5 atd0dr2l r bit7 bit6 000000 w 0x02d6 atd0dr3h r bit15 14 13 12 11 10 9 bit8 w 0x02d7 atd0dr3l r bit7 bit6 000000 w 0x02d8 atd0dr4h r bit15 14 13 12 11 10 9 bit8 w 0x02d9 atd0dr4l r bit7 bit6 000000 w 0x02da atd0dr5h r bit15 14 13 12 11 10 9 bit8 w 0x02db atd0dr5l r bit7 bit6 000000 w 0x02dc atd0dr6h r bit15 14 13 12 11 10 9 bit8 w 0x02dd atd0dr6l r bit7 bit6 000000 w 0x02de atd0dr7h r bit15 14 13 12 11 10 9 bit8 w 0x02df atd0dr7l r bit7 bit6 000000 w 0x02e0 atd0dr8h r bit15 14 13 12 11 10 9 bit8 w 0x02e1 atd0dr8l r bit7 bit6 000000 w 0x02e2 atd0dr9h r bit15 14 13 12 11 10 9 bit8 w 0x02e3 atd0dr9l r bit7 bit6 000000 w 0x02e4 atd0dr10h r bit15 14 13 12 11 10 9 bit8 w 0x02e5 atd0dr10l r bit7 bit6 000000 w 0x02c0?x02ef analog-to-digital converter 12-bit 16-channel (atd0) map (continued) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
detailed register address map s12xs family reference manual, rev. 1.10 730 freescale semiconductor 0x02e6 atd0dr11h r bit15 14 13 12 11 10 9 bit8 w 0x02e7 atd0dr11l r bit7 bit6 000000 w 0x02e8 atd0dr12h r bit15 14 13 12 11 10 9 bit8 w 0x02e9 atd0dr12l r bit7 bit6 000000 w 0x02ea atd0dr13h r bit15 14 13 12 11 10 9 bit8 w 0x02eb atd0dr13l r bit7 bit6 000000 w 0x02ec atd0dr14h r bit15 14 13 12 11 10 9 bit8 w 0x02ed atd0dr14l r bit7 bit6 000000 w 0x02ee atd0dr15h r bit15 14 13 12 11 10 9 bit8 w 0x02ef atd0dr15l r bit7 bit6 000000 w 0x02f0?x02f7 voltage regulator (vreg_3v3) map address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x02f0 vreghtcl r0 0 vsel vae hten htds htie htif w 0x02f1 vregctrl r00000lvds lvie lvif w 0x02f2 vregapicl r apiclk 00 apifes apiea apife apie apif w 0x02f3 vregapitr r apitr5 apitr4 apitr3 apitr2 apitr1 apitr0 00 w 0x02f4 vregapirh r apir15 apir14 apir13 apir12 apir11 apir10 apir9 apir8 w 0x02f5 vregapirl r apir7 apir6 apir5 apir4 apir3 apir2 apir1 apir0 w 0x02f6 reserved r00000000 w 0x02f7 vreghttr r htoen 000 httr3 httr2 httr1 httr0 w 0x02f8?x02ff reserved address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x02f8 0x02ff reserved r00000000 w 0x02c0?x02ef analog-to-digital converter 12-bit 16-channel (atd0) map (continued) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
detailed register address map s12xs family reference manual, rev. 1.10 freescale semiconductor 731 0x0300?x0327 pulse width modulator 8-bit 8-channel (pwm) map address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x0300 pwme r pwme7 pwme6 pwme5 pwme4 pwme3 pwme2 pwme1 pwme0 w 0x0301 pwmpol r ppol7 ppol6 ppol5 ppol4 ppol3 ppol2 ppol1 ppol0 w 0x0302 pwmclk r pclk7 pclk6 pclk5 pclk4 pclk3 pclk2 pclk1 pclk0 w 0x0303 pwmprclk r0 pckb2 pckb1 pckb0 0 pcka2 pcka1 pcka0 w 0x0304 pwmcae r cae7 cae6 cae5 cae4 cae3 cae2 cae1 cae0 w 0x0305 pwmctl r con67 con45 con23 con01 pswai pfrz 00 w 0x0306 pwmtst test only r00000000 w 0x0307 pwmprsc r00000000 w 0x0308 pwmscla r bit 7 6 5 4 3 2 1 bit 0 w 0x0309 pwmsclb r bit 7 6 5 4 3 2 1 bit 0 w 0x030a pwmscnta r00000000 w 0x030b pwmscntb r00000000 w 0x030c pwmcnt0 r bit 7 6 5 4 3 2 1 bit 0 w00000000 0x030d pwmcnt1 r bit 7 6 54321 bit 0 w00000000 0x030e pwmcnt2 r bit 7 6 54321 bit 0 w00000000 0x030f pwmcnt3 r bit 7 6 54321 bit 0 w00000000 0x0310 pwmcnt4 r bit 7 6 54321 bit 0 w00000000 0x0311 pwmcnt5 r bit 7 6 54321 bit 0 w00000000 0x0312 pwmcnt6 r bit 7 6 54321 bit 0 w00000000 0x0313 pwmcnt7 r bit 7 6 54321 bit 0 w00000000 0x0314 pwmper0 r bit 7 6 5 4 3 2 1 bit 0 w 0x0315 pwmper1 r bit 7 6 5 4 3 2 1 bit 0 w 0x0316 pwmper2 r bit 7 6 5 4 3 2 1 bit 0 w
detailed register address map s12xs family reference manual, rev. 1.10 732 freescale semiconductor 0x0317 pwmper3 r bit 7 6 5 4 3 2 1 bit 0 w 0x0318 pwmper4 r bit 7 6 5 4 3 2 1 bit 0 w 0x0319 pwmper5 r bit 7 6 5 4 3 2 1 bit 0 w 0x031a pwmper6 r bit 7 6 5 4 3 2 1 bit 0 w 0x031b pwmper7 r bit 7 6 5 4 3 2 1 bit 0 w 0x031c pwmdty0 r bit 7 6 5 4 3 2 1 bit 0 w 0x031d pwmdty1 r bit 7 6 5 4 3 2 1 bit 0 w 0x031e pwmdty2 r bit 7 6 5 4 3 2 1 bit 0 w 0x031f pwmdty3 r bit 7 6 5 4 3 2 1 bit 0 w 0x0320 pwmdty4 r bit 7 6 5 4 3 2 1 bit 0 w 0x0321 pwmdty5 r bit 7 6 5 4 3 2 1 bit 0 w 0x0322 pwmdty6 r bit 7 6 5 4 3 2 1 bit 0 w 0x0323 pwmdty7 r bit 7 6 5 4 3 2 1 bit 0 w 0x0324 pwmsdn r pwmif pwmie 0 pwmlvl 0 pwm7in pwm7inl pwm7 ena w pwm rstrt 0x0325 reserved r00000000 w 0x0326 reserved r00000000 w 0x0327 reserved r00000000 w 0x0328?x033f reserved address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x0328 0x033f reserved r00000000 w 0x0300?x0327 pulse width modulator 8-bit 8-channel (pwm) map address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
detailed register address map s12xs family reference manual, rev. 1.10 freescale semiconductor 733 0x00340?x0367 ?periodic interrupt timer (pit) map address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x0340 pitcflmt r pite pitswai pitfrz 00000 w pflmt1 pflmt0 0x0341 pitflt r00000000 w pflt3 pflt2 pflt1 pflt0 0x0342 pitce r0000 pce3 pce2 pce1 pce0 w 0x0343 pitmux r0000 pmux3 pmux2 pmux1 pmux0 w 0x0344 pitinte r0000 pinte3 pinte2 pinte1 pinte0 w 0x0345 pittf r0000 ptf3 ptf2 ptf1 ptf0 w 0x0346 pitmtld0 r pmtld7 pmtld6 pmtld5 pmtld4 pmtld3 pmtld2 pmtld1 pmtld0 w 0x0347 pitmtld1 r pmtld7 pmtld6 pmtld5 pmtld4 pmtld3 pmtld2 pmtld1 pmtld0 w 0x0348 pitld0 (hi) r pld15 pld14 pld13 pld12 pld11 pld10 pld9 pld8 w 0x0349 pitld0 (lo) r pld7 pld6 pld5 pld4 pld3 pld2 pld1 pld0 w 0x034a pitcnt0 (hi) r pcnt15 pcnt14 pcnt13 pcnt12 pcnt11 pcnt10 pcnt9 pcnt8 w 0x034b pitcnt0 (lo) r pcnt7 pcnt6 pcnt5 pcnt4 pcnt3 pcnt2 pcnt1 pcnt0 w 0x034c pitld1 (hi) r pld15 pld14 pld13 pld12 pld11 pld10 pld9 pld8 w 0x034d pitld1 (lo) r pld7 pld6 pld5 pld4 pld3 pld2 pld1 pld0 w 0x034e pitcnt1 (hi) r pcnt15 pcnt14 pcnt13 pcnt12 pcnt11 pcnt10 pcnt9 pcnt8 w 0x034f pitcnt1 (lo) r pcnt7 pcnt6 pcnt5 pcnt4 pcnt3 pcnt2 pcnt1 pcnt0 w 0x0350 pitld2 (hi) r pld15 pld14 pld13 pld12 pld11 pld10 pld9 pld8 w 0x0351 pitld2 (lo) r pld7 pld6 pld5 pld4 pld3 pld2 pld1 pld0 w 0x0352 pitcnt2 (hi) r pcnt15 pcnt14 pcnt13 pcnt12 pcnt11 pcnt10 pcnt9 pcnt8 w 0x0353 pitcnt2 (lo) r pcnt7 pcnt6 pcnt5 pcnt4 pcnt3 pcnt2 pcnt1 pcnt0 w 0x0354 pitld3 (hi) r pld15 pld14 pld13 pld12 pld11 pld10 pld9 pld8 w 0x0355 pitld3 (lo) r pld7 pld6 pld5 pld4 pld3 pld2 pld1 pld0 w
detailed register address map s12xs family reference manual, rev. 1.10 734 freescale semiconductor 0x0356 pitcnt3 (hi) r pcnt15 pcnt14 pcnt13 pcnt12 pcnt11 pcnt10 pcnt9 pcnt8 w 0x0357 pitcnt3 (lo) r pcnt7 pcnt6 pcnt5 pcnt4 pcnt3 pcnt2 pcnt1 pcnt0 w 0x0358 0x0367 reserved r00000000 w 0x0368?x077f reserved address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x0368 reserved r00000000 w address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
ordering information s12xs family reference manual, rev. 1.10 freescale semiconductor 735 appendix f ordering information f.1 ordering information the following ?ure provides an ordering part number example for the devices covered by this data book. there are two options when ordering a device. customers must choose between ordering either the mask- speci? part number or the generic / mask-independent part number. ordering the mask-speci? part number enables the customer to specify which particular maskset they will receive whereas ordering the generic maskset means that fsl will ship the currently preferred maskset (which may change over time). in either case, the marking on the device will always show the generic / mask-independent peritoneums and the mask set number. note the mask identi?r suf? and the tape & reel suf? are always both omitted from the part number which is actually marked on the device. for speci? part numbers to order, please contact your local sales of?e. the below ?ure illustrates the structure of a typical mask-speci? ordering number for the s12xs family devices. figure f-1. order part number example s 9 s12x s256 j1 c al r package option: temperature option: device title controller family c = -40?c to 85?c v = -40?c to 105?c m = -40?c to 125?c ae = 64 lqfp aa = 80 qfp al = 112 lqfp status / partnumber type: s or sc = maskset specific part number mc = generic / mask-independent part number p or pc = prototype status (pre qualification) main memory type: 9 = flash maskset identifier suffix: first digit usually references wafer fab second digit usually differentiates mask rev (this suffix is omitted in generic part numbers) tape & reel: r = tape & reel no r = no tape & reel
ordering information s12xs family reference manual, rev. 1.10 736 freescale semiconductor

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